Patent Application
20250141415
This description relates generally to amplifiers and, more particularly, to methods and apparatus to dynamically increase amplifier slew rates.
As electronics continue to advance, systems need to be capable of safely operating at increasingly higher powers and higher speeds. In amplifier circuitry, increasingly complex circuitry handles higher output voltages, output currents, and operating speeds. Such circuitry allows the amplifier circuitry to safely support a wide range of operating conditions.
For methods and apparatus to dynamically increase amplifier slew rates, an example apparatus includes a first transistor having a first terminal and a control terminal; a second transistor having a first terminal and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor; a third transistor having a first terminal and a control terminal; a fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the third transistor; feedback circuitry coupled to the first transistor, the second transistor, the third transistor and the fourth transistor; current source circuitry having a first terminal and a second terminal, the first terminal of the current source circuitry coupled to the feedback circuitry; slew assist circuitry coupled to the first transistor, the second transistor, the third transistor and the fourth transistor, the feedback circuitry and the current source circuitry; and current mirror circuitry coupled to the slew assist circuitry. Other examples are described.
For methods and apparatus to dynamically increase amplifier slew rates, an example apparatus includes a first transistor having a first input; a second transistor having a second input; input transistor circuitry coupled to the first transistor and the second transistor, the input transistor circuitry having a first output and a second output; slew assist circuitry coupled to the first transistor, the second transistor, and the input transistor circuitry, the slew assist circuitry having a first output and a second output; and output stage circuitry coupled to the input transistor circuitry and slew assist circuitry, the output stage circuitry having an output where a slew rate of a voltage on the output is based on a voltage on the first output of the slew assist circuitry and a voltage on the second output of the slew assist circuitry. Other examples are described.
For methods and apparatus to dynamically increase amplifier slew rates, an example apparatus includes feedback circuitry; current source circuitry having a first terminal and a second terminal, the first terminal of the current source circuitry is coupled to the feedback circuitry; a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal; a third transistor a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the current source circuitry and the first transistor; a fourth transistor a first terminal, a second terminal, and a control terminal; a fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor coupled to the third transistor and the fourth transistor, the control terminal of the fifth transistor coupled to the feedback circuitry, the first transistor, and the second transistor; a sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor coupled to the first transistor and the second transistor, the control terminal of the sixth transistor coupled to the feedback circuitry, the third transistor, and the fourth transistor; and current mirror circuitry coupled to the second transistor and the fourth transistor. Other examples are described.
The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or similar (functionally and/or structurally) features and/or parts. Although the drawings show regions with clean lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, blended or irregular.
As electronics continue to advance, systems need to be capable of safely operating at increasingly higher powers and higher speeds. In amplifier circuitry, increasingly complex circuitry handles higher output voltages, output currents, and operating speeds. Such circuitry allows the amplifier circuitry to safely support a wide range of operating conditions.
When amplifier circuitry supports dynamic range rail-to-rail output voltages, an output signal of the amplifier circuitry may have a voltage between a high-side supply voltage (e.g., supply voltage) and a low-side supply voltage (e.g., reference voltage). In such designs, the high-side supply voltage is referred to as a first rail and the low-side supply voltage is referred to as a second rail. In dynamic amplifier designs, one or both of the rails may dynamically change (also referred to as floating) responsive to changes in the system, such as changes in a common mode voltage or an input voltage. In high-voltage devices, the first and second supply voltages of the amplifier circuitry become increasingly farther apart. In 85-volt (V) systems, for example, the amplifier circuitry may generate an output voltage across a range of 85 volts. In some such systems, the amplifier circuitry is structured to have up to an 85-volt change at the output. Such relatively large changes at the output of the amplifier circuitry increase the time during which the amplifier circuitry is in a transient condition. A transient condition is an operating state occurring when the amplifier circuitry is transitioning from a first output voltage to a second output voltage. When in the transient condition, the output of the amplifier circuitry inaccurately reflects an input. An ideal amplifier instantaneously adjusts the output responsive to the input voltage. However, delays and settling times of amplifier circuitry result in durations of time during which the amplifier circuitry is operating in the transient condition.
A speed at which an amplifier circuitry adjusts an output in response to an input change is characterized as a slew rate. The slew rate is a measure of voltage per unit of time at which the amplifier circuitry can adjust the output (e.g., millivolts/second). Increasing the slew rate of the amplifier circuitry decreases the duration of transient operations, which increases the bandwidth of the amplifier circuitry.
Some amplifier circuitry includes high-voltage input switches, input transistor circuitry, feedback circuitry, and output stage circuitry. One method to increase the slew rate of amplifier circuitry is to increase the current of the signal path. The main signal path through the amplifier circuitry begins at the high-voltage switches, which receive first and second inputs of the amplifier circuitry. The high-voltage switches may be implemented using high-voltage transistors. The high-voltage switches control relatively low voltage transistors of the input transistor circuitry, which generate an intermediate signal path output using a tail current source, which represents the first and second inputs. In such designs the high-voltage switches protect transistors of the input transistor circuitry from high voltages of the first and second inputs.
During steady state operating conditions (e.g., no transient at the inputs of the amplifier circuitry), the output stage circuitry generates an output signal responsive to the intermediate signal path outputs. In some designs, the feedback circuitry generates a feedback current responsive to transients at the first and second inputs of the amplifier circuitry. The feedback circuitry uses the feedback current to pull down a control voltage, which increases the tail currents of the intermediate signal path outputs. During slew event conditions (e.g., a transient at the inputs of the amplifier circuitry), increasing the tails currents of the intermediate signal path outputs increases the slew rate of setting the output signal. However, increasing the tail currents of the intermediate signal path outputs increases the overshoot of the output of the amplifier circuitry, which increases a small signal settling time of the amplifier circuitry. Such an increase in the small signal settling time negates at least a portion of the increased slew rate. Also, as the transient at the inputs of the amplifier circuitry settles, the feedback circuitry allows the control voltage to settle which sets the tail current back to the steady state value. However, when the tail current transitions from the increased tail current to a steady state tail current, a delay in the transition between currents can result in a relatively high transconductance. Thus, such delay creates stability issues that further increase the settling time of the amplifier circuitry.
Examples described herein include methods and apparatus to dynamically increase amplifier slew rates using slew assist circuitry. In some described examples, the amplifier circuitry includes first current source circuitry, input transistor circuitry, feedback circuitry, slew assist circuitry, second current source circuitry, current mirror circuitry, driver circuitry, and power stage circuitry. The amplifier circuitry receives a first input signal at a first transistor and a second input signal at a second transistor. The first and second transistors cause the input transistor circuitry to generate intermediate signal path outputs based on values of the first and second input signals and a set current from the first current source circuitry. The driver circuitry generates high-side and low side control signals based on the intermediate signal path outputs. The power stage circuitry generates an output signal by using the high-side and low-side control signals to control a high-side and low-side transistor.
In the described examples, during steady state operating conditions (e.g., no transient at the inputs of the amplifier circuitry), the slew assist circuitry steers a slew assist current from the second current source circuitry to a common terminal, which supplies the common potential. During steady state operating conditions, the slew assist circuitry uses a cross-coupled pair of transistors that implement a cascode bias (e.g., one relatively large transistor cross coupled with a relatively small transistor) to further reduce current from the second current source from entering the main signal path. Such a method of control is referred to as minimum selector cascodes.
During slew event conditions (e.g., a transient at the inputs of the amplifier circuitry), the feedback circuitry generates a feedback current responsive to the transient. The feedback circuitry uses the feedback current to pull down a control voltage, which increases the slew assist current from the second current source circuitry. In some described examples, the current mirror circuitry sinks a mirror of the slew assist current to increase the speed at which the feedback circuitry pulls down the control voltage. Also, in some examples clamp circuitry prevents the current mirror circuitry from sinking the slew assist current during steady state conditions. During the slew event conditions, the slew assist circuitry turns on a first pair of transistors form a first current path, which supplies the increased slew assist current to the current mirror circuitry. Also, during the slew event conditions, the slew assist circuitry forms a second current path from a second pair of transistors to the common potential by turning on a transistor of cross-coupled cascode to steer non-ideal currents. In such operations, the transistor of the cross-coupled cascode reduces a supply of non-ideal current by the second pair of transistors.
The current mirror circuitry receives the slew assist current at one of a first or second output of the slew assist circuitry. The current mirror circuitry generates a first bias voltage responsive to currents at the first output of the slew assist circuitry and a second bias voltage responsive to currents at the second output of the slew assist circuitry. The power stage circuitry receives the first or second bias voltage from the current mirror circuitry. The first bias voltage causes the power stage circuitry to sink current from the low-side transistor by mirroring the slew assist current. Sinking current from the low-side transistor increases the slew rate of rising edges at the output of the amplifier circuitry. The second bias voltage causes the power stage circuitry to supply current to the high-side transistor by mirroring the slew assist current. Supplying current to the high-side transistor increases the slew rate of falling edges at the output of the amplifier circuitry.
Advantageously, supplying current to the high-side transistor increases the slew rate of the amplifier circuitry for generating falling edges on the output signal. Advantageously, sinking current from the low-side transistor increases the slew rate of the amplifier circuitry for generating rising edges on the output signal. Advantageously, the slew assist circuitry increases the slew rate of the amplifier circuitry without increasing the current of the intermediate signal path outputs. Advantageously, decreasing the currents of the intermediate signal path outputs decreases overshoot of the output signal of the amplifier circuitry, which decreases a small signal settling time of the output signal. Advantageously, as the amplifier circuitry recovers from slew event conditions, the slew assist circuitry uses a cascode bias and minimum selector control to steer non-ideal currents from the main signal path.
The amplifier circuitry 100 has a first input terminal, a second input terminal, and an output terminal. The first and second input terminals are structured to be coupled to external circuitry, which supplies a first input (IN1) and a second input (IN2). In some examples, the first and second inputs represent a differential pair of input signals. Transients at the first and second inputs represent transitions in data of the differential pair of input signals. In such examples, when the inputs switch from one logic level (e.g., logic one, logic zero) to another, the amplifier circuitry 100 transitions an output voltage (VOUT) at the output terminal. In the example of
The input stage circuitry 105 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first and second terminals of the input stage circuitry 105 are structured to be coupled to external circuitry, which supplies the first and second inputs of the amplifier circuitry 100. The second, third, fourth, and fifth terminals of the input stage circuitry 105 are coupled to the output stage circuitry 110. Examples of the input stage circuitry 105 are illustrated and described in connection with
The output stage circuitry 110 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first, second, third, and fourth terminals of the output stage circuitry 110 are coupled to the input stage circuitry 105. The fifth terminal of the output stage circuitry 110 is structured to be coupled to external circuitry. Such external circuitry is structured to receive the output of the amplifier circuitry 100.
The driver circuitry 115 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the driver circuitry 115 are coupled to the input stage circuitry 105. The second and third terminals of the driver circuitry 115 are coupled to the power stage circuitry 120. In the example of
The power stage circuitry 120 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first and second terminals of the power stage circuitry 120 are coupled to the input stage circuitry 105. The third and fourth terminals of the power stage circuitry 120 are coupled to the driver circuitry 115. The fifth terminal of the power stage circuitry 120 is structured to be coupled to external circuitry, which receives the output of the amplifier circuitry 100. In the example of
The transistor 125 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 125 is coupled to the capacitors 130, 155, the transistor 150, and the output terminal of the amplifier circuitry 100. The second terminal of the transistor 125 is coupled to the common terminal, which supplies a common potential (e.g., ground, AVSS, etc.). The control terminal of the transistor 125 is coupled to the driver circuitry 115, the capacitor 130, and the transistors 135, 145, 175. In some examples, the transistor 125 is referred to as a low-side field-effect transistor (FET). In such examples, the driver circuitry 115 controls the transistor 125 using a low-side control signal.
The capacitor 130 has a first terminal and a second terminal. The first terminal of the capacitor 130 is coupled to the driver circuitry 115 and the transistors 125, 145. The second terminal of the capacitor 130 is coupled to the transistors 125, 150, 175, the capacitor 155, and the output terminal of the amplifier circuitry 100. In the example of
The transistor 135 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 135 is coupled to the driver circuitry 115, the transistors 125, 145, 175, and the capacitor 130. The second terminal of the transistor 135 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 135 is coupled to the input stage circuitry 105, which supplies a second bias voltage (Bias2). In the example of
The voltage source circuitry 140 has a first terminal and a second terminal. The first terminal of the voltage source circuitry 140 is coupled to the transistor 145. The second terminal of the voltage source circuitry 140 is coupled to the common terminal, which supplies the common potential. In the example of
The transistor 150 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 150 is coupled to a supply terminal, which supplies a supply voltage (VDD). The second terminal of the transistor 150 is coupled to the transistor 125, the capacitors 130, 155, and the output terminal of the amplifier circuitry 100. The control terminal of the transistor 150 is coupled to the driver circuitry 115, the transistors 145, 170, 175, and the capacitor 155. In some examples, the transistor 150 is referred to as a high-side field-effect transistor (FET). In such examples, the driver circuitry 115 controls the transistor 150 using a high-side control signal.
The capacitor 155 has a first terminal and a second terminal. The first terminal of the capacitor 155 is coupled to the transistors 125, 150, the capacitor 130, and the output terminal of the amplifier circuitry 100. The second terminal of the capacitor 155 is coupled to the driver circuitry 115 and the transistors 145, 150, 170, 175. In the example of
The transistor 160 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 160 is coupled to the transistors 165, 170. The second terminal of the transistor 160 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 160 is coupled to the input stage circuitry 105, which supplies a first bias voltage (Bias 1). In the example of
The transistor 165 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 165 is coupled to the supply terminal, which supplies the supply voltage. The second and control terminals of the transistor 165 are coupled to the transistors 160, 170. The transistor 170 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 170 is coupled to the supply terminal, which supplies the supply voltage. The second terminal of the transistor 170 is coupled to the driver circuitry 115, the transistors 145, 150, 175, and the capacitor 155. The control terminal of the transistor 170 is coupled to the transistors 160, 165.
In the example of
The transistor 175 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 175 is coupled to the driver circuitry 115, the transistors 125, 135, 145, and the capacitor 130. The second terminal of the transistor 175 is coupled to the driver circuitry 115, the transistors 145, 150, 170, and the capacitor 155. The control terminal of the transistor 175 is coupled to the voltage source circuitry 180. The voltage source circuitry 180 has a first terminal and a second terminal. The first terminal of the voltage source circuitry 180 is coupled to the supply terminal, which supplies the supply voltage. The second terminal of the voltage source circuitry 180 is coupled to the transistor 175.
In the example of
In example operation, the input stage circuitry 105 receives the first and second inputs from external circuitry. The input stage circuitry 105 generates first and second intermediate signal path outputs (INTOUT1, INTOUT2) responsive to the first and second inputs (IN1, IN2). The driver circuitry 115 generates the high-side and low-side control signals (CNTRLHI, CNTRLLOW) based on the first and second intermediate signal path outputs. The power stage circuitry 120 generates the output (VOUT) of the amplifier circuitry 100 by using the high-side control signal to control the transistor 150 and the low-side control signal to control the transistor 125.
In such example operations, the input stage circuitry 105 generates the first and second bias voltages (VBIAS1, VBIAS2) responsive to determining a transient at the first and second inputs of the amplifier circuitry 100. The power stage circuitry 120 uses the first bias voltage to control the transistor 160. The transistors 165, 170 mirror the current through the transistor 160 to supply a current to the transistor 150, which compensates for excess charges of the capacitor 155. The power stage circuitry 120 uses the second bias voltage to control the transistor 135, which sinks a current from the transistor 125 and compensates for excess charges of the capacitor 130. Advantageously, the first and second bias voltages control a supply of current to or from the capacitors 130, 155, which adjusts the slew rate of the amplifier circuitry 100. Advantageously, supplying current to the transistor 150 increases the slew rate of falling edges at the output of the amplifier circuitry 100. Advantageously, sinking current from the transistor 125 increases the slew rate of rising edges at the output of the amplifier circuitry 100. Example operations of the input stage circuitry 105 to generate the intermediate signal path outputs and the bias voltages are described further below.
The input stage circuitry 200 has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal of the input stage circuitry 200 is structured to be coupled to external circuitry, which supplies a first input (IN1). The second input terminal of the input stage circuitry 200 is structured to be coupled to external circuitry which supplies a second input (IN2). The first and second output terminals of the input stage circuitry 200 are structured to be coupled to the driver circuitry 115 of
The transistor 205 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 205 is coupled to the first input terminal of the input stage circuitry 200, which supplies the first input (IN1). The second terminal of the transistor 205 is coupled to the input transistor circuitry 220, the slew feedback circuitry, and the slew assist circuitry 240. The control terminal of the transistor 205 is coupled to the transistor 210, the feedback circuitry 230, the slew assist circuitry 240, and may be coupled to common mode regulator circuitry, which regulates a common mode voltage (VCM) of the input stage circuitry 200.
The transistor 210 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 210 is coupled to the second input terminal of the input stage circuitry 200, which supplies the second input (IN2). The second terminal of the transistor 210 is coupled to the input transistor circuitry 220, the feedback circuitry 230, and the slew assist circuitry 240. The control terminal of the transistor 210 is coupled to the transistor 205, the feedback circuitry 230, the slew assist circuitry 240, and may be coupled to common mode regulator circuitry, which regulates the common mode voltage of the input stage circuitry 200.
The current source circuitry 215 has a terminal coupled to the input transistor circuitry 220. An example of the current source circuitry 215 is illustrated and described in connection with
The input transistor circuitry 220 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the input transistor circuitry 220 is coupled to the current source circuitry 215. The second terminal of the input transistor circuitry 220 is coupled to the transistor 205, the feedback circuitry 230, and the slew assist circuitry 240. The third terminal of the input transistor circuitry 220 is coupled to the transistor 210, the feedback circuitry 230, and the slew assist circuitry 240. The fourth and fifth terminals of the input transistor circuitry 220 is coupled to the first output terminal of the input stage circuitry 200, which supplies the first and second intermediate signal path outputs (INTOUT1, INTOUT2) to the driver circuitry 110. In the example of
The bias circuitry 225 has a terminal coupled to the slew feedback circuitry. In the example of
The feedback circuitry 230 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the feedback circuitry 230 is coupled to the transistor 205, the input transistor circuitry 220, and the slew assist circuitry 240. The second terminal of the feedback circuitry 230 is coupled to the transistor 210, the input transistor circuitry 220, and the slew assist circuitry 240. The third terminal of the feedback circuitry 230 is coupled to the transistors 205, 210, the slew assist circuitry 240, and may be coupled to common mode regulator circuitry, which regulates the common mode voltage of the input stage circuitry 200. The fourth terminal of the feedback circuitry 230 is coupled to the bias circuitry 225. The fifth terminal of the feedback circuitry 230 is coupled to the current source circuitry 235. An example of the feedback circuitry 230 is illustrated and described in connection with
The current source circuitry 235 has a first terminal and a second terminal. The first terminal of the current source circuitry 235 is coupled to the feedback circuitry 230. The second terminal of the current source circuitry 235 is coupled to the slew assist circuitry 240. In the example of
The slew assist circuitry 240 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the slew assist circuitry 240 is coupled to the transistor 205, the input transistor circuitry 220, and the feedback circuitry 230. The second terminal of the slew assist circuitry 240 is coupled to the transistor 210, the input transistor circuitry 220, and the feedback circuitry 230. The third terminal of the slew assist circuitry 240 is coupled to the transistors 205, 210 and may be coupled to common mode regulator circuitry, which regulates the common mode voltage of the input stage circuitry 200. The fourth and fifth terminals of the slew assist circuitry 240 are coupled to the current mirror circuitry 245. An example of the slew assist circuitry 240 is illustrated and described in connection with
The current mirror circuitry 245 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the current mirror circuitry 245 are coupled to the slew assist circuitry 240. The third and fourth terminals of the current mirror circuitry 245 are coupled to the third and fourth output terminals of the input stage circuitry 200, which supply the first and second bias voltages (VBIAS1, VBIAS2) to the power stage circuitry 120 of
In the example of
In example operation, the input stage circuitry 200 receives the first and second inputs from external circuitry. The input transistor circuitry 220 generates first and second intermediate signal path outputs responsive to the first and second inputs. In such example operations, the current mirror circuitry 245 generates the first and second bias voltages to mirror currents of the slew assist circuitry 240. During steady state operations (e.g., no transients at the first and second inputs), the slew assist circuitry 240 steers slew assist current from the current source circuitry 235 away from the current mirror circuitry 245. However, during slew event operations (e.g., a transient at the first and second inputs), the feedback circuitry 230 generates a feedback current that pulls down a control voltage and increases the slew assist current of the current source circuitry 235. Also, during slew event operations, the slew assist circuitry 240 begins to supply current to the current mirror circuitry 245, which generates the first and second bias voltages. Advantageously, the first and second bias voltages represent the increased slew assist current of the slew assist circuitry 240 during slew event operations. Advantageously, the slew assist circuitry 240 dynamically increases the slew rate of the output stage circuitry 110 during slew event operations of the input stage circuitry 200. Example operations of the input stage circuitry 200 are described further below in connection with
The input stage circuitry 300 has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal of the input stage circuitry 300 is structured to be coupled to external circuitry, which supplies a first input (IN1). The second input terminal of the input stage circuitry 300 is structured to be coupled to external circuitry which supplies a second input (IN2). The first and second output terminals of the input stage circuitry 300 are structured to be coupled to the driver circuitry 115 of
The transistor 302 is coupled to the transistor 304, the input transistor circuitry 308, the feedback circuitry 312, the slew assist circuitry 316, and the first input terminal of the input stage circuitry 300, which supplies the first input (IN1) from external circuitry. The transistor 302 is an example of the transistor 205 of
The current source circuitry 306 is coupled to the input transistor circuitry 308 and a supply terminal, which supplies the supply voltage. The current source circuitry 306 is an example of the current source circuitry 215 of
The bias circuitry 310 is coupled to the feedback circuitry 312, the supply terminal, which supplies the supply voltage, and the common terminal, which supplies the common potential. The bias circuitry 310 is an example of the bias circuitry 225 of
The current source circuitry 314 is coupled to the feedback circuitry 312 and the slew assist circuitry 316. The current source circuitry 314 is an example of the current source circuitry 235 of
The transistor 320 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the transistor 320 is coupled to the current source circuitry 306 and the transistor 324. The second terminal of the transistor 320 is coupled to the transistor 322. The third terminal of the transistor 320 (also referred to as a bulk terminal) is coupled to the transistor 324 and may be coupled to common mode regulator circuitry, which regulates the common mode voltage (VCM) of the input stage circuitry 300. The control terminal of the transistor 320 is coupled to the transistors 302, 322, the feedback circuitry 312, and the slew assist circuitry 316. The transistor 322 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 322 is coupled to the transistor 320. The second terminal of the transistor 322 is coupled to the first output terminal of the input stage circuitry 300, which supplies the first intermediate output signal (INTOUT1) to the driver circuitry 115 of
The transistor 324 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the transistor 324 is coupled to the current source circuitry 306 and the transistor 320. The second terminal of the transistor 324 is coupled to the transistor 326. The third terminal of the transistor 324 (also referred to as a bulk terminal) is coupled to the transistor 320 and may be coupled to common mode regulator circuitry, which regulates a common mode voltage (VCM) of the input stage circuitry 300. The control terminal of the transistor 324 is coupled to the transistors 304, 326, the feedback circuitry 312, and the slew assist circuitry 316. The transistor 326 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 326 is coupled to the transistor 324. The second terminal of the transistor 326 is coupled to the second output terminal of the input stage circuitry 300, which supplies the second intermediate output signal (INTOUT2) to the driver circuitry 115, or more generally the output stage circuitry 110. The control terminal of the transistor 326 is coupled to the transistors 304, 324, the feedback circuitry 312, and the slew assist circuitry 316. The transistors 324, 326 are structured to generate a second intermediate signal path output based on the second input at the transistor 304.
The current source circuitry 328 has a first terminal and a second terminal. The first terminal of the current source circuitry 328 is coupled to the supply terminal, which supplies the supply voltage. The second terminal of the current source circuitry 328 is coupled to the feedback circuitry 312 and the transistor 330. The transistor 330 has a first terminal, a second terminal, and a control terminal. The first and control terminals of the transistor 330 are coupled to the feedback circuitry 312 and the current source circuitry 328. The second terminal of the transistor 330 is coupled to the resistor 332. The resistor 332 has a first terminal and a second terminal. The first terminal of the resistor 332 is coupled to the transistor 330. The second terminal of the resistor 332 is coupled to the common terminal, which supplies the common potential. In some examples, the resistor 332 is structured as a current limiting resistor, which limits a flow of current through the transistor 330. In the example of
The transistor 334 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 334 is coupled to the current source circuitry 314, the transistors 338, 346, the current source circuitry 342, and the capacitor 344. The second terminal of the transistor 334 is coupled to the resistor 336 and the transistor 360. The control terminal of the transistor 334 is coupled to the bias circuitry 310 and the transistor 338. The resistor 336 has a first terminal and a second terminal. The first terminal of the resistor 336 is coupled to the transistors 334, 360. The second terminal of the resistor 336 is coupled to the common terminal, which supplies the common potential. In the example of
The transistor 338 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 338 is coupled to the current source circuitry 314, the transistors 334, 346, the current source circuitry 342, and the capacitor 344. The second terminal of the transistor 338 is coupled to the resistor 340 and the transistor 354. The control terminal of the transistor 338 is coupled to the bias circuitry 310 and the transistor 334. The resistor 340 has a first terminal and a second terminal. The first terminal of the resistor 340 is coupled to the transistors 338, 354. The second terminal of the resistor 340 is coupled to the common terminal, which supplies the common potential. In the example of
The current source circuitry 342 has a first terminal and a second terminal. The first terminal of the current source circuitry 342 is coupled to the supply terminal, which supplies the supply voltage. The second terminal of the current source circuitry 342 is coupled to the current source circuitry 314, the transistors 334, 338, 346, and the capacitor 344. The capacitor 344 has a first terminal and a second terminal. The first terminal of the capacitor 344 is coupled to the supply terminal, which supplies the supply voltage. The second terminal of the capacitor 344 is coupled to current source circuitry 314, 342 and the transistors 334, 338, 346. In some examples, the current source circuitry 342 and the capacitor 344 are structured as pull-up circuitry, which pulls up a voltage to control the current source circuitry 314 and the transistor 346. In such examples, adjusting the current from the current source circuitry 342 or the capacitance of the capacitor 344 adjusts the duration that the current source circuitry 314 supplies the increased slew assist current.
The transistor 346 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 346 is coupled to the resistor 348. The second terminal of the transistor 346 is coupled to the resistors 350, 356. The control terminal of the transistor 346 is coupled to the current source circuitry 314, 342, the transistors 334, 338, and the capacitor 344. The resistor 348 has a first terminal and a second terminal. The first terminal of the resistor 348 is coupled to the supply terminal, which supplies the supply voltage. The second terminal of the resistor 348 is coupled to the transistor 346. In some examples, the transistor 346 and the resistor 348 are structured as current source circuitry, which supplies a current to the resistors 350, 356 responsive to a voltage at the control terminal of the transistor 346. In such examples, the resistor 348 is structured as current limiting circuitry, which controls the current through the transistor 346.
The resistor 350 has a first terminal and a second terminal. The first terminal of the resistor 350 is coupled to the transistor 346 and the resistor 356. The second terminal of the resistor 350 is coupled to the transistor 352. The transistor 352 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the transistor 352 is coupled to the resistor 350. The second terminal of the transistor 352 is coupled to the transistor 354. The third terminal of the transistor 352 (also referred to as a bulk terminal) is coupled to the transistors 302, 304, 358 and the slew assist circuitry 316. The control terminal of the transistor 352 is coupled to the transistors 302, 354, the input transistor circuitry 308, and the slew assist circuitry 316. The transistor 354 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 354 is coupled to the transistor 352. The second terminal of the transistor 354 is coupled to the transistor 338 and the resistor 340. The control terminal of the transistor 354 is coupled to the transistors 302, 352, the input transistor circuitry 308, and the slew assist circuitry 316. In the example of
The resistor 356 has a first terminal and a second terminal. The first terminal of the resistor 356 is coupled to the transistor 346 and the resistor 350. The second terminal of the resistor 356 is coupled to the transistor 358. The transistor 358 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the transistor 358 is coupled to the resistor 356. The second terminal of the transistor 358 is coupled to the transistor 360. The third terminal of the transistor 358 (also referred to as a bulk terminal) is coupled to the transistors 302, 304 and the slew assist circuitry 316. The control terminal of the transistor 358 is coupled to the transistors 304, 360, the input transistor circuitry 308, and the slew assist circuitry 316. The transistor 360 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 360 is coupled to the transistor 358. The second terminal of the transistor 360 is coupled to the transistor 334 and the resistor 336. The control terminal of the transistor 360 is coupled to the transistors 304, 358, the input transistor circuitry 308, and the slew assist circuitry 316. In the example of
The resistor 362 has a first terminal and a second terminal. The first terminal of the resistor 362 is coupled to the supply terminal, which supplies the supply voltage. The second terminal of the resistor 362 is coupled to the transistor 364. The transistor 364 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 364 is coupled to the resistor 362. The second terminal of the transistor 364 is coupled to the slew assist circuitry 316. The control terminal of the transistor 364 is coupled to the feedback circuitry 312.
The transistor 366 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the transistor 366 is coupled to the current source circuitry 314 and the transistor 370. The second terminal of the transistor 366 is coupled to the transistors 368, 376. The third terminal of the transistor 366 (also referred to as a bulk terminal) is coupled to the transistors 302, 304, 370 and the feedback circuitry 312. The control terminal of the transistor 366 is coupled to the transistors 302, 368, 374, the input transistor circuitry 308, and the feedback circuitry 312. The transistor 368 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 368 is coupled to the transistors 366, 376. The second terminal of the transistor 368 is coupled to the current mirror circuitry 318. The control terminal of the transistor 368 is coupled to the transistors 302, 366, 374, the input transistor circuitry 308, and the feedback circuitry 312. In the example of
The transistor 370 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the transistor 370 is coupled to the current source circuitry 314 and the transistor 366. The second terminal of the transistor 370 is coupled to the transistors 372, 374. The third terminal of the transistor 370 (also referred to as a bulk terminal) is coupled to the transistors 302, 366, the input transistor circuitry 308, and the feedback circuitry 312. The control terminal of the transistor 370 is coupled to the transistors 304, 372, 376, the input transistor circuitry 308, and the feedback circuitry 312. The transistor 372 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 372 is coupled to the transistors 370, 374. The second terminal of the transistor 372 is coupled to the current mirror circuitry 318. The control terminal of the transistor 372 is coupled to the transistors 304, 370, 376, the input transistor circuitry 308, and the feedback circuitry 312. In the example of
The transistor 374 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 374 is coupled to the transistors 370, 372. The second terminal of the transistor 374 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 374 is coupled to the transistors 302, 366, 368, the input transistor circuitry 308, and the feedback circuitry 312. In the example of
The transistor 376 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 376 is coupled to the transistors 366, 368. The second terminal of the transistor 376 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 376 is coupled to the transistors 304, 370, 372, the input transistor circuitry 308, and the feedback circuitry 312. In the example of
The transistor 378 has a first terminal, a second terminal, and a control terminal. The first and control terminals of the transistor 378 are coupled to the slew assist circuitry 316 and the third output terminal of the input stage circuitry 300, which supplies the first bias voltage (VBIAS1) to the power stage circuitry 120 of
The transistor 380 has a first terminal, a second terminal, and a control terminal. The first and control terminals of the transistor 380 are coupled to the slew assist circuitry 316 and the fourth output terminal of the input stage circuitry 300, which supplies the second bias voltage (VBIAS2) to the power stage circuitry 120, or even more generally the output stage circuitry 110. The second terminal of the transistor 378 is coupled to the common terminal, which supplies the common potential. In the example of
In the example of
In example operations, the transistors 302, 304 receive one of the first input or the second input. The transistors 320, 322 generate the first intermediate signal path output responsive to the first input at the transistor 302 and the transistor 324, 326 generate the second intermediate signal path output responsive to the second input at the transistor 304. During steady state operations (e.g., no transient at the transistors 302, 304), the current source circuitry 342 and the capacitor 344 pull-up the control terminals of the transistors 346, 364, which reduces the feedback current and slew assist currents. In such example operations, the transistors 368, 370, 374, 376 implement minimum selector control, which uses the transistors 374, 376 to sink the slew assist current and reduce any current to the transistors 378, 380. Advantageously, during steady state operations, the feedback circuitry 312 structures the current source circuitry 314 to supply a reduced slew assist current. Also, the slew assist circuitry 316 further reduces the supply of a slew assist current to the current mirror circuitry 318 by implementing a minimum selector bias of the transistors 374, 376. In such examples, the transistors 374, 376 have a cascode bias resulting from sizing the transistors 374, 376 in relation to the transistors 368, 372. Advantageously, the cascode bias of the transistors 368, 372, 374, 376 reduces currents through the transistors 368, 372 when the transistors 374, 376 are conducting current. Such a cascode bias is further described in connection with
In other example operations, during slew event operations (e.g., transient at the transistors 302, 304), the transient inputs structure one of the first or second feedback current paths through the transistors 352, 354, 358, 360. The one of the first or second feedback currents turn off one of the transistors 334, 338 and strongly turns on the other one of the transistors 334, 338. The other one of the transistors 334, 338 pulls down the control terminals of the transistors 346, 364 to increase the feedback current and slew assist current. Also, the transient inputs structure one of the first or second slew assist current paths through the transistors 366, 368, 370, 372. The one of the first or second slew assist current paths that supply the increased slew assist current to one of the transistors 378, 380 is referred to as the preferred path. The one of the transistors 378, 380 coupled to the preferred path generate a bias voltage which increases the slew rate of the amplifier circuitry 100. Advantageously, the slew assist circuitry 316 dynamically supplies the increased slew assist current to the current mirror circuitry 318 during slew event operations. Example operations of the input stage circuitry 300 are described further below in connection with
The input stage circuitry 400 has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal of the input stage circuitry 400 is structured to be coupled to external circuitry, which supplies a first input (IN1). The second input terminal of the input stage circuitry 400 is structured to be coupled to external circuitry which supplies a second input (IN2). The first and second output terminals of the input stage circuitry 400 are structured to be coupled to the driver circuitry 115 of
In the example of
In the example of
In the example of
The clamp circuitry 410 has a first terminal, a second terminal, and may have a third terminal and a fourth terminal. The first and second terminals of the clamp circuitry 410 are coupled to the slew assist circuitry 240. The third and fourth terminals of the clamp circuitry 410 are coupled to the slew assist circuitry 240 and the current mirror circuitry 245. Examples of the clamp circuitry 410 are illustrated and described in connection with
In the example of
In example operations, the clamp circuitry 410 generates first and second clamp voltages responsive to currents from the slew assist circuitry 240. The first and second clamp voltages are structured to reduce a supply of the slew assist currents from the slew assist circuitry 240 to the current mirror circuitry 245. Advantageously, the clamp circuitry 410 reduces a supply of slew assist current to the current mirror circuitry 245 using the first and second clamp voltages. Advantageously, the clamp circuitry 410 is configured to clamp the slew assist circuitry 240 using the first and second clamp voltages. Example operations of the input stage circuitry 400 are described further below in connection with
The input stage circuitry 500 has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal of the input stage circuitry 500 is structured to be coupled to external circuitry, which supplies a first input (IN1). The second input terminal of the input stage circuitry 500 is structured to be coupled to external circuitry which supplies a second input (IN2). The first and second output terminals of the input stage circuitry 500 are structured to be coupled to the driver circuitry 115 of
In the example of
The resistor 520 has a first terminal and a second terminal. The first terminal of the resistor 520 is coupled to the transistor 374, or more generally the slew assist circuitry 316. The second terminal of the resistor 520 is coupled to the common terminal, which supplies the common potential. The resistor 530 has a first terminal and a second terminal. The first terminal of the resistor 530 is coupled to the transistor 376, or more generally the slew assist circuitry 316. The second terminal of the resistor 530 is coupled to the common terminal, which supplies the common potential.
In example operation, the resistor 520 generates a first clamp voltage responsive to current from the transistor 374 and the resistor 530 generates a second clamp voltage responsive to current from the transistor 376. In such example operations, the first clamp voltage biases the transistor 374 to turn off the transistor 368 and the second clamp voltage biases the transistor 376 to turn off the transistor 372. Advantageously, the first and second clamp voltages further reduce slew assist current being supplied to the current mirror circuitry 318 by fully disabling the transistors 368, 372. Example operations of the input stage circuitry 500 are described further below in connection with
The input stage circuitry 600 has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal of the input stage circuitry 600 is structured to be coupled to external circuitry, which supplies a first input (IN1). The second input terminal of the input stage circuitry 600 is structured to be coupled to external circuitry which supplies a second input (IN2). The first and second output terminals of the input stage circuitry 600 are structured to be coupled to the driver circuitry 115 of
The current mirror circuitry 605 is coupled to the feedback circuitry 312, the slew assist circuitry 316, the clamp circuitry 610, and the third and fourth output terminals of the input stage circuitry 600, which supply the first and second bias voltages (VBIAS1, VBIAS2) to the power stage circuitry 120 of
The transistor 615 has a first terminal, a second terminal, and a control terminal. The first and control terminals of the transistor 615 are coupled to the transistor 368, or more generally the slew assist circuitry 316, the clamp circuitry 610, the transistor 620, and the third output terminal of the input stage circuitry 600, which supplies the first bias voltage (VBIAS1) to the output stage circuitry 110. The second terminal of the transistor 615 is coupled to the common terminal, which supplies the common potential. The transistor 620 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 620 is coupled to the transistors 334, 338, 346, or more generally the feedback circuitry 312, and the transistor 630. The second terminal of the transistor 620 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 620 is coupled to the slew assist circuitry 316, the clamp circuitry 610, the transistor 615, and the third output terminal of the input stage circuitry 600, which supplies the first bias voltage (VBIAS1) to the output stage circuitry 110.
The transistor 625 has a first terminal, a second terminal, and a control terminal. The first and control terminals of the transistor 625 are coupled to the transistor 372, or more generally the slew assist circuitry 316, the clamp circuitry 610, the transistor 630, and the fourth output terminal of the input stage circuitry 600, which supplies the second bias voltage (VBIAS2) to the output stage circuitry 110. The second terminal of the transistor 625 is coupled to the common terminal, which supplies the common potential. The transistor 630 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 630 is coupled to the feedback circuitry 312 and the transistor 620. The second terminal of the transistor 630 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 630 is coupled to the slew assist circuitry 316, the clamp circuitry 610, the transistor 625, and the fourth output terminal of the input stage circuitry 600, which supplies the second bias voltage (VBIAS2) to the output stage circuitry 110.
The resistor 635 has a first terminal and a second terminal. The first terminal of the resistor 635 is coupled to the slew assist circuitry 316 and the transistors 645, 650. The second terminal of the resistor 635 is coupled to the common terminal, which supplies the common potential. The resistor 635 is another example of the resistor 520 of
The transistor 645 has a first terminal, a second terminal, and a control terminal. The first and control terminals of the transistor 645 are coupled to the slew assist circuitry 316, the resistor 635, and the transistor 650. The second terminal of the transistor 645 is coupled to the common terminal, which supplies the common potential. The transistor 650 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 650 is coupled to the slew assist circuitry 316 and the current mirror circuitry 605. The second terminal of the transistor 650 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 650 is coupled to the slew assist circuitry 316, the resistor 635, and the transistor 645.
The transistor 655 has a first terminal, a second terminal, and a control terminal. The first and control terminals of the transistor 655 are coupled to the slew assist circuitry 316, the resistor 640, and the transistor 660. The second terminal of the transistor 655 is coupled to the common terminal, which supplies the common potential. The transistor 660 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 660 is coupled to the slew assist circuitry 316 and the current mirror circuitry 605. The second terminal of the transistor 660 is coupled to the common terminal, which supplies the common potential. The control terminal of the transistor 660 is coupled to the slew assist circuitry 316, the resistor 640, and the transistor 655.
In the example of
In example operation, the transistors 620, 630 mirror currents through the transistors 615, 625, which represent the slew assist current. The transistors 620, 630 increase the speed at which the feedback circuitry 312 pulls down the control terminals of the transistors 346, 364. The transistors 645, 655 mirror current through the resistors 635, 640. The transistors 650, 660 sink the current through the resistors 635, 640 from the slew assist circuitry 316. Advantageously, the transistors 650, 660 reduce the slew assist currents supplied to the current mirror circuitry 605 when current is flowing through the resistors 635, 640. Advantageously, the transistors 650, 660 reduce a likelihood of the transistors 620, 630 pulling down the control terminal of the transistors 346, 364 using non-ideal slew assist currents from the slew assist circuitry 316. Example operations of the input stage circuitry 600 are described further below in connection with
The input transistor circuitry 220, 308 of
The output stage circuitry 110 of
The feedback circuitry 230, 312 of
If the feedback circuitry 230, 312 and the slew assist circuitry 240, 316 determine there is no slew event (e.g., Block 720 returns a result of NO), control proceeds to return to block 705. For example, the feedback circuitry 230, 312 and the slew assist circuitry 240, 316 remain in the steady state operation.
If the feedback circuitry 230, 312 and the slew assist circuitry 240, 316 determine there is a slew event (e.g., Block 720 returns a result of YES), the feedback circuitry 230, 312 generates a feedback current using the differential inputs. (Block 725). In some examples, the feedback circuitry 230, 312 generates a feedback current through a first current path or a second current path. The first current path of the feedback circuitry 230, 312 is controlled by the transistors 205, 302 and flows through the resistors 340, 350 and the transistors 346, 352, 354. The second current path of the feedback circuitry 230, 312 is controlled by the transistors 210, 304 and flows through the resistors 336, 356 and the transistors 346, 358, 360. When a slew event occurs (e.g., a rising edge at one input and a falling edge at another input), the feedback circuitry 230, 312 generates a feedback current by turning on transistors of one of the first or second current paths and turning off transistors of the other one of the first or second current paths. For example, when the first input signal turns off the transistors 205, 302 and the second input signal turns on the transistors 210, 304, the transistors 352, 354 turn on and the transistors 358, 360 turn off. In such an example, the transistors 352, 354 supply a feedback current to the resistor 340.
The bias circuitry 225, 310 of
The slew assist circuitry 240, 316 generates a slew assist current based on the differential inputs. (Block 735). In some examples, the slew assist circuitry 240, 316 generates a slew assist current through a first current path or a second current path. The first current path of the slew assist circuitry 240, 316 is controlled by the transistors 205, 302 and flows from the current source circuitry 235, 314 and through the transistors 366, 368. The second current path of the slew assist circuitry 240, 316 is controlled by the transistors 210, 304 and flows from the current source circuitry 235, 314 and through the transistors 370, 372. When a slew event occurs (e.g., a rising edge at one input and a falling edge at another input), the slew assist circuitry 240, 316 generates a slew assist current by turning on transistors of one of the first or second current paths and turning off transistors of the other one of the first or second current paths.
Also, when the first current path is active, the transistors 205, 302 also turn on the transistor 374 of
The feedback circuitry 230, 312 pulls down a control voltage. (Block 740). In some examples, the feedback circuitry 230, 312 uses the feedback current from the transistors 354, 360 to turn off one of the transistors 334, 338 and strongly turn on the other one of the transistors 334, 338. For example, when the transistors 205, 302 turn on the transistors 352, 354, the transistors 352, 354 supply the feedback current to the resistor 340, which generates a voltage that reverse biases and turns off the transistor 338. In such examples, when the transistors 210, 304 turn off the transistors 358, 360, the bias circuitry 225, 310 causes the transistor 334 to strongly conduct a current, which pulls down a control voltage at the control terminals of the transistors 346, 364.
The feedback circuitry 230, 312 and the current source circuitry 235, 314 determine if the control voltage is less than a threshold voltage. (Block 745). In some examples, one of the transistors 334, 338 pulls down the control voltage at the control terminals of the transistors 346, 364 responsive to slew operations of the feedback circuitry 230, 312. In such examples, the transistors 334, 338 increase currents being supplied to the feedback circuitry 230, 312 and the slew assist circuitry 240, 316. When feedback circuitry 230, 312 and the current source circuitry 235, 314 determine the control voltage is not less than the threshold voltage (e.g., Block 745 returns a result of NO), control proceeds to return to Block 745.
When feedback circuitry 230, 312 and the current source circuitry 235, 314 determine the control voltage is less than the threshold voltage (e.g., Block 745 returns a result of YES), the current source circuitry 235, 314 changes the slew assist current. (Block 750). In some examples, the transistor 364 is a p-channel field effect transistor structured to increase a supply of current to the slew assist circuitry 240, 316 as the gate-to-source voltage decreases. In such examples, the transistor 364 increases a supply of current to the slew assist circuitry 240, 316 responsive to the feedback circuitry 312 pulling down the control voltage at the control terminal of the transistor 364.
The current mirror circuitry 245, 318, 605 of
The output stage circuitry 110 changes a slew rate of an edge of the output signal using the bias voltages. (Block 760). In some examples, the power stage circuitry 120 mirrors the slew assist current responsive to receiving the bias voltages from the current mirror circuitry 245, 318, 605. In such examples, the transistor 135 changes a slew rate of rising edges of the output signal by sinking a replica of the current through the transistor 372 from the control terminal of the transistor 125 and the capacitor 130. Similarly, the transistors 160, 165, 170 change the slew rate of falling edges of the output signal by supplying a replica of the current through the transistor 368 to the control terminal of the transistor 150 and the capacitor 155.
The feedback circuitry 230, 312 and the slew assist circuitry 240, 316 determine if input currents of the differential inputs are approximately equal. (Block 765). In some examples, the feedback circuitry 230, 312 and the slew assist circuitry 240, 316 begin to approach steady state operations as currents from the transistors 205, 210, 302, 304 begin to settle after a slew event. If the feedback circuitry 230, 312 and the slew assist circuitry 240, 316 determine the input currents of the differential inputs are not approximately equal (e.g., Block 765 returns a result of NO), control proceeds to return to Block 765.
If the feedback circuitry 230, 312 and the slew assist circuitry 240, 316 determine the input currents of the differential inputs are approximately equal (e.g., Block 765 returns a result of YES), the feedback circuitry 230, 312 reduces the slew assist current. (Block 770). In some examples, when the feedback circuitry 230, 312 is in the steady state of operation, the current source circuitry 342 and the capacitor 344 pull up the control voltage at the control terminal of the transistor 364. In such examples, the feedback circuitry 230, 312 decreases the current supplied to the slew assist circuitry 240, 316.
The slew assist circuitry 240, 316 steers away excess slew assist current. (Block 775). In some examples, as further described above, the transistors 374, 376 are sized to be substantially larger than the transistors 368, 372 to reduce the excess non-ideal slew assist current from the transistors 366, 370 from being supplied to the current mirror circuitry 245, 318, 605. In some such examples, the clamp circuitry 410, 510, 610 further prevents the excess non-ideal slew assist current by clamping the slew assist circuitry 240, 316 to a voltage that fully disables the transistors 366, 370. Also, the clamp circuitry 410, 610 includes circuitry to directly sink the excess non-ideal slew assist current. For example, the transistors 645, 655 of
Although example methods are described with reference to the flowchart illustrated in
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and things, the phrase “at least one of A and B” refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and things, the phrase “at least one of A or B” refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more,” and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Also, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is at least one of not feasible or advantageous.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by at least one of the connection reference or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, or ordering in any way, but are merely used as at least one of labels or arbitrary names to distinguish elements for ease of understanding the described examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to at least one of manufacturing tolerances or other real-world imperfections. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified herein.
As used herein, the phrase “in communication,” including variations thereof, encompasses one of or a combination of direct communication or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication or constant communication, but rather also includes selective communication at least one of periodic intervals, scheduled intervals, aperiodic intervals, or one-time events.
As used herein, “programmable circuitry” is defined to include at least one of (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions(s) or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to at least one of configure or structure the FPGAs to instantiate one or more operations or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations or functions or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
A device that is “configured to” perform a task or function may be configured (e.g., at least one of programmed or hardwired) at a time of manufacturing by a manufacturer to at least one of perform the function or be configurable (or re-configurable) by a user after manufacturing to perform the function/or other additional or alternative functions. The configuring may be through at least one of firmware or software programming of the device, through at least one of a construction or layout of hardware components and interconnections of the device, or a combination thereof.
As used herein, the terms “terminal,” “node,” “interconnection,” “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
In the description and claims, described “circuitry” may include one or more circuits. A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as one of or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by at least one of an end-user or a third-party.
Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in at least one of series or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are at least one of: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include at least one of a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/-10 percent of the stated value, or, if the value is zero, a reasonable range of values around zero.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
This patent application claims the benefit of and priority to U.S. Provisional Patent Application No. 63/546,622 filed Oct. 31, 2023, which is hereby incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63546622 | Oct 2023 | US |
