This disclosure relates generally to optical connectors and, more particularly, to methods and apparatus to enable customization of pigtail lengths of optical connectors.
Optical connectors, such as fiber array units (FAUs), are used to optically connect an optical component to an external component/device through a series of wires or fibers. More particularly, optical FAUs can be used to connect a photonic integrated circuit (PIC) to a mechanical transfer (MT) ferrule through a series of optical fibers for externally connecting the PIC to an external component/device.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified in the below description.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
FAUs commonly have fixed length dongles and are permanently attached to a PIC. These fixed length dongles provide a serious limitation where end use platforms (e.g., a computer, server systems, etc.) may ultimately need to accommodate these fixed length dongles. A simple solution is to add connections to extend the lengths to satisfy system routing requirements, but this will be costly not only in the added hardware cost but also with the additional link loss that will add cost in terms of pJ/bit of data transferred, and this additional loss may lead to other architectural limitations where link budgets are exceeded. Alternatively, since FAUs are permanently attached to the PIC, a family of various lengths and configurations needs to be produced to accommodate the variety of possible end use platforms, which would be expensive and time consuming to maintain by the electronics packaging manufacturer.
FAU dongles, also known as pigtails, take up a considerable amount of space and special accommodations are needed in handling test systems and attach equipment. These accommodations put constraints on pigtail length options for end use platforms and may limit package side egress to one or two sides. Additionally, FAU dongles that are pre-assembled to PICs are incompatible with the thermal compression bond (TCB) assembly process used to bond chips (e.g., PICs) to package substrates. Further, FAU dongles that are pre-assembled to PICs present difficulties for package ball grid array (BGA) reflow to board processes because the reflow process can deleteriously affect the connections between the FAU and the PIC. As such, attaching FAUs to high value packages has significant yield/cost risks. Therefore, there exists a need for an FAU to enable customization of pigtail lengths with increased modularity.
The affixed FAU 120 and the detachable FAU 130, as their names imply, differ based on how they are attached or attachable to the optical component 110. More particularly, in some examples, the affixed FAU plug 120 permanently connects to the optical component 110 through at least the first array of optical fibers 125, with the first array of optical fibers 125 bonded to both the optical component 110 and the affixed FAU plug 120. As used herein, “permanently” and all variations thereof in the context of a connection refers to a connection that cannot be undone without damage or risk of damage to the component and/or the connected components. By contrast to the affixed FAU 120, the detachable FAU 130 can be selectively connected or removed from the optical component 110 without damage to the components involved.
The first array of optical fibers 125 includes any number of optical fibers that may be appropriate for the application, which may also include only one fiber. In some examples, the detachable FAU plug 130 connects to a user-end ferrule (such as the user-end ferrule 430 shown in
The bonding of the first array of optical fibers 125 to the affixed FAU plug 120 and the bonding of the second array of optical fibers 135 to the detachable FAU plug 130 may be accomplished using any method of fiber bonding. Such methods may include dispensing epoxy on the fibers that have been previously placed inside a ferrule. However, in other examples, the fibers 125, 135 may be bonded to the FAU plugs 120, 130 before the distal end of the second array of optical fibers 135 are placed inside the user-end ferrule 430.
In some examples, the affixed FAU plug 120 and the detachable FAU plug 130 include corresponding portions of the v-groove alignment slots 140 to facilitate the positioning of the fibers 125, 135 relative to the FAU plugs 120, 130. In this manner, the v-groove alignment slots 140 facilitate the aligning of the first array of optical fibers 125 with the second array of optical fibers 135 when the affixed and detachable FAU plugs 120, 130 are positioned adjacent one another as shown in
In some examples, the alignment casing 150 is used to align the first array of optical fibers 125 on the affixed FAU plug 120 with the second array of optical fibers 135 on the detachable FAU plug 130. In some examples, the alignment casing 150 includes guide pins 160 for aligning with slots in the affixed FAU plug 120 and the detachable FAU plug 130 for greater alignment control over the optical fibers. That is, in some examples, the guide pins 160 are bonded to the alignment casing (e.g., within corresponding grooves) and positioned to be received within ones of the v-grooves 140 in the FAU plugs 120, 130, thereby orienting both FAU plugs 120, 130 relative to the alignment casing 150 and relative to each other. In some examples, the affixed FAU plug 120 and the detachable FAU plug 130 engage (e.g., connect, abut, adjoin, etc.) with one another such that the alignment of the optical fibers 125, 135 is maintained through the use of a retention mechanism (such as those illustrated in
In some examples, the affixed FAU plug 120 is removably coupled to the detachable FAU plug 130 via the alignment casing 150. The alignment casing 150 may be removed from the configuration to allow removal of the detachable FAU plug 130 and to allow replacement with a different (e.g., new) detachable FAU plug (not shown). This allows for different FAU pigtail lengths/combinations to be interchanged without the need to remove the entire FAU or obtain a new optical component 110.
Further, in some examples, the affixed FAU plug 120 is compatible with the package BGA reflow to board process. In such an example, the affixed FAU plug 120 can be bonded to the optical component 110 and then subjected to the BGA reflow process without destroying the FAU. In such an example, the affixed FAU plug 120 is less likely to be damaged during the BGA process since the entire FAU is not present on the optical component 110 itself.
In the illustrated example of
The example optical fiber alignment and ferrule plug creation process 400 then moves to
In some examples, the alignment casing 150 may be attached to the affixed FAU plug 120 and/or the detachable FAU plug 130 and maintain a permanent alignment through a permanent bond, such as adhesive. In such examples, the other one of the affixed FAU plug 120 and/or the detachable FAU plug 130 is not permanently affixed to the alignment casing 150 to enable the FAU plugs 120, 130 to be selectively connected or separated. In some examples, the alignment casing 150 maintains the alignment of the optical fibers 125, 135 through a temporary or selectively couple with the FAU plugs 120, 130 using a retention/force mechanism. Example retention/force mechanisms are further explained in reference to
The example optical fiber alignment and ferrule plug creation process 400 creates a connection between the affixed FAU plug 120 and the detachable FAU plug 130, reducing link losses while still maintaining the ability to replace the detachable FAU plug 130 as described herein. Bonding the uncut optical fibers 410 to the first ferrule 420 and then cutting the first ferrule 410 to obtain the affixed FAU plug 120 and the detachable FAU plug 130 creates the relatively high precision of less than 1 micron of lateral offset and less than 1 degree of angular offset described above. In some examples, the lateral offset can be significantly less than 1 micron (e.g., +/−0.75 microns, +/−0.5 microns, +/−0.25 microns, etc.). In an example where the affixed FAU plug 120 and the detachable FAU plug 130 are created separately, the link losses across the optical fibers are greater due to possible inaccuracies in fiber bonding to the respective FAU plug. However, the replacement FAU plug still provides a reduction in link losses where the replacement FAU plug is created using the example optical fiber alignment and ferrule plug creation process 400. In some examples, after the first ferrule 420 is cut as described in reference to
In some examples, an example testing environment may need to rearrange the shuffled optical fibers 610 to meet the needs of the example testing environment. For example, optical signals transmitted on the optical fibers exiting the detachable FAU plug 130 (e.g., the second array of optical fibers 135) may need to terminate in a non-linear position with respect to the detachable FAU plug 130 (e.g., the optical fibers are shuffled in the arrangement shown in
As illustrated in
As shown in
In some examples, the second retention mechanism 810 may be deformed by squeezing the release mechanism 812, which opens the compression mechanism 814 by moving about the hinge point 816. As the compression mechanism 814 is opened, the example FAU plug assembly 115 may be inserted into the opening. Releasing the release mechanism 812 will allow the compression mechanism 814 to provide a compressive force to retain the alignment of the first array of optical fibers 125 on the affixed FAU plug 120 to the second array of optical fibers 135 on the detachable FAU plug 130.
In some examples, a spring 820 may be included to the outward end of the detachable FAU plug 130 (e.g., the end facing away from the affixed FAU plug 120), as illustrated in
The illustrated example of
In the illustrated example of
The example alignment and ferrule manufacturing process 1100 then continues at block 1110 where the optical fibers 410 are attached to the first ferrule 420. In some examples, the optical fibers 410 are attached to the first ferrule 420 through a bonding process, such as using epoxy.
The example alignment and ferrule manufacturing process 1100 then continues, at block 1120, by attaching the optical fibers 410 to a second ferrule (e.g., the user-end ferrule 430). As stated above in reference to
After the optical fibers 410 have been bonded to both the first ferrule 420 and the user-end ferrule 430, the example process advances to block 1130 where the first ferrule 420 is cut to obtain the affixed FAU plug 120 and the detachable FAU plug 130. As mentioned above in reference to
In some examples, at block 1140, the example alignment and ferrule manufacturing process 1100 involves adding an identifier to each of the affixed FAU plug 120 and the detachable FAU plug 130. Such an identifier may include, for example, a serial number to indicate the compatibility of the respective plugs (either as a matching pair cut from the same first ferrule 420 or as plugs cut from different instances of the first ferrule). Matching two identical serial numbers may, for example, indicates a higher precision pair if minimal link losses are desired for a use platform. In some examples, the identifiers are added to the affixed FAU plug 120 and the detachable FAU plug 130 prior to cutting the first ferrule (at block 1130) and may even be added before attachment of the optical fibers to the first ferrule (at block 1110).
Next, at block 1150, the affixed FAU plug 120 is bonded to the optical component 110. In some examples, the bonding of the affixed FAU plug 120 to the optical component 110 utilizes any known method of bonding and/or aligning optical fibers to a component, such as active alignment.
At block 1160, the detachable FAU plug 130 is aligned with the affixed FAU plug 120 using the alignment casing 150. In some examples described herein, the alignment casing 150 may include guide pins 160 for aligning with the v-groove alignment slots 140 to facilitate alignment of the optical fibers in the separate FAU plugs 120, 130.
At block 1170, the alignment is retained using a retention mechanism. As described herein, in some examples, the retention mechanism may include the first retention mechanism 710, the second retention mechanism 810, the third retention mechanism 1010, and/or any other mechanism for retaining the alignment of the first array of optical fibers 125 on the affixed FAU plug 120 to the second array of optical fibers 135 on the detachable FAU plug 130. In some examples, blocks 1160 and 1170 are accomplished simultaneously such as when the retention mechanism includes guide pins 160 to facilitate the alignment without the use of an alignment casing 150.
While an example manner of implementing the example optical fiber alignment and ferrule plug creation process 400 of
If the detachable FAU plug 130 is to be replaced (e.g., block 1210 returns a result of YES), the process advances to block 1220 where retention mechanism is removed. In some examples, the retention mechanism includes the first retention mechanism 710, the second retention mechanism 810, the third retention mechanism 1010, and/or any other mechanism for retaining an alignment of the first array of optical fibers 125 on the affixed FAU plug 120 to the second array of optical fibers 135 on the detachable FAU plug 130.
At block 1230, the detachable FAU plug 130 is removed. In some examples, block 1230 may also include removing the alignment casing 150 if it is present in the configuration.
In some examples, once the detachable FAU plug 130 is removed, the example detachable FAU plug replacement process 1200 advances to block 1240 to identify a new detachable FAU plug based on an identifier on the new detachable FAU plug. In some examples, the identifier may include a serial number. The serial number may be used to organize the detachable FAU plug 130 into a group based on operational or organizational characteristics, which may include number of optical fibers, optical fiber orientation, PIC compatibility, etc.
At block 1250, the new detachable FAU plug is aligned with the affixed FAU plug 120 using the alignment casing 150. In some examples described herein, the alignment casing 150 may include guide pins 160 for aligning with the v-groove alignment slots 140 to align the optical fibers therein.
At block 1260, the alignment is retained using the retention mechanism. In some examples, the retention mechanism may be removably coupled to the affixed FAU plug 120 and/or the detachable FAU plug 130. In some examples, the retention mechanism may also include the alignment casing, such as including guide pins 160.
When the retention mechanism is placed to retain the alignment or when the example detachable FAU plug replacement process 1200 determines that the detachable FAU plug 130 does not need to be replaced (e.g., block 1210 returns a result of NO), then the example detachable FAU plug replacement process 1200 ends. The example detachable FAU plug replacement process 1200 may be repeated as many times as necessary until no additional detachable FAU plug 130 are to be used.
While an example manner of implementing the example detachable FAU plug replacement process 1200 is illustrated in
The example optical assembly 100 and the associated example retention mechanisms 710, 810, 1010 disclosed herein may be included in any suitable electronic component.
The IC device 1400 may include one or more device layers 1404 disposed on the die substrate 1402. The device layer 1404 may include features of one or more transistors 1440 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1402. The device layer 1404 may include, for example, one or more source and/or drain (S/D) regions 1420, a gate 1422 to control current flow in the transistors 1440 between the S/D regions 1420, and one or more S/D contacts 1424 to route electrical signals to/from the S/D regions 1420. The transistors 1440 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1440 are not limited to the type and configuration depicted in
Each transistor 1440 may include a gate 1422 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1440 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 1440 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1402 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1402. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1402 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1402. In other examples, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1420 may be formed within the die substrate 1402 adjacent to the gate 1422 of each transistor 1440. The S/D regions 1420 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1402 to form the S/D regions 1420. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1402 may follow the ion-implantation process. In the latter process, the die substrate 1402 may first be etched to form recesses at the locations of the S/D regions 1420. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1420. In some implementations, the S/D regions 1420 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 1420 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1420.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1440) of the device layer 1404 through one or more interconnect layers disposed on the device layer 1404 (illustrated in
The interconnect structures 1428 may be arranged within the interconnect layers 1406-1410 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1428 depicted in
In some examples, the interconnect structures 1428 may include lines 1428a and/or vias 1428b filled with an electrically conductive material such as a metal. The lines 1428a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1402 upon which the device layer 1404 is formed. For example, the lines 1428a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1406-1410 may include a dielectric material 1426 disposed between the interconnect structures 1428, as shown in
A first interconnect layer 1406 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1404. In some examples, the first interconnect layer 1406 may include lines 1428a and/or vias 1428b, as shown. The lines 1428a of the first interconnect layer 1406 may be coupled with contacts (e.g., the S/D contacts 1424) of the device layer 1404.
A second interconnect layer 1408 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1406. In some examples, the second interconnect layer 1408 may include vias 1428b to couple the lines 1428a of the second interconnect layer 1408 with the lines 1428a of the first interconnect layer 1406. Although the lines 1428a and the vias 1428b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1408) for the sake of clarity, the lines 1428a and the vias 1428b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 1410 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1408 according to similar techniques and configurations described in connection with the second interconnect layer 1408 or the first interconnect layer 1406. In some examples, the interconnect layers that are “higher up” in the metallization stack 1419 in the IC device 1400 (i.e., further away from the device layer 1404) may be thicker.
The IC device 1400 may include a solder resist material 1434 (e.g., polyimide or similar material) and one or more conductive contacts 1436 formed on the interconnect layers 1406-1410. In
The IC package 1500 may include a die 1506 coupled to the package substrate 1502 via conductive contacts 1504 of the die 1506, first-level interconnects 1508, and conductive contacts 1510 of the package substrate 1502. The conductive contacts 1510 may be coupled to conductive pathways 1512 through the package substrate 1502, allowing circuitry within the die 1506 to electrically couple to various ones of the conductive contacts 1514 (or to other devices included in the package substrate 1502, not shown). The first-level interconnects 1508 illustrated in
In some examples, an underfill material 1516 may be disposed between the die 1506 and the package substrate 1502 around the first-level interconnects 1508, and a mold compound 1518 may be disposed around the die 1506 and in contact with the package substrate 1502. In some examples, the underfill material 1516 may be the same as the mold compound 1518. Example materials that may be used for the underfill material 1516 and the mold compound 1518 are epoxy mold materials, as suitable. Second-level interconnects 1520 may be coupled to the conductive contacts 1514. The second-level interconnects 1520 illustrated in
In
Although the IC package 1500 illustrated in
In some examples, the circuit board 1602 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1602. In other examples, the circuit board 1602 may be a non-PCB substrate.
The IC device assembly 1600 illustrated in
The package-on-interposer structure 1636 may include an IC package 1620 coupled to an interposer 1604 by coupling components 1618. The coupling components 1618 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1616. Although a single IC package 1620 is shown in
In some examples, the interposer 1604 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1604 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1604 may include metal interconnects 1608 and vias 1610, including but not limited to through-silicon vias (TSVs) 1606. The interposer 1604 may further include embedded devices 1614, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1604. The package-on-interposer structure 1636 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1600 may include an IC package 1624 coupled to the first face 1640 of the circuit board 1602 by coupling components 1622. The coupling components 1622 may take the form of any of the examples discussed above with reference to the coupling components 1616, and the IC package 1624 may take the form of any of the examples discussed above with reference to the IC package 1620.
The IC device assembly 1600 illustrated in
Additionally, in various examples, the electrical device 1700 may not include one or more of the components illustrated in
The electrical device 1700 may include a processor circuitry 1702 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor circuitry 1702 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1700 may include a memory 1704, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1704 may include memory that shares a die with the processor circuitry 1702. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 1700 may include a communication chip 1712 (e.g., one or more communication chips). For example, the communication chip 1712 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 1712 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1712 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1712 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1712 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1712 may operate in accordance with other wireless protocols in other examples. The electrical device 1700 may include an antenna 1722 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 1712 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1712 may include multiple communication chips. For instance, a first communication chip 1712 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1712 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1712 may be dedicated to wireless communications, and a second communication chip 1712 may be dedicated to wired communications.
The electrical device 1700 may include battery/power circuitry 1714. The battery/power circuitry 1714 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1700 to an energy source separate from the electrical device 1700 (e.g., AC line power).
The electrical device 1700 may include a display 1706 (or corresponding interface circuitry, as discussed above). The display 1706 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1700 may include an audio output device 1708 (or corresponding interface circuitry, as discussed above). The audio output device 1708 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1700 may include an audio input device 1724 (or corresponding interface circuitry, as discussed above). The audio input device 1724 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1700 may include a GPS circuitry 1718. The GPS circuitry 1718 may be in communication with a satellite-based system and may receive a location of the electrical device 1700, as known in the art.
The electrical device 1700 may include any other output device 1710 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1710 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1700 may include any other input device 1720 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1720 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1700 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1700 may be any other electronic device that processes data.
From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that enable customization of pigtail lengths of optical connectors. Additionally, using the example systems, methods, apparatus, and articles of manufactures disclosed herein creates customizable optical connectors without significant link losses by enabling high precision creation and alignment of the optical connectors.
Example methods, apparatus, systems, and articles of manufacture to enable customization of pigtail lengths of optical connectors are disclosed herein. Further examples and combinations thereof include the following:
Example 1 includes an apparatus comprising an affixed fiber array unit plug including a first optical fiber, a detachable fiber array unit plug including a second optical fiber, the detachable fiber array unit plug to be removably coupled to the affixed fiber array unit plug, and guide pins to interface with both the detachable fiber array unit plug and the affixed fiber array unit plug when coupled together, the guide pins to facilitate alignment of the first optical fiber with the second optical fiber.
Example 2 includes the apparatus of example 1, wherein the affixed fiber array unit plug is bonded to an optical component via the first optical fiber.
Example 3 includes the apparatus of example 1, wherein the detachable fiber array unit plug is bonded to a mechanical transfer ferrule via the second optical fiber.
Example 4 includes the apparatus of example 3, wherein the affixed fiber array unit plug includes a third optical fiber, and the detachable fiber array unit plug includes a fourth optical fiber to align with the third optical fiber, the second and fourth optical fibers arranged in a first array on the detachable fiber array unit plug and arranged in a second array on the mechanical transfer ferrule, an ordering of the second and fourth optical fibers in the first array different than an ordering of the second and fourth optical fibers in the second array.
Example 5 includes the apparatus of example 1, wherein the affixed fiber array unit plug includes a first groove, and the detachable fiber array unit plug includes a second groove, the first optical fiber disposed in the first groove, the second optical fiber disposed in the second groove.
Example 6 includes the apparatus of example 1, wherein the affixed fiber array unit plug and the detachable fiber array unit plug include grooves to interface with the guide pins.
Example 7 includes the apparatus of example 1, further including a retention mechanism to retain the detachable fiber array unit plug in engagement with the affixed fiber array unit plug, and to retain detachable fiber array unit plug and the affixed fiber array unit plug against the guide pins.
Example 8 includes the apparatus of example 7, wherein the guide pins are bonded to the retention mechanism.
Example 9 includes the apparatus of example 7, further including an alignment casing to support the guide pins.
Example 10 includes the apparatus of example 9, wherein the retention mechanism surrounds the detachable fiber array unit plug, the affixed fiber array unit plug, and the alignment casing.
Example 11 includes the apparatus of example 7, wherein the guide pins are longer than a combined length of the affixed fiber array unit plug and the detachable fiber array unit plug.
Example 12 includes the apparatus of example 7, wherein the retention mechanism includes a release mechanism that, when released, provides a compressive force to urge the detachable fiber array unit plug and the affixed fiber array unit plug against the guide pins, and when squeezed, removes the compressive force.
Example 13 includes the apparatus of example 12 further including a spring positioned between a distal end of the detachable fiber array unit plug and the retention mechanism, the spring to provide an axial retention force to facilitate engagement of the detachable fiber array unit plug to the affixed fiber array unit plug.
Example 14 includes the apparatus of example 12, wherein the retention mechanism attaches to a slot on an optical component.
Example 15 includes the apparatus of example 7, wherein the retention mechanism includes a spring to urge at least one of the detachable fiber array unit plug or the affixed fiber array unit plug against the guide pins, the spring to removably attach to an optical component.
Example 16 includes the apparatus of example 1, wherein the detachable fiber array unit plug is replaceable.
Example 17 includes the apparatus of example 1, wherein a length of the second optical fiber is customizable independent of a length of the first optical fiber.
Example 18 includes the apparatus of example 1, wherein the affixed fiber array unit plug includes a first unique identifier disposed thereon and the detachable fiber array unit plug includes a second unique identifier disposed thereon, the first unique identifier the same as the second unique identifier.
Example 19 includes a method comprising attaching optical fibers to a first ferrule, the first ferrule positioned between first and second ends of the optical fibers, attaching the first ends of the optical fibers to a second ferrule, and cutting the first ferrule and the optical fibers to obtain an affixed fiber array unit plug and a detachable fiber array unit plug.
Example 20 includes the method of example 19, further including aligning, using guide pins, the optical fibers on the affixed fiber array unit plug to the optical fibers on the detachable fiber array unit plug.
Example 21 includes the method of example 20, further including retaining the alignment of the optical fibers with a retention mechanism.
Example 22 includes the method of example 19, further including adding an identifier to the affixed fiber array unit plug and the detachable fiber array unit plug.
Example 23 includes the method of example 19, further including bonding the second ends of the optical fibers to an optical component.
Example 24 includes the method of example 19, wherein the detachable fiber array unit plug is a first detachable fiber array unit plug, the method further including coupling the first detachable fiber array unit plug to the affixed fiber array unit plug with a retention mechanism at a first point in time, and replacing the first detachable fiber array unit plug with a second detachable fiber array unit plug.
Example 25 includes an apparatus comprising first means for supporting a first array of optical fibers, second means for supporting a second array of optical fibers, the second supporting means separable from the first supporting means, and means for aligning the first array of optical fibers to the second array of optical fibers.
Example 26 includes the apparatus of example 25, further including means for retaining the first and second supporting means in engagement with the aligning means.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.
This invention was made with Government support under Agreement No. HR0011-19-3-0003, awarded by DARPA. The Government has certain rights in the invention.