Patent Application
20070070126
The present invention relates generally to printer heads, and more particularly to methods and apparatuses for implementing multi-via heater chips.
A number of printers, copiers, and multi-function products utilize heater chips in their printing heads for discharging ink drops from one or more ink vias. These heater chips typically provide only one heater array for each ink via that is disposed along one side of the ink via. In particular, as shown in
In addition, connections between the logic arrays and the heater arrays they address occupy a significant amount of space on the heater chips. In some instances, these connections may occupy as much space as the heater arrays themselves. As an example, as shown in
Accordingly, there is a need in the industry for heater chips that can provide for enhanced printing resolutions while reducing chip die sizes.
According to an embodiment of the present invention, there is a chip for use in a printing device. The chip includes a first heater array with a left side and a right side, a first ink via placed on the left side of the first heater array, a second heater array with a left side and a right side, where a right side of the first heater array faces the left side of the second heater array, a second ink via placed on the right side of the second heater array, and at least one logic array disposed between the first heater array and the second heater array.
According to an aspect of the present invention, the chip may further include a third heater array and a fourth heater array, where the third heater array and first heater array sandwich the first ink via and the fourth heater array and the second heater array sandwich the second ink via. The first and second ink via may include one of a cyan ink via, a magenta ink via, a yellow ink via, and a monochrome ink via. According to another aspect of the invention, the at least one logic array may include a first logic array for addressing the first heater array and a second logic array for addressing the second heater array, where the first logic array is substantially parallel to the second logic array. Alternatively or in addition, the at least one logic array may include a single logic array having first logic cells for addressing the first heater array and second logic cells for addressing the second heater array, where the single logic array is substantially linear. At least a portion of the first logic cells may be interleaved with at least a portion of the second logic cells, thereby making the single logic array non-contiguous. With such interleaving, a pair of second logic cells may be interleaved between a first pair of first logic cells and a second pair of first logic cells.
According to another embodiment of the invention, there is an integrated multi-via heater chip. The heater chip includes a first heater array having a left side and a right side, a first ink via positioned on the left side of the first heater array, a second heater array having a left side and a right side, where the first heater array and the second heater array are positioned opposite one another so that the right side of the first heater array is facing the left side of the second heater array, a second ink via positioned on the right side of the second heater array, and a first logic array positioned between the first heater array and the second heater array, where the first logic array includes a plurality of first logic cells for addressing the first heater array and a plurality of second logic cells for addressing the second heater array.
According to an aspect of the invention, at least a portion of the first set of logic cells and at least a portion of the second set of logic cells may be substantially aligned. The first logic cells may be interleaved with the second logic cells. According to another aspect of the invention, the heater chip may further include a third heater array positioned on the left side of the first heater array and a fourth heater array positioned on the right side of the second heater array, where the first ink via is positioned between the first heater array and the second heater array and the second ink via is positioned between the third heater array and the fourth heater array. In such an arrangement, the heater chip may further include a second logic array positioned on a left side of the third heater array and a third logic array positioned on a right side of the fourth heater array, where the second logic array includes at least a plurality of third logic cells for addressing the third heater array and the third logic array includes at least a plurality of fourth logic cells for addressing the fourth heater array.
According to yet another aspect of the present invention, at least a portion of control signals for the first logic cells may be routed between the first heater array and the first logic array and at least a portion of control signals for the second logic cells may be routed between the second heater array and the first logic array. The first heater array may include a plurality of blocks of heaters and the second heater array may also include a plurality of blocks of heaters, where each block of heaters in the first heater array is addressed by at least a portion of the first logic cells and where each block of heaters in the second heater array is addressed by at least a portion of the second logic cells.
According to another embodiment of the present invention, there is a method of fabricating chips for use in a printing device. The method includes providing a first heater array and a second heater array for a first ink via, where the first ink via is positioned between the first heater array and second heater array, providing a third heater array and a fourth heater array for a second ink via, where the second ink via is positioned between the third heater array and the second heater array and where a right side of the second heater array faces a left side of the third heater array, and positioning a first logic array between the second heater array and the third heater array, where the first logic array includes a plurality of first logic cells in communication with the second heater array and a plurality of second logic cells in communication with the third heater array.
According to an aspect of the present invention, at least a portion of the first logic cells may be connected in series to each other and at least a portion of the second logic cells may be connected in series to each other. In addition, at least a portion of the first logic cells may be interleaved between at least a portion of the second logic cells, thereby making the first logic array non-contiguous. In such an arrangement, the first and second logic cells may be arranged linearly. According to another aspect of the invention, at least a portion of the first and second logic cells may each include a shift register and a latch at an output of the shift register. According to yet another aspect of the invention, the method may further include positioning a second logic array on a left side of the first heater array and positioning a third logic array on a right side of the fourth heater array, wherein the second logic array includes third logic cells for communicating with the first heater array and wherein the third logic array includes fourth logic cells for communicating with the fourth heater array.
Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:
The present inventions now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the inventions are shown. Indeed, these inventions may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout.
According to a first aspect of the present invention, heater arrays may be positioned on both sides of at least a portion of the ink vias, which allow the ink vias to provide smaller ink drops in order to achieve higher printing resolutions. Each of these heater arrays may include a plurality of individual heaters fabricated as resistors in the heater chips. For example, these resistors may be thin-film resistors in accordance with an exemplary embodiment of the invention. These thin-film resistors may be formed of a variety of materials, including platinum, gold, silver, copper, aluminum, alloys, and other materials. The heaters may also be formed of other technologies besides thin-film resistors as known to those of ordinary skill in the art. When the heaters in the heater arrays are activated, they provide thermal energy to the ink via, and the ink is discharged.
Moreover, when heater arrays are positioned on both sides of vias in a multi-via heater chip, at least two heater arrays may be adjacent to each other. Thus, according to a second aspect of the present invention, a single, hybrid non-contiguous logic array may be disposed between adjacent heater arrays for addressing the adjacent heater arrays. This configuration reduces the area needed for the logic arrays, thereby allowing for a much smaller die size compared to the use of the wiring buses of
The heater arrays 204, 206, 210, 212, 216, 218, 222, and 224 illustrated in
Still referring to
According to an exemplary embodiment of the present invention, each group of two bits (known as a “primitive group”) in each of the cyan P-register 226, magenta P-register 228, and yellow P-register 230 logic arrays may address a block of heaters, perhaps 40 heaters, in the respective heater arrays 204, 206, 210, 212, 216, and 218. In certain embodiments where each P-register logic array 226, 228, and 230 includes 32-bits, this allows sixteen primitive groups within each P-register logic array 226, 228, and 230 to address up to a total of sixteen blocks of 40 heaters or a total of 640 heaters. Where each heater array includes 320 heaters, this allows each of the P-register logic arrays 226, 228, and 230 to address the two heater arrays surrounding their respective ink vias. One of ordinary skill in the art will recognize that the number of bits needed for the P-register logic arrays may depend at least in part on the size of the heater arrays and the groupings and addressing schemes for the heaters within the heater arrays. One of ordinary skill in the art will also recognize that the size of each primitive group may be more or less than two bits as necessary. For example, a primitive group may be four bits.
Like the P-register logic arrays 226, 228, and 230 discussed above, each group of two bits (also known as a “primitive group”) in the first and second monochrome P-register logic arrays 232 and 234, may address a block of heaters, perhaps 20 heaters, in the respective monochrome heater arrays 222 and 224. One of ordinary skill in the art will recognize that the number of bits required to address the blocks of heaters in a heater array may be vary without departing from embodiments of the present invention. For example, if the monochrome heater arrays 222 and 224 having 320 heaters each were addressed in blocks of 40 using two bit primitive groups, then the first and second P-register logic arrays 232 and 234 could be combined into a single 32-bit P-register logic array capable of addressing 640 heaters. Many other addressing variations will be readily apparent to one of ordinary skill in the art.
In accordance with a second aspect of the present invention, at least a portion of two different P-register logic arrays shown in
The logic cells 420a-n and 440a-n in
Once the PDATA has been stored as values in the logic cells 420a-n and 440a-n, these stored values are maintained at the output of the logic cells by a LOAD signal activating the parallel hold latches at the output of the logic cells 420a-n and 440a-n. This stored values maintained at the output of the P-registers may, in conjunction with one or more FIRE signals, allow the logic cells 420a-n and 440a-n to activate and deactivate the heaters within the respective heater arrays 206 and 210. In accordance with an embodiment of the invention, the logic cells 420a-n may utilize a different PDATA, CLOCK, LOAD, and FIRE signals than the logic cells 440a-n. One of ordinary skill in the art will recognize that other signals may be utilized with the logic cells 420a-n and 440a-n and heater arrays as necessary or desired.
In accordance with an exemplary embodiment of the present invention, the control signals for cyan logic cells 420a-n, which may include one or more of its PDATA, CLOCK, LOAD, and FIRE signals, may be routed between the cyan heater array 206 and the cyan/magenta P-register logic array 302 in
In the exemplary embodiment of
According to an exemplary embodiment of the present invention, the cyan P-register logic array 504 may include logic cells with 16 bits for addressing eight groups of 40 heaters (a total of 320 heaters) in the first cyan heater array 204. The cyan/magenta P-register logic array 302 may include logic cells with 32 bits—16 of which address eight groups of 40 heaters in the second cyan heater array 206 and 16 of which address eight groups of 40 heaters in the first magenta heater array 210. Similarly, magenta/yellow P-register logic array 502 may include logic cells with 32 bits-16 of which address eight groups of 40 heaters in the second magenta heater array 212 and 16 of which address eight groups of 40 heaters in the first yellow heater array 216. The yellow P-register logic array 506 may include logic cells with 16 bits for addressing eight groups of 40 heaters in the second yellow heater array 218. According to an exemplary embodiment of the invention, the first monochrome P-register logic array 232 may include logic cells with 32-bits for addressing 16 groups of 20 heaters in the first monochrome heater array 222. Similarly, the second monochrome P-register logic array 234 may include logic cells with 32-bits for addressing 16 groups of 20 heaters in the second monochrome heater array 224. One of ordinary skill will recognize that in other embodiments, 16-bits may be utilized to instead address 8 groups of 40 heaters in the first and second monochrome P-register logic arrays 232 and 234. One of ordinary skill will also recognize that in other embodiments, the yellow P-register logic array 506 and the first monochrome P-register logic array 232 may be combined, like the configuration shown in
While the primitive groups (e.g., groupings of 2 bits) in the P-register logic arrays disclosed in
Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
