Patent Application
20130332142
Power consumption is an important performance metric in the development of circuitry. Power consumption can be estimated in the design phase of a circuit with synthesis and simulation techniques that utilize, for example, the Verilog hardware description language (HDL) or the very high speed integrated circuit (VHSIC) hardware description language (VHDL). Nevertheless, such estimation is typically a complicated, time-consuming, and multistep process. To estimate the power consumption of a given application running on a particular circuit, high-level register-transfer level (RTL) code is typically first developed to describe the circuit. Subsequently, the RTL code is synthesized by a synthesis tool to produce a gate-level description. Finally, the power consumption for that particular application is estimated by simulating the running of the application on the circuit with a simulation tool that utilizes the gate-level description. In this manner, each application must ultimately be simulated to estimate its power consumption characteristics.
Embodiments of the invention provide novel methods and apparatus for performing power estimation for an application executed by a circuit. The power consumption is first estimated for a set of base events that can be executed by the circuit. These base events may include reading from a memory, writing to a memory, reading from a register, writing to a register, adding, multiplying, and so on. The application is then reduced to an equivalent sequence of base events selected from the set of base events. Once these steps have been performed, power estimation for the application can be estimated by summing the estimated power consumption for each base event in the equivalent sequence of base events for the application. In so doing, the application itself need not be separately simulated in order to estimate its power consumption. Substantial savings are thereby afforded in both time and other resources.
In accordance with an aspect of the invention, power consumption is estimated for an application being executed by a circuit. Power consumption values are estimated for a set of base events executed by the circuit. The application is then reduced to an equivalent sequence of base events selected from the set of base events. Lastly, the estimated power consumption values for the base events in the equivalent sequence of base events are summed.
In accordance with another aspect of the invention, an apparatus comprises a memory and at least one processor coupled to the memory. The at least one processor is operative to estimate power consumption values for a set of base events executed by the circuit. In addition, the at least one processor is operative to reduce the application to an equivalent sequence of base events selected from the set of base events. Finally, the at least one processor is operative to sum the estimated power consumption values for each of the base events in the equivalent sequence of base events.
Embodiments of the present invention will become apparent from the following description of embodiments thereof, which are to be read in connection with the accompanying drawings.
The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
The present invention, according to aspects thereof, will be described herein in the context of illustrative methods and data processing systems for estimating power consumption in circuits. It will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the present invention. That is, no limitations with respect to the specific embodiments described herein are intended or should be inferred.
As a preliminary matter, for the purposes of clarifying and describing embodiments of the invention, the following table provides a summary of certain acronyms and their corresponding definitions, as the terms are used herein:
A method in accordance with an illustrative embodiment of the invention for estimating the power consumption of an application being executed by a circuit may be conceptually separated into two phases: 1) an event-based power estimation phase, and 2) an application-based power estimation phase. As used herein, the term “application” is intended to be construed broadly and may comprise any sequence of instructions that can be executed by a processor, for example, a processor in a circuit under test.
Verilog and VHDL are very common hardware description languages for register-transfer and gate-level abstractions of circuits. Moreover, synthesis tools are available from a number of vendors including, for example, Synopsys®, Inc. (Mountain View, Calif., USA) and Cadence Design Systems, Inc. (San Jose, Calif., USA). These aspects of the circuit and others are described in a number of readily available references including, for example, S. Ramachandran, Digital VLSI Systems Design: A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog, Springer, 2007; and V. Pedroni, Digital Electronics and Design with VHDL, Morgan Kaufmann, 2008, both of which are hereby incorporated by reference herein.
Subsequently, a gate-level power simulation (i.e., analysis) of the circuit under test is performed in block 120 of
Tools for gate-level power simulations such as that performed in block 120 are also available from a number of commercial vendors. One popular choice is, for example, Primetime PX from Synopsys®, Inc., although there are several others. The results of the simulation in block 120 are stored in the event power database (DB) in block 135. The associations may, for example, be stored in the form of a table such as Table 1 shown in
Once so determined, the power consumption data stored in the event power database (block 135 in
The method 300 starts by taking an application (block 305) for which total power consumption is to be determined and reducing the application down to an equivalent sequence of base events selected from the set of base events stored in Table 1 (
register4=register3+register1*register2
can be reduced to six base events: 1) reading from a register (Read(register)); 2) reading from a register (Read(register)); 3) reading from a register (Read(register)); 4) performing a multiplication (Multiply); 5) performing an addition (Add); and 6) writing to a register (Write(register)).
With the application reduced from a sequence of higher-level program instructions to an equivalent sequence of base events for which power consumption values were estimated in phase one of the method, the estimation of the power consumption for execution of the application on the circuit under test becomes as simple as summing the estimated power consumption values for the base events in the equivalent sequence of base events. The power consumption values can be obtained from the event power database, also shown in
Notably, by performing the power estimation by summing an equivalent sequence of base events in the above-described manner, there is no longer a need to run a gate-level simulation for each application. Rather, once the event power database is populated by running the simulation for the one or more artificial programs, power estimations for any number of applications can be made without further simulations. Significant savings in time and other resources are thereby gained by implementing aspects of the invention when compared to conventional power estimation techniques.
For purposes of describing the present embodiment of the invention, the computer instructions (i.e., application software or firmware) stored in the memory 615 may be conceptually separated into an operating system (OS) module 625, a synthesis module 630, a simulation module 635, an event list compiler module 640, and a power calculation module 645. The OS module 625, when executed by the processing unit 605, allows the data processing system 600 to manage computer hardware resources and to provide common services for the other application software and firmware. The synthesis module 630, in turn, when executed by the processing unit 605, allows the data processing system 600 to perform the synthesis process in block 110 of
As is known in the art, at least a portion of one or more aspects of the methods and apparatus discussed herein may be distributed as an article of manufacture that itself includes a computer readable medium having non-transient computer readable code means embodied thereon. The computer readable program code means is operable, in conjunction with a computer system, to carry out all or some of the steps to perform the methods or create the apparatus discussed herein. The computer readable medium may be a recordable medium (e.g., floppy disks, hard drives, compact disks, EEPROMs, or memory cards) or may be a transmission medium (e.g., a network including fiber-optics, the world-wide web, cables, or a wireless channel using time-division multiple access, code-division multiple access, or other radio-frequency channel). Any medium known or developed that can store, in a non-transitory manner, information suitable for use with a computer system may be used. The computer-readable program code means is intended to encompass any mechanism for allowing a computer to read instructions and data, such as magnetic variations on a magnetic medium or height variations on the surface of a compact disk. As used herein, a tangible computer-readable recordable storage medium is intended to encompass a recordable medium, examples of which are set forth above, but is not intended to encompass a transmission medium or disembodied signal.
At least a portion of the techniques of the present invention may be implemented in an integrated circuit. In forming integrated circuits, identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes an element described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Any of the exemplary elements illustrated in, for example,
Moreover, it should again be emphasized that the above-described embodiments of the invention are intended to be illustrative only. Other embodiments may use different types and arrangements of elements for implementing the described functionality. These numerous alternative embodiments within the scope of the appended claims will be apparent to one skilled in the art given the teachings herein.
Lastly, the features disclosed herein may be replaced by alternative features serving the same, equivalent, or similar purposes, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
