Methods and arrangements for conditional execution of instructions in parallel processing environment

Abstract

Methods and processor architectures for the execution of instruction having a condition are disclosed. Very long instruction words can be loaded from a memory unit into an instruction word decoder and the decoder can separate the VLIW into processable sequences. Each processable sequence can be processable by a processing unit among a plurality of processing units. Each processable sequence can be executed independently in the absence of a condition in the processable sequences, and when the processable sequences contain a condition, processing units can be logically coupled together to add processing resources to a processing intensive condition type code to assist in disposing of the conditional execution quickly by assigning these additional resources.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

In the following the disclosure is explained in further detail with the use of preferred embodiments, which shall not limit the scope of the invention.

FIG. 1 is a block diagram of a processor architecture having parallel processing modules;

FIG. 2 is a block diagram of a processor core having a parallel processing architecture;

FIG. 3 depicts independent parallel execute operation of four parallel processing units;

FIG. 4 shows an exemplary diagram of fetch, decode, and execute stages of a parallel processing architecture;

FIG. 5 illustrates one example of a conditional execution of processing units coupled in pairs;

FIG. 6 shows one example of a conditional execution with multiple conditions;

FIG. 7 depicts one execution example of the conditional execution of six processing units coupled in pairs;

FIG. 8 shows an example of conditional execution using three conditions attached to one processing unit;

FIG. 9 shows an example of the conditional execution of two processing units attached to one condition, where an ‘if’-branch is executed if the condition is met, and an ‘else’-branch if it is not met;

FIG. 10 shows an example of the conditional execution of several processing units attached to one condition, where an ‘if’-branch is executed if the condition is met, and an ‘else’-branch if it is not met;

FIG. 11 shows an example of the conditional execution of multiple processing units attached to one condition as well as instructions from the decode and fetch stage;

FIG. 12 shows a flow diagram for conditional execution with causal coupling;

FIG. 13 shows a flow diagram for conditional execution of processing units using causal coupling; and

FIG. 14 shows a flow diagram for conditional execution not considering causal coupling.

Claims

1. A method for executing a very long instruction word (VLIW) comprising: loading a VLIW from at least one memory unit into an instruction word decoder;separating the VLIW into processable sequences, each processable sequence processable by a processing unit among a plurality of processing units;executing each processable sequence independently in the absence of a condition in the processable sequences; andcoupling processing units together when the processable sequences contains a condition.

2. The method of claim 1, further comprising assigning the processable sequence that contains the condition to a processing unit to create a distinguished processing unit and coupling at least one processing unit of the plurality of processing units to the distinguished processing unit for at least one clock cycle to facilitate processing of the condition and decoupling the at least one processing unit in response to the condition being processed.

3. The method of claim 1, further comprising coupling of at least one processing unit of the plurality of processing units to the distinguished processing unit for at least one future clock cycle and executing the instructions in said coupled processing units in said future clock cycle depending on the result of said distinguished processing unit.

4. The method of claim 1, wherein loading comprises generating a processing unit coupling control signal.

5. The method of claim 1, wherein separating comprises generating a processing unit coupling control signal.

6. The method of claim 1, wherein processing of the instruction having the condition comprises generating coupling signals and wherein coupling comprises hierarchical based coupling when no coupling instructions are available.

7. The method of claim 1, further comprising executing the processable sequence having the condition to determine a result and coupling processing units together in response to a result of the executing.

8. The method of claim 1, further comprising evaluating the condition by a distinguished processing unit and signalling a control unit in response to a result of the condition.

9. The method of claim 8, wherein the control unit can utilize the signal to couple processing units.

10. The method of claim 1, wherein the coupling of processing units is controlled by a control unit.

11. The method of claim 1, further comprising generating a signal indicating how many processing units to couple together in response to the condition being one of met or not met.

12. A very long instruction word (VLIW) processing apparatus comprising: a memory to store VLIWs;a decoder to separate the VLIWs into processable sequences, some of the processable sequences having a condition;a first processing unit coupled to the decoder; andat least a second processing unit coupled to the decoder, where the first processing unit and the at least a second processing unit each execute processable sequences independently of each other in response to no conditions in the processable sequences and the first processing unit and the at least second processing unit are logically coupled in response to a condition in the processable sequence.

13. The apparatus of claim 12, further comprising a control unit coupled to the first processing unit and to the at least second processing unit and to logically couple the first processing unit to the at least second processing unit in response to the condition.

14. The apparatus of claim 13 wherein the condition has a result that is one of a true result or a false result and the control unit couples the first processing unit to the at least one second processing unit in response to the result.

15. The apparatus of claim 12, further comprising a fetch module coupled to the decoder and to an instruction memory to load the decoder with the VLIW.

16. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program when executed on a computer causes the computer to: load a VLIW from at least one memory unit into an instruction word decoder;separate the VLIW into processable sequences, each processable sequence processable by a processing unit from a plurality of processing units, where in the absence of a condition in processable sequence the processing units will process the processable sequences independently; andcouple a processing unit to another processing unit for at least one clock cycle to facilitate processing of a processable sequence with a condition.

17. The computer program product of claim 16, further comprising a computer readable program when executed on a computer causes the computer to decouple the at least one processing unit in response to a control signal.

18. The computer program product of claim 16, further comprising a computer readable program when executed on a computer causes the computer to generate a processing unit coupling control signal.

19. The computer program product of claim 18, further comprising a computer readable program when executed on a computer causes the computer to generate a processing unit coupling control signal.

20. The computer program product of claim 16, further comprising a computer readable program when executed on a computer causes the computer to process the instruction having the condition and generate a coupling signal in response to results of processing the instruction.