Methods and arrangements for triggering detection, image correction or fingerprinting

Abstract

The present technology relates to image signal processing. One aspect of the present technology involves analyzing reference imagery gathered by a camera system to determine which parts of an image frame offer high probabilities of—relative to other image parts—containing decodable watermark data. Another aspect of the present technology whittles-down such determined image frame parts based on detected content (e.g., a cereal box) vs expected background within such determined image frame parts.

Description

BACKGROUND AND SUMMARY

The present technology helps reduce processing time and resource use to discover machine-readable indicia in imagery captured by camera-based systems.

Camera-based systems are widely used to monitor operation of industrial processes and/or facilitate checkout in retail settings (e.g., think grocery and big box stores). One example is in the food industry, where cameras are positioned at different locations along a production line that packages food, or that applies labels to food containers. Another example is a retail checkout station, where items are swiped in front of an often stationary point of sale (POS) scanner.

One of the functions performed by such camera systems is to sense and decode machine-readable markings. In the checkout example, machine-readable markings often carry product identifiers, e.g., GTIN, UPC and/or other codes. This is not a trivial task, given the often limited processing windows and computing resources in such camera systems.

While 1D (and sometimes 2D) barcodes have been used in such checkout and production environments, digital watermarking offers compelling improvements. In a product packaging context, digital watermarking may include a printed marking, e.g., included by modulating design artwork or sparsely peppered against a substrate or background color. The digital watermarking typically conveys a plural-bit data payload. In some, but not as a requirement for all embodiments, the presence of such marking is not generally apparent to an untrained consumer, who inspects a digitally watermarked package from a typical reading distance of 12-24 inches, in normal retail lighting (e.g., 75 to 100 foot-candles), and who has not previously been alerted to the watermarking's existence. Yet, when a camera captures imagery of such a watermarked package, and the imagery is analyzed by corresponding watermark decoding software, the markings can be discerned, and decoded to recover the plural-bit payload. In a retail setting, in addition to product packaging, product labels, hang tags, shelf labels, instructions, wrapping, and receipts can also be digitally watermarked.

Examples of digital watermarking and applications of such can be found, e.g., in assignee's U.S. Pat. Nos. 9,747,656, 9,635,378, 9,449,357, 9,401,001, 9,380,186, 6,614,914, and 6,345,104, which are each hereby incorporated herein by reference in its entirety, and U.S. Published Application No. US 2017-0024840 A1, which is also hereby incorporated herein in its entirety.

One aspect of the present technology involves analyzing reference imagery gathered by a camera system to determine which parts of an image frame offer high probabilities—relative to other image frame parts—of containing decodable watermark data.

Another aspect of the present technology whittles-down such determined image frame parts based on detected content (e.g., cereal box) vs expected background within such determined image frame parts.

Still another aspect is a method for processing a set of image areas within an image frame. The method includes the acts: for each image area, establishing a plurality of subareas, each subarea comprising n×m pixels, where n and m are both integers, each of the pixels including a value; for each subarea: determining an image characteristic representing the n×m pixels; comparing the determined image characteristic to a baseline characteristic associated with the subarea; and classifying the subarea as background or content based on said comparing; and triggering image distortion correction or signal decoding based on a classification from said classifying.

The triggering could be based on a plurality of classifications from said classifying.

The image characteristic may comprise a pixel mean value representing the n×m pixels. Or the image characteristic may comprise a pixel greyscale mean value representing the n×m pixels. Yet still, the image characteristic may comprise a brightness or luminance value associated with the n×m pixels.

The method may further comprise maintaining an array or table of baseline values associated with baseline characteristic, and maintaining a histogram of pixel values associated with each subarea. The histogram may be updated with the image characteristic. And the updated histogram may be used to update the baseline characteristic

Another aspect of the present technology includes a method comprising: obtaining image data captured by one or more retail scanner cameras; analyzing a subset of the image data to determine whether it represents a content object or background imagery, said analyzing yielding a determination; and triggering signal decoding or fingerprint extraction based on the determination.

Yet another aspect is a camera-based scanner comprising: one or more cameras; more or more processors configured for: analyzing image data captured by said one or more cameras to determine whether it represents a content object or background imagery, said analyzing yielding a determination; and gating signal decoding or fingerprint extraction based on the determination; and an output for outputting data from a signal decoding or fingerprint extraction.

The foregoing and other aspects, features and advantages of the technology will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary camera scanner system.

FIGS. 2A, 2B, 3A and 3B show different viewpoints that may be captured by the scanner system of FIG. 1.

FIG. 4 shows an example of three-faceted imagery captured by the tower camera system of the FIG. 1 scanner.

FIG. 5 shows an example of three-faceted imagery captured by the platter camera system of the FIG. 1 scanner.

FIG. 6 shows an example of parts of an image frame determined to offer high probabilities of containing decodable watermark data.

FIG. 7A shows an image processing flow for the four (4) parts identified in FIG. 6.

FIG. 7B shows the image processing flow of FIG. 7A, improved further with a content detector.

FIG. 8 is a flow diagram for operation of a content detector.

DETAILED DESCRIPTION

Retail checkout benefits from accurately identifying products for purchase. Consumer satisfaction is often enhanced when the identification proceeds in a time-efficient manner. Just think of all the time you've spent standing at a checkout line, wishing it would move faster. Camera-based systems capture images of moving objects. Consider an item being swiped, e.g., moved past, a stationary camera system. Such systems may include, e.g., CMOS or CCD image sensors, processing circuitry (or one or more processors) and decoding modules. Such decoding modules may configure a processor to detect and decode 1D, 2D or digital watermarking; and/or may be configured as dedicated or special purpose circuitry. An example camera system includes a retail scanner. Example commercially-available retail scanners include, e.g., Datalogic's Magellen 9800i series scanners, Zebra's MP6000 and MP7000 scanners, Honeywell's Stratos 2700 scanner, and NCR's RealScan bi-optic scanners.

Referring to FIG. 1, an illustrative retail scanner 10 includes a vertically-extending tower portion 12, and a horizontally-extending platter portion 14. Each portion includes a window 16, 18 through which one or more camera systems captures imagery of items presented for scanning.

In the FIG. 1 scanner, an arrangement of mirrors projects several different views of a retail product onto different parts of a camera sensor in the tower portion. Likewise for the platter portion. In particular, the optics arrangement in the tower captures two views looking out horizontally from the mid-height of the window 16, at angles of roughly +/−45 degrees. These two view axes cross each other over the platter window 18, so as to capture two different views of an object placed on window 18. This is illustrated in FIG. 2A.

Another mirror arrangement provides a third viewpoint, looking down, at an angle of roughly 45 degrees, from near the top of the tower window 16. This is illustrated in FIG. 2B.

The three views, as projected onto the tower image sensor, are termed “facets.”

A similar mirror arrangement is employed in the platter portion 14. Two views look up from the window 18 at angles of roughly +/−45 degrees. (Unlike the tower case, these two fields of view don't cross each other.) A third image is also captured by the platter camera sensor, looking up at a roughly 45 degree angle towards the tower. These views are illustrated in FIGS. 3A and 3B.

The projection of three different views onto a common image sensor in the tower portion, and the similar projection of three different views onto a common image sensor in the platter portion, yields composite imagery of the sort shown in FIGS. 4 and 5, respectively. (The center facet of FIG. 4 is void of product imagery because the product (a two liter drink bottle) was positioned a sufficient distance away from the tower window 16 that the downward-looking FIG. 2B view did not capture any of the product in its field of view.)

Camera-based retail scanning systems commonly capture between 30 and 100 frames of imagery every second. If real-time operation is to be achieved, such systems can only allocate a short interval to process each image. For example, if a system captures 60 frames each second, it can devote a maximum of 16.6 milliseconds to each image.

This time constraint is a particular challenge because product-identifying indicia (e.g., a barcode or digital watermark) may appear anywhere in the captured frames. Moreover, each captured image is commonly a synthesis of several different images—captured from different viewpoints by an optical arrangement including multiple mirrors. Searching the full extent of such a composite image in search of a decodable indicia is typically too time consuming. It is generally preferable to examine a limited number of image excerpts.

Once an image has been captured by a retail scanner, a task becomes to locate and read digital watermark indicia depicted somewhere in the image, quickly, before the next-captured image is presented for analysis.

In an exemplary system, the watermark payload is formatted into a binary sequence, which is encoded and mapped to the locations of a tile. For illustration, we describe an implementation of an I by J array of bit cells. The parameters, I and J are integers, and the tile is comprised of an I by I array of bit cells. The size of the tile is configurable and depends on application requirements, such as payload capacity per unit area, robustness, and visibility. Payload capacity increases per unit area with the increase in bit cells per unit area. This additional capacity may be used to improve robustness by redundantly encoding the payload in plural bit cells. Visibility tends to decrease with higher spatial resolution (higher CPI), as the Human Visual System (HVS) is less sensitive to changes at higher spatial frequencies. Examples of bit cell array sizes include 64 by 64, 128 by 128, 256 by 256 and 512 by 512. While each of these is square and has a dimension that is power of 2, the tile need not be so limited. For example, the tile may have another rectangular form. The bit cells correspond to spatial locations within a tile. In particular, the spatial locations correspond to pixel samples at a configurable spatial resolution, such as 75-600 DPI. The payload is repeated in contiguous tiles of artwork. An instance of the payload is encoded in each tile, occupying a block of artwork having a size that depends on the number of bit cells per tile and the spatial resolution. The tile is redundantly encoded in several contiguous tiles, providing added robustness, as the detector accumulates signal estimates for a payload across tiles. Additionally, the entire payload may be extracted from a portion of a tile in configurations where it is redundantly encoded in sub-tile regions.

A few examples will help illustrate the parameters of a tile. The spatial resolution of the bit cells in a tile may be expressed in terms of cells per inch (CPI). This notation provides a convenient way to relate the bit cells spatially to pixels in an image, which are typically expressed in terms of dots per inch (DPI). Take for example a bit cell resolution of 75 CPI. When a tile is encoded into an image with a pixel resolution of 300 DPI, each bit cell may correspond to a 4 by 4 array of pixels in the 300 DPI image. As another example, each bit cell at 150 CPI corresponds to a region of 2 by 2 pixels within a 300 DPI image, or a region of 4 by 4 pixels within a 600 DPI image. Now, considering tile size in terms of I by J bit cells and setting the size of a bit cell, we can express the tile size by multiplying the bit cell dimension by the number of bit cells per horizontal and vertical dimension of the tile. A tile with 128 by 128 bit cells is about 1.7 by 1.7 inches at a CPI of 75 and about 0.85 by 0.85 inches at a CPI of 150. Each provides the same number of embedding locations per tile (16,384), but occupies a different spatial area based on the spatial resolution the two-dimensional array of bit cells. At each of these 16,384 tiny regions, the luminance of the artwork is subtly increased or decreased to thereby encode a plural bit (e.g., 64-bit) payload.

One particular method of encoding a plural-bit watermark payload in imagery of host artwork begins by error-correction coding the payload to yield a large set of raw bits. (Techniques such as block codes, BCH, Reed Solomon, convolutional codes, and turbo codes may be used.) These raw bits are XORed with a pseudo-random noise sequence. Each result is spatially mapped to plural of the 16,384 different regions, and serves to tweak its luminance. The magnitudes of the tweaks may be adjusted, at different locations, in accordance with a model of human visual perception—as applied to the host artwork at the locations where the tweak values will be applied. The tweak values are then summed with the pixel values of the host artwork. Many digital watermarks also convey a calibration signal. This signal (which can comprise a known signal in a transform domain, such as a sparse array of peaks (e.g., 30 to 120 peaks, and preferably 50-70) in the Fourier magnitude domain) enables a watermark detector to discern how an image submitted for decoding has been geometrically transformed since it was originally encoded. For example, the calibration signal (which may be also called an orientation signal or reference signal) allows the detector to discern an amount by which the image has been shifted in X- and Y-directions (translation), an amount by which it has been changed in scale, and an amount by which it has been rotated. With knowledge of such “pose” information (geometric state information), the watermark detector can compensate for, e.g., counter-distort, the geometrical distortion of the image since its original watermarking, and can correctly extract the watermark payload. Example of orientation signals are provided, e.g., in assignee's U.S. Pat. Nos. 9,842,163, 7,986,807, 7,046,819, 6,614,914, 6,625,297, and in US Published Application No. US 2016-0217547 A1, which are each incorporated herein by reference in its entirety.

In an exemplary system, a watermark signal may include a rectangular pattern that is tiled across some or all of the product artwork. The pattern comprises an array of 128×128 “waxels”—defining 16,384 smaller regions where data representing pixel values of the artwork is increased or decreased to thereby encode a plural bit (e.g., 64-1028 bit) payload. While this discussion has generally referred to blocks and patches in terms of pixels, the detailed operations are more typically performed on the basis of “waxels,” as was previously noted. A waxel may be the same as a pixel. Or it may be a region of 2×2 pixels, 3×3 pixels, 4×4 pixels, etc.

In an illustrative embodiment, each watermark block is originally encoded and printed on the object artwork (e.g., label or carton) so that each of the 128×128 “waxels” comprising the block is represented by a 4×4 area of pixels, at 300 dpi (i.e., with the printed block spanning 512 pixels, or 1.70 inches, on a side).

In another illustrative embodiment, each waxel corresponds to a 2×2 pixel neighborhood, with a watermark block spanning an area of 256×256 pixels. Within a 1280×960 pixel image frame captured by a camera, which 256×256 block of pixels should be examined, first, for presence of digital watermarking? Which should be examined second, and so on?

A 256×256 block can take an enormous number of possible locations within the image frame. (For example, it can take (1280−256)*(960−256), or 720,896, different locations.) A brute force detection methodology, e.g., attempting to detect and decode watermarking at each possible different location, would require an unruly amount of time and processing resources, e.g., especially for processing-constrained retail checkout scanners.

To deal with this problem, one advantageous technology samples exemplary test images of products scanned by a retail scanner to identify candidate watermark locations that should be examined to decode digital watermarking. Assignee's U.S. Pat. No. 9,922,220, which is hereby incorporated herein by reference in its entirety, details some example detection processes.

In one embodiment of the present technology, a set of watermarked test images is analyzed (e.g., off-line, without the time constraints found in a typical retail checkout scenario) to determine which locations in an image frame captured by a particular retail scanner most commonly have a decodable watermark signal found therein. We'll call these locations “interesting locations” as a catchy, upbeat term. With reference to FIG. 6, areas 20, 22, 24 and 26 represent four (4) such interesting locations. Areas 22 and 24 are shown with trapezoidal shapes as a generic modeling of scanner distortion. For example, some image areas may have distortion (e.g., scaling and/or warping) introduced during image capture due to device characteristics such as lens distortion, focal length, object location, use of mirrors, swipe path, etc. Such distortion can be determined during the above-mentioned off-line analysis of test images. Of course, a particular scanner or other camera may have more or less than four areas identified as likely areas to include watermarking. Interesting areas may include, e.g., 2-26 such areas. However, reducing the number of image areas greatly reduces processing time and processing resources relative to processing most or all portions of an image frame. So, we have settled on 4 such areas for discussion purposes.

An encoded signal detection analysis may proceed according to FIG. 7A, where image data from interesting locations is analyzed to detect encoded signals. The image data can be downsampled, e.g., by a factor of p, where p in an integer, using, e.g., nearest-neighbor downsampling. One example is p comprising 2, 3 or 4; or 8, 16 or 32. Downsampling is helpful since image data can be processed faster with less pixels data to analyze. Other downsampling technology, e.g., bilinear, bicubic, etc. can be alternatively used. Raw image data could be analyzed instead, but with an associated processing time and resources cost that may not be tolerated by a single dad wrestling 2 kids in a grocery store checkout lane. The downsampling yields downsampled image regions corresponding to the interesting locations 20, 22, 24 and 26. In the case of anticipated or known distortion, e.g., corresponding to interesting locations 22 and 24, image distortion correction can be applied to the downsampled image regions. We discussed above how image distortion (e.g., scaling, warping, perspective distortion) can be determined during an offline analysis. With pre-determined distortion information, the image data can be rescaled and transformed (e.g., to remove warp or perspective distortion). The resulting downsampled image regions (perhaps distortion-corrected) are provided to an encoded signal detector, e.g., a digital watermarking detector.

Even further improvements in overall processing time and resource use can be achieved when signal decoding and/or distortion correction is triggered by detection of an object in one or more of the interesting locations. For example, a product swiped past a retail scanner may not yield a depiction of the product in one or more of the four interesting areas. So, there isn't any reason to analyze that vacant area to find a digital watermark. Or there need not be watermark decoding processing from an image frame captured during idol scanner moments, when no products are being scanned. In the FIG. 6 example, an object detected in one or more of the four (4) areas 20, 22, 24 and/or 26 triggers watermark detection in that area(s) where an object was detected.

With reference to FIG. 7B, an object detector (also referred to as a “Content Detector” in the figure) is operated prior to image distortion correction and/or signal decoding. The object detector determines whether the image data corresponding to an interesting location (e.g., 20, 22, 24, 26) includes content or simply contains ordinary background image data. “Ordinary background image data” may represent what the camera sees when an object (e.g., a cereal box) is not viewed. Let's now consider an in-counter point of sale (POS) scanner at a grocery store. The image background for any given image block will generally remain the same over time, until an object (e.g., a cereal box) is swiped in front of the scanner camera(s). The object detector preferably determines image characteristics associated with the background (e.g., static image content relative to an object swipe). These image characteristics can be used to form a baseline characteristic, and an object can be detected within an interesting area when the image characteristics deviate from the baseline characteristic.

One implementation of an object detector algorithm includes the following with reference to FIG. 8:

• • 1. Divide a region around an interesting area's center into smaller portions. For sure, not all of the image data from an interesting region need be considered. For example, image data corresponding to an interesting location 20, 22, 24 or 26 is designated, segmented or divided into n×m subareas, were n and m are integers. In one example, 4×4 subareas, each 24×24 pixels large, are designated around the interesting area's center. The total pixel area covered in this example is 96×96 pixels, and includes 16 subareas.
  • 2. An image characteristic is determined for each subarea. For example, a pixel value representation (e.g., pixel mean value, mean pixel greyscale value, brightness average, luminance mean value, or a standard deviation or extreme spread of such values) is determined for each subarea. For example, in a 24×24 pixel subarea, a mean pixel value from the 576-pixel set (24×24 pixel subarea) is determined.
  • 3. Test the determined image characteristic against an expected background baseline. For example, the content detector maintains or communicates with an array or table or memory location of background image characteristics (e.g., pixel mean values) for each subarea—we call these a “background keepout” value. The array or table can be built from, e.g., 10-10,000 or more test images obtained from the scanner. These can be analyzed offline; or, alternatively, the array or table can be dynamically updated with image data from each captured frame, or from every ith frame, where i is an integer. For example, every 2^nd, 3^rd, 5^th, 7^th, or 10^th or more frame is used to dynamically update the table or array or memory location. If a subarea image characteristic falls into this background keepout, this subarea will be labeled as background. One example models image content as a Gaussian random variable N(μ, σ). It can be assumed that the variance of pixels are constant and equal. The mean pixel value can be determined by assuming that at each pixel, the most reoccurring value (or value range) during test scans (or dynamically for every ith frame, where i is an integer) includes background image content. A histogram of test data can be generated, with a prominent pixel value in a subarea used as the mean, μ_Bⁱ, for that subarea. A threshold value r can be set to distinguish between content (e.g., cereal box) and background (e.g., idol background) of an observed pixel x₀ⁱ at each location from the background's mean μ_Bⁱ,|x₀ⁱ−μ_Bⁱ|τ
  • 4. If less than x out of the y subareas are labeled as background, the content detector has detected some content within an interesting area. For example, if less than 4-8 or less than 4-12 out of the 16 subareas are labeled as background, content is detected within the interesting area. We currently prefer triggering on less than 6 out of 16 subareas.
  • 5. Optionally, a newly determined image characteristic for a tested subarea from function 2, above, can be added into a respective subarea registry, e.g., a histogram.
  • 6. Optionally, the histogram in function 5, above, can be used to re-compute the background keepout values for each subarea after z entries, e.g., where z includes 50-1000 entries, preferably 100-500 entries, and even more preferably, 150-250 entries. This may be helpful in some case, e.g., where an encoded package is left in front of the scanner for some time. In such a case, the background characteristic would then be modeled after the encoded package and not the actual background.

Another optional approach is to disregard image data to build a characteristic if a block reaches a signal decode stage or signal detected stage. In other words, the above algorithms can be modified to stop blocks that have reached a signal read or detect stage from contributing to a learning histogram. Since these cases indicate a strong likelihood that the block includes an encoded signal, its image content can be excluded when formulating a background image characteristic.

As a variant to function nos. 1 and 2, above, we can calculate an image characteristic directly from the raw image data itself. In one example, we select relatively fewer pixels compared all pixels in a subarea. For example, 16 to 64 pixels (e.g., in a 4×4, 4×9, 5×5, 6×6, 7×8, 8×8 pixel pattern around the center of a subarea) from the raw image data are selected, and an image characteristic (e.g., pixel value mean) is computed from these 16 to 64 pixels. This is repeated for each identified subarea. This results in even further reduced processing time and resource savings compared to using all pixels within a subarea to generate an image characteristic. Or, a n×m pixel pattern is selected within an interesting area, e.g., centered around a center of the interesting area, where n and m are integers and n×m yields a smaller pixel number than the total number of pixels in the interesting area, and even more preferably yields a smaller pixel number than 24×24 pixels.

Returning to FIG. 7B, the content detector only triggers or calls a signal detector for interesting areas 20 and 24, since content was not detected in areas 22 and 26. This avoids unneeded distortion correction (path 22) and detection analysis (paths 22 and 26).

Subarea processing order can be varied according to the following. If using a multi-core or multi-thread processor, or multiple processors, processing of paths 20, 22, 24 and 26 (FIG. 7B) can occur in parallel. Otherwise, interesting areas can be ordered randomly for each captured image frame. For example, a random order may be 20, 22, 24 then 26; or 26, 24, 22, then 20; or 22, 20, 26, then 24, etc. The random order preferably changes from one image frame to the next. Further processing can stop for a particular interesting area if no content is found in that area. Or processing may continue on other interesting areas until all interesting areas are processed, or the number of interesting areas reaches a user-specified maximum. For instance, there could be 8-16 interesting areas, but a maximum processing limit is set to 3, so processing of interesting areas stops after finding 3 interesting areas that include content. The detector stage can start processing data from an interesting area as soon as the first one is identified, or can be configured to wait until all content-including interesting areas are identified. In this later case, the detector stage can use the same processing order that was used in processing interesting areas, or use a different strategy, e.g., one of the other above strategies.

A related technology applies to creating a faster perceived consumer experience when analyzing image content captured by mobile devices, e.g., iPhones, tablets, Pixel devices, or Galaxy phones, to detect signals encoded therein. Such phones include one or more multi-core processors, touch display screens, and one or more cameras.

When trying to scan or optically capture encoded items (e.g., packages) with mobile devices, we have found that users tend to aim their mobile device at a certain location of interest. For example, the users tend to aim their view screen at a package's company logo, nutrition label, or sometimes prominent text or colors. In some cases, such locations of interest do not include encoded information. Many decoding schemes tend to first analyze image data located at the center of a frame operating under the assumption that encoding is likely to be found in the area that a user is focused on. But if that location is not watermarked for any reason, center-block location will not find an encoded signal.

So, we can add random detection blocks to augment the center detection blocks. For example, consider a package that has a centrally located icon, which is not encoded, but includes encoding elsewhere in the image frame, it takes just a few more frames before a random block is likely placed at an area including encoding. Consider another use case where a user guides their camera to a location of interest from an edge of a package. Randomly placed detection blocks may catch an encoded area before the user reaches the area of interest. Randomly placed detection blocks, in concert with centrally placed detection blocks, provide a perceived faster detection experience to consumers.

Operational Environments

Having described and illustrated principles of the technology with reference to certain embodiments, it should be recognized that the technology is not so-limited.

For example, while the foregoing description has focused on digital watermark detection, the artisan will recognize that the detailed arrangements can also be used advantageously in extracting information from imagery by other techniques, such as by optical character recognition (OCR), barcode decoding, image fingerprint recognition (e.g., by SIFT, bag-of-features techniques, etc.), and recognition by neural networks (e.g., convolutional neural networks, as detailed in Applicant's pending patent application Ser. No. 15/726,290, filed Oct. 5, 2017, which is hereby incorporated herein by reference in its entirety). For example, our content detector technology (FIG. 7B) can be used prior to image fingerprint extraction.

Naturally, the particular numeric values detailed above are exemplary, and should not be taken as limiting the scope of the technology. An interesting area or subarea may be any size. A watermark block needn't be 128×128 pixels. A waxel needn't be a 2×2 pixel region. Etc., etc.

Although some of the above examples employed a single watermark detector, e.g., to successively examine multiple interesting areas, it should be recognized that multiple watermark detectors can run simultaneously, e.g., on different cores of a multi-core processor. Thus, for example, interesting area 20 may be submitted for decoding on Core2, while interesting area 26 is being watermark-decoded by Core1.

While the emphasis of the foregoing description has been on implementations in retail checkout, it will be recognized that the principles of this technology finds utility in various different contexts, including industrial applications (e.g., warehouse management and e-commerce fulfillment) and consumer (e.g., in connection with smartphones).

Computing devices suitable to perform the processes detailed herein are familiar to the artisan. In general terms, each may include one or more processors, one or more memories (e.g. RAM), storage (e.g., a disk or flash memory), a user interface (which may include, e.g., a keypad, a TFT LCD or OLED display screen, touch or other gesture sensors, one or more microphones, etc., together with software instructions for providing a graphical user interface), interconnections between these elements (e.g., buses), and an interface for communicating with other devices (which may be wireless, such as GSM, 3G, 4G, CDMA, WiFi, WiMax, Zigbee or Bluetooth, and/or wired, such as through an Ethernet local area network, etc.).

The arrangements detailed above can be implemented using a variety of different hardware structures, including a microprocessor, an ASIC (Application Specific Integrated Circuit) and an FPGA (Field Programmable Gate Array). Hybrids of such arrangements can also be employed, such as reconfigurable hardware, and ASIPs.

By microprocessor, Applicant means a particular type of hardware structure, namely a multipurpose, clock-driven, integrated circuit that includes both integer and floating point arithmetic logic units (ALUs), control logic, a collection of registers, and scratchpad memory (aka cache memory), linked by fixed bus interconnects. The control logic fetches instruction codes from a memory (often external), and initiates a sequence of operations required for the ALUs to carry out the instruction code. The instruction codes are drawn from a limited vocabulary of instructions, which may be regarded as the microprocessor's native instruction set.

A particular implementation of the above-detailed arrangements, e.g., the systems, methods and algorithms discussed relative to FIG. 7B, on a microprocessor involves first defining a sequence of algorithm operations in a high level computer language, such as MatLab or C++ (sometimes termed source code), and then using a commercially available compiler (such as the Intel C++ compiler) to generate machine code (i.e., instructions in the native instruction set, sometimes termed object code) from the source code. (Both the source code and the machine code are regarded as software instructions herein.) The process is then executed by instructing the microprocessor to execute the compiled code.

As noted, many microprocessors are now amalgamations of several other microprocessors (termed “cores”). Such arrangements allow multiple operations to be executed in parallel. (Some elements—such as the bus structure and cache memory may be shared between the cores.)

Examples of microprocessor structures include the Intel Xeon, Atom and Core-I series of devices. They are attractive choices in many applications because they are off-the-shelf components. Implementation need not wait for custom design/fabrication.

Closely related to microprocessors are GPUs (Graphics Processing Units). GPUs are similar to microprocessors in that they include ALUs, control logic, registers, cache, and fixed bus interconnects. However, the native instruction sets of GPUs are commonly optimized for image/video processing tasks, such as moving large blocks of data to and from memory, and performing identical operations simultaneously on multiple sets of data (e.g., pixels or pixel blocks). Other specialized tasks, such as rotating and translating arrays of vertex data into different coordinate systems, and interpolation, are also generally supported. The leading vendors of GPU hardware include Nvidia, ATI/AMD, and Intel. As used herein, Applicant intends references to microprocessors to also encompass GPUs.

GPUs are attractive structural choices for execution of the detailed algorithms, due to the nature of the data being processed, and the opportunities for parallelism.

While microprocessors can be reprogrammed, by suitable software, to perform a variety of different algorithms, ASICs cannot. While a particular Intel microprocessor might be programmed today to compute a Shannon entropy metric, and programmed tomorrow to prepare a user's tax return, an ASIC structure does not have this flexibility. Rather, an ASIC is designed and fabricated to serve a dedicated task, or limited set of tasks. It is purpose-built.

An ASIC structure comprises an array of circuitry that is custom-designed to perform a particular function. There are two general classes: gate array (sometimes termed semi-custom), and full-custom. In the former, the hardware comprises a regular array of (typically) millions of digital logic gates (e.g., XOR and/or AND gates), fabricated in diffusion layers and spread across a silicon substrate. Metallization layers, defining a custom interconnect, are then applied—permanently linking certain of the gates in a fixed topology. (A consequence of this hardware structure is that many of the fabricated gates—commonly a majority—are typically left unused.)

In full-custom ASICs, however, the arrangement of gates is custom-designed to serve the intended purpose (e.g., to perform a specified algorithm). The custom design makes more efficient use of the available substrate space—allowing shorter signal paths and higher speed performance. Full-custom ASICs can also be fabricated to include analog components, and other circuits.

Generally speaking, ASIC-based implementations of the detailed algorithms offer higher performance, and consume less power, than implementations employing microprocessors. A drawback, however, is the significant time and expense required to design and fabricate circuitry that is tailor-made for one particular application.

An ASIC-based particular implementation of the above-detailed technology, e.g., the systems, methods and algorithms discussed relative to FIG. 7B, again begins by defining a sequence of algorithm operations in a source code, such as MatLab or C++. However, instead of compiling to the native instruction set of a multipurpose microprocessor, the source code is compiled to a “hardware description language,” such as VHDL (an IEEE standard), using a compiler such as HDLCoder (available from MathWorks). The VHDL output is then applied to a hardware synthesis program, such as Design Compiler by Synopsis, HDL Designer by Mentor Graphics, or Encounter RTL Compiler by Cadence Design Systems. The hardware synthesis program provides output data specifying a particular array of electronic logic gates that will realize the technology in hardware form, as a special-purpose machine dedicated to such purpose. This output data is then provided to a semiconductor fabrication contractor, which uses it to produce the customized silicon part. (Suitable contractors include TSMC, Global Foundries, and ON Semiconductors.)

A third hardware structure that can be used to execute the above-detailed systems, methods and algorithms discussed relative to FIG. 7B, is an FPGA. An FPGA is a cousin to the semi-custom gate array discussed above. However, instead of using metallization layers to define a fixed interconnect between a generic array of gates, the interconnect is defined by a network of switches that can be electrically configured (and reconfigured) to be either on or off. The configuration data is stored in, and read from, a memory (which may be external). By such arrangement, the linking of the logic gates—and thus the functionality of the circuit—can be changed at will, by loading different configuration instructions from the memory, which reconfigure how these interconnect switches are set.

FPGAs also differ from semi-custom gate arrays in that they commonly do not consist wholly of simple gates. Instead, FPGAs can include some logic elements configured to perform complex combinational functions. Also, memory elements (e.g., flip-flops, but more typically complete blocks of RAM memory) can be included. Likewise with A/D and D/A converters. Again, the reconfigurable interconnect that characterizes FPGAs enables such additional elements to be incorporated at desired locations within a larger circuit.

Examples of FPGA structures include the Stratix FPGA from Altera (now Intel), and the Spartan FPGA from Xilinx.

As with the other hardware structures, implementation of each of the above-detailed algorithms begins by authoring the algorithm in a high level language. And, as with the ASIC implementation, the high level language is next compiled into VHDL. But then the interconnect configuration instructions are generated from the VHDL by a software tool specific to the family of FPGA being used (e.g., Stratix/Spartan).

Hybrids of the foregoing structures can also be used to perform the detailed algorithms. One structure employs a microprocessor that is integrated on a substrate as a component of an ASIC. Such arrangement is termed a System on a Chip (SOC). Similarly, a microprocessor can be among the elements available for reconfigurable-interconnection with other elements in an FPGA. Such arrangement may be termed a System on a Programmable Chip (SORC).

Another hybrid approach, termed reconfigurable hardware by the Applicant, employs one or more ASIC elements. However, certain aspects of the ASIC operation can be reconfigured by parameters stored in one or more memories. For example, a watermark calibration signal can be defined by parameters stored in a re-writable memory. By such arrangement, the same ASIC may be incorporated into two disparate devices, which employ different watermark calibration signals. One may be a system for reading watermark-encoded identifiers from objects on a checkout conveyor belt or clerk assisted swipe, which looks for a calibration signal comprised of one particular constellation of spatial frequency signals. A second may be an age verification terminal (e.g., at a liquor store) for reading watermark-encoded birthdate information hidden in a driver's license—which looks for a calibration signal comprised of a second, different constellation of spatial frequency signals. The chips are all identically produced in a single semiconductor fab, but are differentiated in their end-use by different calibration signal data stored in memory (which may be on-chip or off).

Yet another hybrid approach employs application-specific instruction set processors (ASIPS). ASIPS can be thought of as microprocessors. However, instead of having multi-purpose native instruction sets, the instruction set is tailored—in the design stage, prior to fabrication—to a particular intended use. Thus, an ASIP may be designed to include native instructions that serve operations prevalent in a particular application (e.g., pixel greyscale mean value). However, such native instruction set would typically lack certain of the instructions available in more general purpose microprocessors.

Reconfigurable hardware and ASIP arrangements are further detailed in patent published patent application 20170004597, the disclosure of which is incorporated herein by reference in its entirety.

Software instructions for implementing the detailed functionality can be authored by artisans without undue experimentation from the descriptions provided herein, e.g., written in C, C++, MatLab, Visual Basic, Java, Python, Tcl, Perl, Scheme, Ruby, etc., in conjunction with associated data.

Software and hardware configuration data/instructions are commonly stored as instructions in one or more data structures conveyed by tangible media, such as magnetic or optical discs, memory cards, ROM, etc., which may be accessed across a network.

Different of the functionality can be implemented on different devices. Thus, it should be understood that description of an operation as being performed by a particular device (e.g., a computer in a food packaging facility) is not limiting but exemplary; performance of the operation by another device (e.g., a cloud computer), or shared between devices, is also expressly contemplated.

In like fashion, description of data being stored on a particular device is also exemplary; data can be stored anywhere: local device, remote device, in the cloud, distributed, etc.

In addition to the patent documents referenced elsewhere, details concerning watermarking are known from Applicant's patent documents U.S. Pat. Nos. 6,122,403, 6,345,104, 6,424,725, 6,516,079, 6,590,996, 6,912,295, 6,988,202, 7,013,021, 7,076,082, 7,231,061, 7,978,875, 7,574,014, 7,013,021, 6,442,284, 20100150434, 20120078989, 20120129574, 20140052555, 20140304122, 20150278980, 20160063611, and 20160275639.

Linking from watermarks (or other identifiers) to corresponding online payoffs is detailed, e.g., in Digimarc's U.S. Pat. Nos. 6,947,571 and 7,206,820.

Arrangements for identifying regions within captured imagery that have higher probabilities of watermark detection are detailed in Applicant's U.S. Pat. Nos. 6,442,284, 6,516,079, 7,013,021 and 20150030201 (as well as in certain of the earlier-referenced documents). Another arrangement for setting camera exposure to capture imagery of watermarked objects is taught in U.S. Pat. No. 6,366,680. Publication 20160267620 teaches how watermarking can be used to ensure that components of multi-component packaging are assembled correctly.

This specification has discussed several different embodiments. It should be understood that the methods, elements and concepts detailed in connection with one embodiment can be combined with the methods, elements and concepts detailed in connection with other embodiments. While some such arrangements have been particularly described, some have not—due to the number of permutations and combinations. Applicant similarly recognizes and intends that the methods, elements and concepts of this specification can be combined, substituted and interchanged—not just among and between themselves, but also with those known from the cited prior art. Moreover, it will be recognized that the detailed technology can be included with other technologies—current and upcoming—to advantageous effect. Implementation of such combinations is straightforward to the artisan from the teachings provided in this disclosure.

While this disclosure has detailed particular ordering of acts and particular combinations of elements, it will be recognized that other contemplated methods may re-order acts (possibly omitting some and adding others), and other contemplated combinations may omit some elements and add others, etc.

Although disclosed as complete systems, sub-combinations of the detailed arrangements are also separately contemplated (e.g., omitting various features of a complete system).

While certain aspects of the technology have been described by reference to illustrative methods, it will be recognized that apparatuses configured to perform the acts of such methods are also contemplated as part of Applicant's inventive work. Likewise, other aspects have been described by reference to illustrative apparatus, and the methodology performed by such apparatus is likewise within the scope of the present technology. Still further, tangible computer readable media containing instructions for configuring a processor or other programmable system to perform such methods is also expressly contemplated.

To provide a comprehensive disclosure, while complying with the Patent Act's requirement of conciseness, Applicant incorporates-by-reference each of the documents referenced herein in its entirety including any appendices and all drawings. (Such materials are incorporated in their entireties, even if cited above in connection with specific of their teachings.) These references disclose technologies and teachings that Applicant intends be incorporated into the arrangements detailed herein, and into which the technologies and teachings presently-detailed be incorporated.

In view of the wide variety of embodiments to which the principles and features discussed above can be applied, it should be apparent that the detailed embodiments are illustrative only, and should not be taken as limiting the scope of the invention. Rather, Applicant claims as the invention all such modifications as may come within the scope and spirit of the following claims and equivalents thereof.

Claims

1. A method for processing a set of image areas within an image frame, the image frame having been captured by one or more cameras, said method comprising: for each image area within the set of image areas, establishing a plurality of subareas, in which each subarea of the plurality of subareas comprising n×m pixels, where n and m are both positive integers;for each subarea of the plurality of subareas: determining an image characteristic representing the n×m pixels;comparing the image characteristic to a baseline characteristic associated with the each subarea, the baseline characteristic comprising a representation of static image content; andclassifying the each subarea as background or as content based on said comparing, said classifying yielding a classification; andtriggering image distortion correction or signal decoding based on the classification.

2. The method of claim 1 in which said triggering is based on a plurality of classifications from said classifying.

3. The method of claim 1, in which the image characteristic comprises a pixel mean value representing the n×m pixels.

4. The method of claim 1 in which the image characteristic comprises a pixel greyscale mean value representing the n×m pixels.

5. The method of claim 1 in which the image characteristic comprises a brightness or luminance value associated with the n×m pixels.

6. The method of claim 1 further comprising maintaining an array or table of baseline values associated with the baseline characteristic.

7. The method of claim 6 further comprising maintaining a histogram of pixel values associated with each subarea.

8. The method of claim 7 further comprising updating the histogram with the image characteristic to yield an updated histogram.

9. The method of claim 8 further comprising updating the baseline characteristic with the updated histogram.

10. The method of claim 1 in which the baseline characteristic comprises a representation of static image content within a predetermined tolerance.

11. A non-transitory computer readable medium comprising instructions stored therein that, when executed by one or more electronic processors, cause the one or more electronic processors to perform the following: obtaining data representing an image frame, the image frame comprising a set of image areas, the image frame having been captured by one or more cameras, the set of image areas comprising a plurality of subareas, in which each subarea of the plurality of subareas comprises n×m pixels, where n and m are both positive integers;for each subarea of the plurality of subareas: determining an image characteristic representing the n×m pixels;comparing the image characteristic to a baseline characteristic associated with the each subarea, the baseline characteristic comprising a representation of static image content; andclassifying the each subarea as background or as content based on said comparing, said classifying yielding a classification; andtriggering image distortion correction or signal decoding based on the classification.

12. The non-transitory computer readable medium of claim 11 in which said triggering is based on a plurality of classifications from said classifying.

13. The non-transitory computer readable medium of claim 11 in which the image characteristic comprises a pixel mean value representing the n×m pixels.

14. The non-transitory computer readable medium of claim 11 in which the image characteristic comprises a pixel greyscale mean value representing the n×m pixels.

15. The non-transitory computer readable medium of claim 11 in which the image characteristic comprises a brightness or luminance value associated with the n×m pixels.

16. The non-transitory computer readable medium of claim 11 in which the instructions further comprise instructions that cause the one or more electronic processors to perform the following the act: maintaining an array or table of baseline values associated with the baseline characteristic.

17. The non-transitory computer readable medium of claim 16 in which the instructions further comprise instructions that cause the one or more electronic processors to perform the following the act: maintaining a histogram of pixel values associated with each subarea.

18. The non-transitory computer readable medium of claim 17 in which the instructions further comprise instructions that cause the one or more electronic processors to perform the following the act: updating the histogram with the image characteristic to yield an updated histogram.

19. The non-transitory computer readable medium of claim 18 in which the instructions further comprise instructions that cause the one or more electronic processors to perform the following the act: updating the baseline characteristic with the updated histogram.

20. The non-transitory computer readable medium of claim 11 in which the baseline characteristic comprises a representation of static image content within a predetermined tolerance.