Patent Application
20120212064
The present invention relates generally to control of a power generation system connected to a direct current source, and more particularly to a three-phase power generation system.
Photovoltaic panels (“PV”) provide electrical current when exposed to light. For a given level of insolation, the output voltage and current are a function of the load, and their product may be defined as the power delivered by the PV to its load. When the output is open circuit, voltage may be maximized and there may be no current. Likewise when the output terminals of a PV are shorted the current may be maximized but there may be very low voltage across the terminals. In both cases there may be no power delivered. The relationship between power and current is a nonlinear one which may be described by a characteristic current versus voltage curve (“IV curve”). The characteristic curve may be found by experimentation or by testing a panel when it completes manufacture. A complete characterization may be a family of curves, each curve corresponding to a specific value of insolation. It may be desirable to operate a given PV or collection of them at a condition that maximizes the power deliverable to a corresponding load.
PVs are expected by their makers to last at least twenty five years. However, the inverters used in today's installations require very large, high capacitance electrolytic capacitors. These capacitors suffer from temperature extremes, their lifetime particularly shortened by high temperature, such as that experienced on a roof. The liquid in these capacitors will eventually leak out of their canisters, and must be replaced in as little as five years by an experienced technician. This leads to an increased lifetime total cost of ownership. An example inverter circuit including an electrolytic capacitor 302 is illustrated in
The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate exemplary aspects of the invention, and, together with the general description given above and the detailed description given below, serve to explain features of the invention.
The various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the invention or the claims.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.
It may be desirable to operate a given PV or collection of PVs at a condition that maximizes the power deliverable to a corresponding load. The maximum power point (“MPPT”) may be considered to be the maximum area under the characteristic IV curve for a given level of insolation. A PV may be controlled by setting its output voltage, thus the current available may be a function of the illumination level. The power available from the PV is then a function of the controlled output voltage and the current generated by the panel. The voltage at which MPPT is attained may differ for different levels of illumination.
The light level experienced by a PV changes during a day as the sun rises and falls. In addition, passing clouds, birds, wind turbine blades, and aircraft may change the light incident on a PV at any instant. Longer term, a PV may experience a change of net light received due to dust and soiling accumulating on the panel, tree growth or nearby construction casting shadows on the panel, and cleaning which may remove dust and soiling. Thus, a control mechanism is needed to keep the PV operating at or near an ideal output voltage for producing power regardless of the light available at any given moment. Due to the possibility of a short duration change in light level, for example due to passing wind turbine blades, it is desirable for the control system to rapidly respond to short-duration changes.
In many instances PVs are used to generate electrical power for a grid system in which the power generated is three phase electricity. A power conversion apparatus, for example an array converter as described herein, may convert the direct current provided by a PV or collection of PVs into the desired three phase power. When the multiphase power is connected to a grid power system, noise and other errors in the grid power may affect the efficiency of power delivery to the grid by the power generation system. It may be beneficial for a power conversion control system to diminish any noise or mismatch between the power generator and a grid to which it is connected.
The amount of power derived from a PV may be substantial, enough to damage connected electronics or even the PV itself. It may be desirable to monitor actual and target operational conditions and override instant or anticipated operation outside of a safe operational envelope.
A direct current (DC) pulse amplitude modulated (“PAM”) current converter, denominated a “PAMCC”, may be connected to an individual solar panel (“PV”), and in some embodiments may be configured to output three-phase alternating current (AC). A representation of an example embodiment is illustrated in
A solar panel typically may be comprised of a plurality, commonly seventy-two, individual solar cells connected in series, wherein each cell may provide approximately 0.5 volt at some current, the current being a function of the intensity of light flux impinging upon the panel. The PAMCC may receive direct current (“DC”) from a PV and may provide pulse amplitude modulated current at its output. The pulse amplitude modulated current pulses may typically be discontinuous or close to discontinuous with each pulse going from near zero current to the modulated current and returning to near zero between each pulse. The pulses may be produced at a high frequency relative to the signal modulated on a sequence of pulses. The signal modulated onto a sequence of pulses may represent portions of a lower frequency sine wave or other lower frequency waveform, including DC. When the PAMCC's output is connected in parallel with the outputs of similar PAMCCs an array of PAMCCs may be formed, wherein the output pulses of the PAMCCs may be out of phase with respect to each other. An array of PAMCCs may be constructed to form a distributed multiphase inverter whose combined output may be the demodulated sum of the current pulse amplitude modulated by each PAMCC. If the signal modulated onto the series of discontinuous or near discontinuous pulses produced by each PAMCC is an AC current sine wave, then a demodulated, continuous AC current waveform may be produced by the array of PAMCCs. This AC current waveform may be suitable for use by both the “load”, meaning the premises that may be powered or partially powered by the system, and may be suitable for connection to a grid. For example, in some embodiments an array of a plurality of PV-plus-PAMCC modules may be connected together to nominally provide split-phase, Edison system 60 cps 240 volt AC to a home.
In the various embodiments, a PAMCC may be controlled by a controller executing a control loop. The control loop may be embodied in a program stored in memory that is executed by a processor or by a state machine, or by programmable logic, such as a field programmable gate array (“FPGA”) that is part of the controller. In some embodiments the control loop may be partitioned between firmware and logic. In the various embodiments the control loop may comprise a fast “inner loop” portion that runs continuously, and a one or more slower “outer loops” which may require more time to complete. The outer loops may from time to time change various values that may be saved in shared memory, wherein the faster inner loop may use an instant value that has been most recently saved into shared memory, and the outer loops may update their various values asynchronously to the inner loop.
In the various embodiments, startup values may be prepositioned in memory for a given three-phase PAMCC. During startup the prepositioned values may be used by the control loop, then the values may be modified during ongoing operation. In the various embodiments a table of look up values may speed up calculation speeds, wherein the values may be modified by a scaling factor responsive to instant conditions. The scaling factors may be influenced primarily by temperature and instant insolation, and, optionally, by other conditions. Each of the three phases may be corrected against an ideal output curve, thereby also balancing the power.
Various embodiments may be suitable for power conversion from any direct current source to an arbitrary output signal configuration. Examples of suitable direct current sources include batteries, wind turbines, geothermal, chemical, tidal and piezoelectric power sources. Examples of output signal configurations include sinusoidal alternating current, direct current, trapezoidal, Gaussian, square wave, triangle wave, and adaptive signals. Adaptive signals may include, for example, modifying the output waveforms on a cycle-by-cycle or other time period basis to adapt to, modify, or cancel the effect of transient noise or other conditions. Such signals may also include symbols modulated or superimposed on the base (carrier) signal as a method for communicating between modules, subsystems, or out of systems modes.
To clearly describe the operation of the present invention, the operation of a similar two-phase system is described first. The operation of a three phase system according to the present invention then involves a different output stage.
In a single phase system, a PAMCC may be connected to an individual solar panel (PV). A solar panel typically may be comprised of a number, commonly seventy-two, of individual solar cells connected in series, wherein each cell may provide approximately 0.5 volt at some current. The current produced by individual solar cells is a function of the intensity of light flux impinging upon the panel. The PAMCC may receive direct current (DC) from a PV and may provide pulse amplitude modulated current at its output. The pulse amplitude modulated current pulses may typically be discontinuous or close to discontinuous with each pulse going from near zero current to the modulated current and returning to near zero between each pulse. The pulses may be produced at a high frequency relative to the signal modulated on a sequence of pulses. The signal modulated onto a sequence of pulses may represent portions of a lower frequency sine wave (e.g., a 60 Hz AC current waveform) or other lower frequency waveform, including DC.
When the PAMCCs output is connected in parallel with the outputs of similar PAMCCs, an array of PAMCCs may be formed in which the output pulses of the PAMCCs may be out of phase with THD (Total Harmonic Distortion) PCM (Pulse Code Modulation). PCM is a digital representation of an analog signal where the magnitude of the signal is sampled regularly at uniform intervals, then quantized to a series of symbols in a digital (usually binary) code. THD is a measure of noise on a signal with respect to each other. An array of PAMCCs form a distributed multiphase inverter whose combined output is the demodulated sum of the current pulse amplitude modulated by each PAMCC. If the signal modulated onto the series of discontinuous or near discontinuous pulses produced by each PAMCC was an AC current sine wave, then a demodulated, continuous AC current waveform may be produced by the array of PAMCCs. This AC current waveform may be suitable for use by both the “load”, meaning the premises that may be powered or partially power by the system, and suitable for connection to a grid. For example, in some embodiments an array of a plurality of PV-plus-PAMCC modules may be connected together to nominally provide a split-phase, Edison system 60 cps 240 volt AC to a home.
Before discussing an array comprising a plurality of PV-plus-PAMCC modules, an individual PAMCC is described. For example, referring to
In the embodiment for a three-phase system illustrated in
The controller 412 may comprise a plurality of output terminals, each operated independently. Controller 412 output terminals 415, 416, 417, and 418 may be connected to the control terminals of four triacs (CRL11424; CR22423; CR12425; and CR21426 respectively) by four lines 419, 420, 421, and 422 respectively (inner-connections not shown). Each line, therefore each triac, may be independently controlled by control signals from the controller 412. The anode terminals of CRL11424 and CR22423 may be connected in parallel to the positive output terminal of TI 407. The cathode terminals of triacs CR12425 and CR21426 may be connected in parallel to the negative output terminal of TI 407. The cathode terminal of triac CR11424 and the anode terminal of triac CR12425 may be connected in parallel to a coil L12430. The cathode terminal of triac CR22423 and the anode terminal of triac CR21426 may be connected in parallel to a coil L22431.
A terminal 434 from coil L12430 is arbitrarily designated as providing a “phase I” (P1) output and a terminal 436 from coil L22431 is arbitrarily designated as providing a “phase 2” (P2) output. In some embodiments the coils L12430 and L22431 are embodied in a one-to-one transformer. In the embodiment illustrated in
Operation of the system may be implemented by control signals on lines 411 and 419 through 422. In particular the control signal sent to the control gate Q1G on line 411 and signals CR11T on line 419; CR22T on line 420; CR12T on line 421; and CR21T on line 422 may connect and disconnect the current provided by PV 401 in a sequence within the PAMCC 400 with a high-frequency period, for example 30 KHz, which provides a PCM signal which is modulated by a slower, 60 cycle pattern, thereby providing an output whose amplitude is a PAM signal approximating a sine wave.
Referring to
Circuit operation may begin with the solar panel 401 being exposed to sufficient light to produce significant current. The presence of the current may be observed as an increase in voltage across Q1404. At this point Q1404 may be initially turned on by applying a signal from controller 412 on line 411 between Q1G and Q1S. The interface between the controller 412 and the transistor Q1404 may be optically isolated, transformer coupled, or the controller 412 may be connected to Q1S. In this state L1406 and L2405 may begin to charge with current. When the voltage across PV 401 falls to a predetermined value, the time to charge the coils may be noted in order to calculate the current and standard operation may begin with the next grid zero crossing. In one embodiment this may be when the voltage at P1 crosses above P2 while P1 is going positive and P2 is going negative. At this point signals CR11T on line 419 and CR22T on line 421 may be asserted such that CR11424 and CR21426 may conduct when current may be applied to them.
CASE I: PWM modulation for positive half wave of the grid.
Referring to
The resonate frequency for the reconstruction filters may be chosen to be about one half the switching frequency of Q1404 so that one half of a sine wave of current may be provided to P1434 and P2436 for each pulse width modulated current pulse delivered to them. Since the resonate frequency of each reconstruction filter may be independent of the pulse width of current applied to it, and the charge in the instant current pulse applied to the reconstruction filter may be equal to the charge in the half sine wave of current delivered out of the reconstruction filter to the grid. Changes in the pulse width of input current may be reflected as changes in the amplitude of the output of the reconstruction filters. As the current in the inductors in the reconstruction filters returns to zero, the next pulse of current may be delivered to the capacitors of the reconstruction filters because the frequency of the reconstruction filters may be one half the rate at which pulse width modulated current pulses are produced by Q1404.
The off time of Q1404 may be modulated such that the width of current pulses produced may be in the shape of the grid sine wave. The reconstruction filters may transform this sequence of pulse width modulated current pulses into a sequence of pulse amplitude modulated current pulses whose amplitude follows corresponding points of the shape of the grid sine wave.
So long as the grid half cycle remains positive at the terminal P1434 relative to the output of terminal P2436, further current pulses may be produced by repeating the process described hereinbefore, beginning at “CASE I: PWM modulation for positive half wave of the grid”.
The negative zero crossing of the grid voltage is defined as the condition wherein the voltage at terminal P1434 may be equal to the voltage at terminal P2436 after P1434 has been more positive than P2436. Prior to the negative zero crossing, Q1404 may be turned on, thereby removing current from CR11424 and CR21426. At this point the signals CR11T in line 419 and CR21T in line 421 may be de-asserted, preventing triacs CR11424 and CR21426 from conducting current during the grid negative half cycle. After the negative zero crossing, with the voltage of terminal P1434 more negative than the voltage of terminal P2436, the signals CR22T 420 and CR12T 421 may then be asserted, enabling CR22423 and CR12425 to conduct when current is applied to them.
CASE 2: PWM modulation for negative half wave of grid
Referring to
The reconstruction filters for Case 2 may be the same components as described in association with Case I; their design and operation are not repeated here.
The off time of Q1404 is modulated such that the width of current pulses produced may be in the shape of the grid sine wave. The reconstruction filters may transform this sequence of pulse width modulated current pulses into a sequence of pulse amplitude modulated current pulses whose amplitude follow corresponding points of the shape of the grid sine wave.
So long as the grid half cycle remains negative, with the voltage of terminal P1434 more negative than the voltage of terminal P2436, further current pulses may be produced by repeating the process described above, beginning at “CASE 2: PWM modulation for negative half wave of grid.”
The positive zero crossing of the grid voltage may be defined as the condition wherein the voltage at terminal P1434 is equal to P2436 after the voltage at terminal P1434 has been more negative than the voltage of terminal P2436. Prior to the positive zero crossing, Q1404 may be turned on, removing current from triacs CR12425 and CR22423. At this point the signals CR12T 421 and CR22T 420 may be de-asserted, preventing triacs CR12425 and CR22423 from conducting current during the grid positive half cycle. After the positive zero crossing with P1434 more positive than P2436, signals CR11T 419 and CR21T 421 may be asserted, enabling triacs CR11424 and CR21426 to conduct when current is applied to them.
With the grid again positive, the process may again return to the process described above, beginning with the section labeled CASE 1: PWM modulation for positive half wave of the grid.
In
Following on the summation of the currents of two PAMCC 400 outputs,
One of several ways to choose the phasing of the arrayed PAMCCs 400 may be for each PAMCC 400 to be pre-assigned a timing slot number, with the first slot being scheduled following a zero crossing and each PAMCC 400 firing its PAM signal in the predetermined (i.e., assigned) sequence. In some embodiments, especially where the number of PVs may be large, the phase relationship of individual PAMCCs may not be controlled, in that they will naturally be phase separated across a cycle without deterministic phase scheduling.
In an alternative embodiment, illustrated in
In another alternative embodiment, two pairs of transistors may be used in the output switching section of the single transistor Q1404 to replace CR11T 424 and CR12T 425. Each pair of transistors may allow the voltage to be higher or lower on either side of the transistor pair. Of each pair, one transistor may function in a manner similar to an efficient diode, and the other may function as a switch because the normal voltage during an ON state may be in one direction from high to low.
In some embodiments the system may be shut down for safety, maintenance, or other purposes. One example of a shut-down system is illustrated in
A solar panel may be controlled by an electronic module, the module including means for measuring the temperature of the panel cells, the voltage across the panel, and for controlling the power (current) provided by the panel. A solar panel may be expected to provide a certain output voltage under good operating conditions, as determined by specification, characterization data, or by the experience derived by accumulating performance data over time. The current available may be a function of the intensity of sunlight incident upon the panel, and the voltage a function of the temperature of the cells, assuming otherwise normal conditions for the cells. As described above, a weak cell, due to damage, deterioration, soil, or simply partial shading of the panel, may not provide the same power as may the other, unaffected cells. Because all cells in a string are electrically in series, the current must be in common. Therefore the weak cell may adjust for the instant lower power capacity by lowering the voltage for that cell. Again because the cells are electrically connected in series, the voltage across the string may be the sum of the voltages of all the cells in the string. When a cell in the string loses some voltage, the whole string may lose voltage as well.
An electronic module typically tests a panel periodically, for example once per hour, to determine the maximum power point (MPPT) operating condition. This may be accomplished by varying the current demanded from a panel, measuring the voltage across the panel, then determining the power for that condition as the product of voltage times current. By varying across a certain range of currents, a peak power point may be found. Previously, such MPPT testing was done without regard to whether the condition selected may drive a weak cell in a string into a forward bias condition, thereby causing the bypass diodes to be forward biased, as described hereinbefore.
In the various embodiments, the electronic module may first determine the temperature of the solar panel cells, determine expected panel voltage for the temperature found, and may not allow the current to cause the voltage to drop more than a predetermined amount below the expected voltage. For example, in one embodiment the maximum value below MPP to be allowed may be:
RT MPP−tolerance−degradation(temp)
Wherein RT MPP may be the maximum power point condition for room temperature, “tolerance” may be a value provided by the solar panel manufacturer, and degradation(temp) may be the diode drop value that results from increasing temperature, for example −2.1 my/degree C. for a silicon solar cell. These values may be different for other solar cell chemistries.
As a result, if there were in fact bypass diodes the bypass diodes may never be forward biased, therefore the diodes may not be needed and a solar panel paired with the various electronic module embodiments may be made without bypass diodes, thereby saving the area that would be required for the interconnect of the bypass diodes.
The various embodiments avoid the condition of a hot spot without the use of an efficiency-lowering protection diode. The various embodiment methods assume an apparatus may be used to control the operating conditions of the panel, wherein the apparatus includes means for measuring the total voltage across the strings and means for changing the operating conditions of the panel. Bypass diodes may not be needed nor used, saving the area required for interconnect as required by previous methods. In the various embodiments, the instant voltage may be compared to the expected voltage for a measured operating temperature. If the voltage is less than expected by more than a certain amount, the power (current) demanded from the panel may be reduced such that the voltage may be less than a diode drop of the expected voltage, thereby avoiding a hot spot. In this manner, reducing the current may ensure that the voltage does not decrease below a determined safe limit. With hot spots (i.e., reverse biasing of a weak cell), avoided, bypass diodes may not be needed.
While the preceding description of the pulse amplitude modulation current converter technology addressed a two-phase system, the technology may also be applied to three-phase electrical systems such as typical in electric utility grids.
For a commercial power generator, the generation system may be connected to a low impedance three phase grid, wherein the power (therefore, the voltage-current product) may be kept the same. Accordingly, for a system according to the various embodiments the power in each of the three phases may be equal.
In a system according to the various embodiments, current may be driven from a common reference of a given polarity to two terminals of the opposite polarity. Referring to
Now referring to
In the example of
A switch Q11806, typically a MOSFET, may be driven ON in response to a signal on line 1808 from the controller 1812, thereby charging the coils L11802 and L21804 with current from the photovoltaic panel 1830, as described in the operation of the two-phase system above. Though discussed in relation to an example MOSFET, switch Q11806 may be any known type of technology capable of performing a switching function, including relays, transistors, bi-polar transistors, insulated-gate bipolar transistors (IGBTs), silicon carbide MOSFETs, Gallium nitride transistors, thyristors, NMOS FETs, series connected MOSFETs, thyristor emulators, and diodes in series with IGBTs to name just a few. Referring to the example of
To illustrate the commutation effect of the thyristors,
The process described above may be repeated so long as the phases are within a given sixty degree range. In each case, the thyristor first turned ON may result in the greater voltage change from the common reference. After a time, the thyristor that may result in the lower voltage change may be turned ON. Therefore, during a given sixty degree period the common reference point may always be the same, and during the first thirty degrees one phase may be farther away from the common reference, and during the second thirty degrees the other phase may be farther away. To include all twelve thirty degree time phases, the following thyristors may be controlled to turn ON first, then second for each window per Table 1.
In Table 1 the annotations refer to the thyristor labels shown in
T
p
=T−T
S1
−T
S2
The time period T should be related to a higher frequency than the frequency of the grid being powered. In one embodiment the period T may be related to a frequency that is about 504 times the frequency of the grid, wherein the grid frequency is 60 Hz in the United States and is 50 Hz in most of the rest of the world. The current in each time period of
where VO1 is defined as the open circuit voltage for the power rail that is to be driven first, Vi is the voltage from the photovoltaic panel 1830, and L is the equivalent inductance of the two coils L11802 and L21804, including the effect of mutual inductance. Similarly, the current at the next time period may be calculated from:
where V02 is defined as the open circuit voltage for the power rail that is to be driven second. Referring to
Expanding terms in the equation yields:
which after dropping out canceled terms results in:
The average current during the time period TS1 may be calculated by:
where KR is a conductance term controlled by a slow “outer loop” to provide the current needed. Rewriting terms yields:
By defining the terms
the following equation can be solve for TS1:
Similarly for TS2:
As before we define the terms:
where EPV and RPV are the Thévenin equivalent of the photovoltaic panel.
A solar powered current source will eventually be unable to provide enough current to meet the demand of the load as the sun sets or storm clouds move in. As the target current approaches the maximum available the target current is gradually reduced to minimize THD.
The various embodiments for controlling a three-phase PAMCC module may include an apparatus for controlling the operation of a PV. For example, the various PAMCCs in an array converter system, each connected to a corresponding PV and further connected in parallel with other PAMCCs, may be controlled to provide a three phase alternating current output. The output voltage may be controlled to match that of a connected grid power system. The current, and therefore power, available may be determined based on the radiance impinging on the PV, efficiency, and other factors. By controlling each PV to operate at or near its individual maximum power point condition, the power available from the system as a whole may be increased as well.
Referring to
The processor 2120 may include an ADC 2123 configured with three inputs or a single input with a MUX (not shown) to sense voltage at the output terminals 2108, 2110, 2112. The ADC 2123 may be configured to provide a digital representation of the sensed voltage to the processor 2120 firmware. In the various embodiments the ADC 2123 may be a discrete ADC which may provide its data output on a bus or via a serial link to the processor 2120. The ADC 2123 may include inputs corresponding to the positive 2122 and negative 2124 terminals of a solar panel, simplified in
A coil L12140 and a coil L22142 may provide energy storage. Unfolding circuits 2610, 2164, and 2166 may connect the reconstruction filters 2107, 2019, and 2111 to the controller 2116. A connection between coils L12140 and L22142 may be closed or opened by a switch ST 2114, whose control gate may be controlled by the controller 2116 via the main gate driver circuit 2162. By properly timing the opening and closing of the switch ST 2114 and two of the three output terminal switches, for example SWA 2102 and SWB 2106, a boost converter may be formed, thereby providing current through Phase A and Phase B to Phase C.
At the time of manufacture, a PAMCC 2100 register in NVM 2121 may be populated with values for TS1 and TS2 which have been predetermined for each switching time, for example 30 μSec, of the PAMCC 2100. Other switching times may be used. These values may be determined by simulation or by laboratory experimentation to determine typical values. In the various embodiments a table value may correspond to the number of clock ticks for a given pulse time. When the PAMCC 2100 begins actual operation these values may be used for initial conditions, then adapted to actual conditions. The initial TS1 and TS2 values may be saved for an entire 360 degree cycle, or values for sixty degrees saved, the index pointer starting over after each sixty degrees. The TS1 and TS2 initial values may be saved in tables TINIT1 and TINIT2. In the various embodiments TINIT1 and TINIT2 may be sixteen bit registers. Other bit widths may be used. Additionally, the PAMCC 2100 may store multiple temperature curves and thermal coefficients for use with the various embodiments.
α=αNOM+α11(VRMS−VRMSNOM)+α12(VIN−VINNOM).
A nominal value for a is needed. In the various embodiments a nominal value for a may be found while the PAMCC 100 under test is in operating mode. A typical United States three phase grid voltage of 110 volts RMS (defined as VRMSNOM) may be supplied in block 2202 to the output terminals 2108, 2110, 2112. A typical solar panel provided with typical radiance, or a solar panel simulator or other source of direct current, may be connected in block 2204 across the input terminals 2122, 2124 of the PAMCC 2100. The voltage that a panel will produce is a function of how much current is taken from it at a given radiance level, which is simply described by a family of IV curves for the panel. Assuming the initial TS1 and TS2 values have been previously written into the tables TINIT1 and TINIT2 in NVM 2121, the test may begin with a very high value of α in block 2206, which the control loop uses to scale the TS1 and TS2 table values (discussed in detail below) to produce the VRMS output. Because VRMSNOM is being provided by a grid simulator, which may be more powerful than the PAMCC, the three-phase output of the PAMCC 100 is known to be VRMSNOM, while VIN from the PV will be a value depending upon the IV characteristics of the PV or PV simulator (or other source of direct current) and the operation of the PAMCC 2100. The value of α may be slowly decreased while the PV output voltage VIN is observed in block 2208. In determination block 2210 the controller may determine if VIN is equal to VINNOM. If VIN is not equal to VINNOM (i.e., determination block 2210=“No”), at block 2208 monitoring of VIN may continue. If VIN is equal to VINNOM (i.e., determination block 2210=“Yes”), at that point (VIN−VINNOM)=(VRMS−VRMSNOM)=0, therefore a now equals αNOM. The value of αNOM may be saved at block 2212, for example in NVM 2121. VINNOM may be found by testing a sample of the production PV panels or from specifications for a panel provided by the manufacturer.
While the grid simulator is still attached to the output terminals 2108, 2110, 2112 of the PAMCC 2100, α may be changed such that VIN no longer equals VINNOM at block 2214, so now α12 is known and may be saved to nonvolatile memory (NVM) at block 2216:
The difference between VIN and VINNOM should be large enough to correspond to several least significant bits (LSBs) of the PAMCC ADC 2123. In the various embodiments approximately two volts may be used.
Next the grid power supply may be removed 2218 and a variable resistive load may be connected at block 2220 to the three-phase output terminals 2108, 2110, 2112 such that VRMS is approximately two volts above VRMSNOM while a is changed to hold VIN=VINNOM at block 2222. In that condition α11 is calculated at block 2224 as:
and α11 is saved to NMV 2121.
This procedure may be accomplished during the manufacturing of a PAMCC 2100. Its purpose may be to provide startup values such that when a PAMCC 2100 is operated for the first time it will have reasonable starting values. Once a PAMCC 2100 is operational, the process described in
PVs may be tested by the manufacturer after assembly. Included in the data collected may be data associating a voltage and a corresponding current at certain temperatures and radiances. For example, a manufacturer may heat a given panel to the maximum temperature expected in operation, then remove the heat and expose the panel to a nominal amount of light, for example 0.5 sun and record the voltage and corresponding current produced as a function of temperature while the panel cools. This data is denominated the panel's “IV curve.” The IV curve may then be used, sometimes with other factors, during operation by the PAMCC 2100 as a model for dynamically calculating the maximum power point condition.
Control Loop
As described below, in any sixty degree phase segment there may be two output terminals connected one at a time in a predetermined order to the third output terminal during a switching time T. It is not important which two phases are selected and in which order their switches are closed. The switch amongst SWA 2102, SWB 2104, and SWC 2106 that is connected first may be connected for a first time duration TS1. The switch that is connected second may be connected for a second time duration TS2. The switch ST 2114 may be opened at the beginning of the switching time, then closed for the time duration TP. The timing of these switches may be determined by the control loop.
In the various embodiments, adjustments to the control loop may be segmented into those processes that can be executed quickly (fast enough to be accomplished within a single switching cycle time) and other processes that require more time to complete.
When a PAMCC 2100 is operated for the first time, the initial value of a, found previously, may be used. In succeeding loops a may be updated at block 2306, depending upon the instant value of another scale factor γ. If γ is not numerically equal to one, at block 2306 a new value for α may be found by
αNEW=αOLD*γ
The value of γ may be reset to be equal to a numerical value of one at block 2305.
Alternatively, some embodiments determine a new value for α at block 2306 by
αNEW=p*αOLD*γ+(1−p)*αOLD,
where p<1, for example p=0.5, then reset γ at block 2305 by
γ=αNEW/αOLD
In block 2308, the two tables TBL1 and TBL2 may be populated by scaling the corresponding values of TINIT1 and TINIT2 per the formulas
T
S1TBL1
=T
INIT1*α and
T
S2TBL1
=T
INIT2*α.
In a similar fashion, tables TBLKO1 and TBLKO2 may be populated at block 2310. Values may be found for each switching time and the tables saved in registers. In the various embodiments the tables TBL1 and TBL2 may be ten bit registers. Using values expressed in fewer bits (e.g., 10 bits) shortens the time required for math operations.
During operation, the PAMCC 2100 may determine the voltage VRMS across a rolling window of several grid cycles, for example ten cycles. VRMS may then be evaluated as an ideal voltage VIDEAL at any instant in time by using a sine function. In this operation the ADC 2123 may read the instant output voltage of each of the two driven phases and compare the value read to the ideal voltage for that time period. Note that the phases may be offset from each other. Any difference may be denominated dVOUT1 and dVOUT2. Referring to
T
S1OUT
=T
S1TBL1
*γ−KO
1*(dVOUT1) and
T
S2OUT
=T
S2TBL2
*γ−KO
2*(dVOUT2),
where KOn (n=1,2) is the ratio (TsINITn/VIDEAL). In some embodiments the evaluation of terms may be made faster by populating a table of KOn values for a given sixty degree phase window, wherein KOn is evaluated for each switching time. The KOn tables TBLKO1 and TBLKO2 may be repopulated at block 2310 of each cycle of the loop 2300 illustrated in
The switching times may be determined during one switching cycle, and applied during a next succeeding switching cycle time, with these two processes running concurrently. Depending upon the conversion speed of the ADC 2123 and the conversion time available, conversion of a dVOUT value may lag by one or more switching cycles.
Still referring to
T
S1TEMP
=TBL1*γ and
T
S2TEMP
=TBL2*γ
dVOUT1(ΔVO1) may be determined in block 2506. TS1OUT may be calculated according to the equation below in step 2508.
T
S1OUT
=T
S1TEMP
−K
1
*dVOUT1
dVOUT2(ΔVO2) may be determined in step 2510. TS2OUT may be calculated according to the equation below in block 2512.
T
S2OUT
=T
S2TEMP
−K
2
*dVOUT2
The scaling factor γ may be updated in block 2514 using equation 1 (EQ1)
γNEW=γOLD−KS*(VIN−VTAR). [EQ1]
This may provide feedback to steer VIN towards the value desired for maximum power point delivery. The value of KS may be determined such that stability is maintained. For example, in some embodiments a value of Ks may be found by equation 2 (EQ2):
K
S=1/(50*VTAR) [EQ2]
γ is intended to be maintained at a value of approximately one. In the slow outer loop method 2300, a may be updated at block 2306 using the instant value of γ, then the stored value of γ is reset to one at block 2305.
The temperature of a PV 401, as measured at the back skin of the panel, plus measured values for voltage and electrical current at the output terminals, together with an electrical and thermal model of the panel, may analytically determine a voltage/current condition corresponding to the maximum power point (“MPP”). Temperature change may be relatively slow, and therefore dealt with by a slow outer control loop (method 2300,
Referring to
In a more general case, the MPP voltage for a range of irradiance values will follow a curve as a function of the MPP current. In the various embodiments the MPP controller, as described above, may operate using a table approximating the IV curve to be followed. If the temperature of a PV 401 (sensed via the back skin temperature sensor) changes, the new MPP curve and its approximation as a table may be calculated by the external loop using method 2300.
Sometimes a PV 401 may not be uniformly illuminated. For example, falling leaves, overhead wind turbine blades, bird droppings, soil, or passing clouds may cause some or as few as one cell in an array of cells of a full PV panel 401 to be shaded. The risk of a shaded cell entering reverse breakdown and dissipating a large amount of power is highest when there is strong illumination over the panel generally but a single cell is shaded. There are two cases of shading to be considered: shading in a cell that is increasing; and shading in a cell that is decreasing.
If a cell is shaded relative to the cells in the rest of an array, the IV curve of the panel changes shape because all other cells have the same characteristic, but the shaded cell (in series with the other cells of a common string) has a limited photocurrent. The characteristic curve may be very similar to that illustrated in
The voltage drop may be mainly on the shaded diode. So the voltage across the shaded diode may be the voltage difference between the nominal curve and the one with partial shading. For a given PV 401 operating condition, a higher voltage may always be safer than a lower voltage, in that a higher voltage may result in a lower current. So in the various embodiments the voltages corresponding to the MPP, Hot Spot Suppression (“HSS”), and safe operation may be compared and the higher of the three selected. Safe operation is a design consideration, wherein a PV 401 manufacturer may specify the maximum power that a PV cell may deliver without damage. A PV 401 manufacturer may desire to limit the voltage across a reversed cell and may therefore specify a limit voltage as a voltage corresponding to safe operation. Alternatively, a PV 401 manufacturer may limit the reverse power (PLim). From the PLim the manufacture may determine a voltage corresponding to safe operation that may be the limited reverse voltage (Vrev
V
rev
lim
=P
Lim
/I
Panel
The fast loop 2500 may follow the MPP and safety limit and effectively protect the shaded diodes from excessive reverse voltage. The slow loop 2300 may determine whether the inner loop 2500 is in a regular MPP condition or a hot spot protection condition. In the later case the slow loop 2300 may determine whether the limit was triggered by partial or uniform shading by observing the MPP position with respect to the regulation point.
Piece Wise Linear Method
In the various embodiments, control of a PV 401 may be effected by a piecewise linear (“PWL”) method. A PWL method may drive the operating point of a panel to be part of a piecewise linear curve with respect to a calculated I-V curve. In such a method the target voltage VTAR may be determined by equation 3 (EQ3):
V
TAR
=V
ZERO−(I−Ioffset)×KR, [EQ3]
where Vzero and KR are constant, Ioffset (in counts) may be based on the ADC result for zero coil current, and I may be the instant ADC value for the current measurement path. The loop may run once every switching cycle, while the current may be updated as fast as possible.
A piecewise linear method may be implemented in an MPP controller by a table of values for Vzero, KR and Ioffset appropriate for various regions corresponding to different desired control behaviors. The values on one line of the table may be applied if I (the instant coil current) is larger than Ioffset on a certain line and smaller than the Ioffset on the line above (the top line corresponds to a single ended comparison).
Referring to
A table may be constructed corresponding to
Consider an example wherein the instant current value I is 4000 mA. This value falls within the range corresponding to the middle row of Table 1, which corresponds to the regulation zone 3104. VTAR can be calculated using the EQ3 formula above, with the values for Ioffset, VZERO, and KR found in Table 2. Examination of Table 2 and EQ3 reveals that within the regulation zone 3104 the load line is a vertical line; that is, a constant voltage VZERO. Above the transition point 3116, corresponding to the top line of Table 1, KR is a negative number, thus VTAR increases. Current I may increase, but at a much slower rate than in the regulation zone.
Likewise for instant current I below transition point 3118, KR is a positive number and Ioffset is a negative number. KR being a positive number and Ioffset being a negative number causes the system to drive down the value of current I by increasing the voltage output of PV 401. VTAR may subsequently be used in EQ1 and EQ2 in the inner loop method 2500 and in turn in the outer loop method 2300.
It should be noted that the regions depicted in
V
TAR
n
=V
TAR
n−1
+K
S×(Vzero−(I−Ioffset)×KR−VTAR
where VTAR
In some embodiments dynamic resistance may be used to determine if a panel has experienced a change in overall insolation, or if one or more cells have become partially shaded. This is important if, for example, the operating point has been moved by the PWL protection limit to a new operating condition. The PWL protection limit may be provided by a fast loop for preventing damage due to a hot spot, as previously discussed. In various embodiments a recovery process may determine a new operating condition.
Upon a first measurement, a panel may be determined to be operating at its maximum power point 3706 on the I-V curve 3704. At a subsequent measurement the operating point may be determined to be at the condition denominated as 3708 by the fast loop of the PWL method. The condition 3708 corresponds to the point at which a current curve 3710 intersects the PWL protection curve 3106. However, the control loop 2300 (
At block 3815 Tp may be increased by an amount expected to increase the panel voltage V by approximately one volt. Increasing Tp may be beneficial because increasing the voltage of a panel may be safer than decreasing the voltage of a panel. At the new operating condition resulting from the increase in Tp, at block 3820 V and I for the panel may be read, and ΔI and ΔV may be calculated by taking the instant values of V and I read at this new operating point and subtracting the previous values for 1 and V determined before increasing Tp. At block 3825 dynamic impedance may then be found according to:
The manufacturer of the solar panel typically provides a value for the shunt resistance, Rp, of the panel, determined by testing at the time of manufacture. Using the shunt resistance Rp and the dynamic impedance Rdy found at block 3825, and the uniform dynamic resistance Rfy_unif calculated in block 3810, at determination block 3840 the dynamic impedance Rdy is compared to the result of the sum of the uniform dynamic resistance and one half the shunt resistance (Rdy_unif+Rp/2*Nbr of cells). The scale factor of (½) is an arbitrary selection; greater or lesser values may be used. What matters is that the discrimination level is spaced from the two impedances that need to be discerned (Rdy_unif and Rdy_unif+Rp/Nbr of cells). If the dynamic impedance Rdy is greater than the result of the sum of the uniform dynamic resistance and one half the shunt resistance (Rdy_unif+Rp/2*Nbr of cells), (determination block 3840=“TRUE”), the change in operating condition (for example, the determined new operating point 3708 illustrated in
With a new I-V curve established, the PWL tables may be updated at block 3855, and at block 3850 the operating point is driven to the Vmp point along the newly established I-V curve.
If the dynamic impedance Rdy is less than the result of the sum of the uniform dynamic resistance and one half the shunt resistance (Rdy_unif+Rp/2*Nbr of cells), (determination block 3840=“FALSE”), the I-V curve determined at block 3805 actually is the instant I-V curve, and at block 3855 the PWL tables may be updated. At block 3860 the operating point is driven to the Vmp point along the I-V curve determined at block 3805.
State Diagram Method
In some embodiments control of a PV 401 may be effected by a parameterized model of the panel data that is instantiated in a programmable processor. An example of such a state diagram is illustrated in
Using the intrinsic model illustrated in
The locus of Vmp may be calculated as a function of photocurrent current at nominal temperature by using the panel model. The junction temperature may be calculated based upon the back skin temperature. The Vmp locus may be recalculated using a new Tj value. In some embodiments, the temperature model may not be updated unless there is a change of Tj larger than 5° C. (˜1.2V).
The temperature needed to evaluate the panel electrical model may be the junction temperature Tj. Tj may be measured directly if the panel includes a temperature sensor that is integrated with the cells, or a spare cell may be used to measure the temperature at the level of the cells. Tj may be determined indirectly by measuring the temperature on the back skin of the panel.
Referring to the thermal model shown in
(Tj−Ta)/(Rf+Rcf)+(Tj−Ta)/(Rcb+Rb)=Pin
Assuming Rcf>Rb, then Pin≈((Tj−Ta)/(Rcb+Rb)=(Tj−Tb)/Rcb) in the static case.
Tj=Tb+Pin*Rcb
Pin=−Ii×Vi+Pth
where Pth is the thermal input power resulting from photon absorption. Pth may be extracted from measured electrical data and meteorological data for a site, the (−Ii×Vi) term is the power that is generated electrically and is transferred to the power modulator. For a clean panel, a value of Pth proportional to Iph current may be used due to the almost linear dependency of Iph to the illumination.
Tj=Tb+Pin*Rcb=Tb+(ξIph−IiVi)Rcb
where ξ is the model parameters that describes the Pin proportionality to Iph.
Initially, the system 3200 may start at in an initial state 3208 which assumes a non-uniform shading environment and needs to find Vmp. Regulation begins at block 3208 at Voc and transitions via pathway 3224 to state NI 3220.
System 3200 may be in (an assumed) state NI 3220 and may slowly walk Vtar towards Vmp of the uniform shaded case by dropping the voltage by a voltage increment, such as 1 volt direct current (VDC), such as approximately 1 VDC, such as 2VDC to 1.75VDC, 1.75VDC to 1.5VDC, 1.5VDC to 1.25VDC, 1.25VDC to 1VDC, 1VDC to 0.75VDC, 0.75VDC to 0.5VDC, 0.5VDC to 0.25VDC, 0.25VDC to 0.01VDC, such as less than 1VDC, such as more than 1VDC, such as approximately 0.5VDC, or such as approximately 0.1VDC. Additionally, the voltage increment may be a voltage selected to allow minimal power variation near a maximum power point of the photovoltaic panel, PV 401, such as a power variation such as 1 watt (W), such as 2W, such as 10W to 5W, 5W to 4W, 4W to 3W, 3W to 2W, 2W to 1W, 1W to 0.5W, 0.5W to 0.4W, 0.4W to 0.3W, 0.3W to 0.2W, 0.2W-0.1W, 0.1W to 0.5W, 0.5W to 0.4W, 0.4W to 0.3W, 0.3W to 0.2W, 0.2W to 0.1W, or such as 0.01W. System 3200 may slowly walk Vtar towards Vmp of the uniform shaded case by dropping the voltage by a single voltage increment at a time while calculating the input power, keeping track of the maximum value. If Vmp is approached by less than the voltage increment a determination that the system 3200 is actually in the uniform shading case may be made, and the system 3200 performs operational controls 3238 to transition to the US state 3212.
In the NI state 3220, if power decreases by more than 1% of the actual maximum value so far, the maximum may be reached, and PV 401 voltage may be decreased by 0.5V. The PAMCC 400 may set up a regulation table with current limit and voltage regulation at the determined value and a safety limit below flash data, for example 2.0 VDC, scaled for Tj, and the system 3200 may perform operational controls 3228 to transition to the NS state 3218.
In the NS state 3218, if there is a non-uniform shading condition, and power increases, the system 3200 may perform operational controls 3230 to transition to the NI state 3220.
In the NS state 3218, if there is a non-uniform shading condition, and power is decreasing, then the new Vmp may be tracked and the system 3200 may perform operational controls 3232 to transition to the ND state 3216. In the ND state 3216, the regulation voltage may be increased by 1.0 VDC.
In the NS state 3218, if power decreases operational controls 3226 may be performed to transition the system 3200 to the NI state 3220.
In the NS state, if power increases, voltage may be increased by 1.0 VDC at a time while keeping track of the maximum. When power decreases by more than 1% of the maximum value so far, voltage may be decreased by 1.5VDC and the PAMCC 400 may set up a regulation table with current limit and voltage regulation at the determined values and safety limit at 2V below flash data scaled for Tj. Operational controls 3234 may be performed to transition to the NS state 3218.
If the system is in a uniform shading environment, the PAMCC 400 may build the regulation table based on assumed current limit, voltage regulation at Vmp@ max irradiance, safety limit 20. VDC below nominal flash data, adjusted for Tj.
If the operating point results in the protection region, regardless of the instant state, operational controls 3257 may be performed to transition to the P state 3206. The protection region may be triggered (reached) anytime the panel current reduces. The panel current may be reduced due to uniform or non-uniform shading conditions. However, a fast loop method 2500 may not know the reason for the current drop, and to protect against unsafe conditions the P state 3206 may be entered and the uniform or non-uniform shading condition may be determined.
In the P state 3206, while increasing voltage by 1 volt direct current (VDC) steps, if power increases then voltage may be increased by 0.5V and operational controls 3222 performed to transition to the NI state 3220, then operational controls 3228 may be performed to transition to the NS state 3218. Then the PAMCC 400 may build a regulation table with current limit and voltage regulation at the determined values and may set a safety limit at 2V below the flash data, adjusted for Tj. In an alternative embodiment (not shown) transition from the P state 3206 directly to the NS state 3218 may be performed.
In the P state 3206, if power decreases, then operational controls 3248 may be performed to transition to the UD state 3214, where the PAMCC 400 may use the original Vmp and may set up a regulation table with current limit and voltage regulation at the determined values and may set a safety limit at 2 VDC below the flash data, adjusted for Tj.
At the US state 3212, if current increases operational controls 3242 may be performed to transition to the UI state 3210, and the PAMCC 400 may set up a regulation table with current limit and voltage regulation at the determined values and may set a safety limit at 2 VDC below the flash data, adjusted for Tj.
At the US state 3212, if current decreases, operational controls 3244 may be performed to transition to the UD state 3214. The controller may determine if the PV is in a uniform or partial shading condition (i.e., the operating condition should be for uniform or partial insolation) by increasing voltage by a voltage increment, such as approximately 1 VDC. such as 1 volt direct current (VDC), such as approximately 1 VDC, such as 2VDC to 1.75VDC, 1.75VDC to 1.5VDC, 1.5VDC to 1.25VDC, 1.25VDC to 1VDC, 1VDC to 0.75VDC, 0.75VDC to 0.5VDC, 0.5VDC to 0.25VDC, 0.25VDC to 0.01VDC, such as less than 1VDC, such as more than 1VDC, such as approximately 0.5VDC, or such as approximately 0.1VDC. Additionally, the voltage increment may be a voltage selected to allow minimal power variation near a maximum power point of the photovoltaic panel, PV 401, such as a power variation such as 1 watt (W), such as 2W, such as 10W to 5W, 5W to 4W, 4W to 3W, 3W to 2W, 2W to 1W, 1W to 0.5W, 0.5W to 0.4W, 0.4W to 0.3W, 0.3W to 0.2W, 0.2W-0.1W, 0.1W to 0.5W, 0.5W to 0.4W, 0.4W to 0.3W, 0.3W to 0.2W, 0.2W to 0.1W, or such as 0.01W.
At the UD state 3214, if a partial shading case is determined, the processor may perform operational controls 3236 to transition to the NS state 3218. If power increases then voltage may be increased by 0.5 VDC and the PAMCC 400 may set up a regulation table with current limit and voltage regulation at the determined values, and may set a safety limit at 2V below the flash data, adjusted for Tj.
At the UD state 3214, if a uniform shading case is determined, operational controls 3246 may be performed to transition to the US state 3212. The original Vmp may be returned to and the PAMCC 400 controller may set up a regulation table with current limit and voltage regulation at the determined values and may set a safety limit at 2V below the flash data, adjusted for Tj.
In the UD state, periodic testing may be performed to determine that the PV 401 is still in fully shaded (uniform) case, increasing voltage by a voltage increment such as 1 volt direct current (VDC), such as approximately 1 VDC, such as 2VDC to 1.75VDC, 1.75VDC to 1.5VDC, 1.5VDC to 1.25VDC, 1.25VDC to 1VDC, 1VDC to 0.75VDC, 0.75VDC to 0.5VDC, 0.5VDC to 0.25VDC, 0.25VDC to 0.01VDC, such as less than 1VDC, such as more than 1VDC, such as approximately 0.5VDC, or such as approximately 0.1VDC. Additionally, the voltage increment may be a voltage selected to allow minimal power variation near a maximum power point of the photovoltaic panel, PV 401, such as a power variation such as 1 watt (W), such as 2W, such as 10W to 5W, 5W to 4W, 4W to 3W, 3W to 2W, 2W to 1W, 1W to 0.5W, 0.5W to 0.4W, 0.4W to 0.3W, 0.3W to 0.2W, 0.2W-0.1W, 0.1W to 0.5W, 0.5W to 0.4W, 0.4W to 0.3W, 0.3W to 0.2W, 0.2W to 0.1W, or such as 0.01W. As the voltage is increased by the voltage increment, if power increases the voltage may increase by 0.5V and the PAMCC may set up a regulation table with current limit and voltage regulation at the determined values and may set a safety limit at 2V below flash data, adjusted for Tj. The system transitions 3236 to the NS state 3218. If the power does not increase, the controller may return to the original Vmp and set up a regulation table with current limit and voltage regulation at the determined values and may set a safety limit at 2V below flash data, adjusted for Tj. At this point the system transitions 3246 to the US state 3212.
If the current increases beyond the higher limit in the MPPT regulation segment the inner loop transitions in the current limiting segment, the outer loop observes this and transitions (arc 3545) to the CL 3204 state. In this state if current increases further the outer loop will transition to the STOP 3202 state via the 3250 transition arc. Other hardware errors or operating conditions like switching errors, input bound conditions, arithmetic exceptions, license expiration, could set the transition to STOP 3202 over 3252 arc. If current falls back then the outer loop will follow the inner loop to UD state.
While discussed in relation to a PAMCC the MPPT control, piecewise linear method, and state machine processes may be used in conjunction with any controller and are not dependent on the use of a PAMCC in a solar panel system. The various embodiments described herein may provide a combined method for controlling solar panel system operations using a calibrated panel model and panel back skin temperature based MPPT determination, identifying uniform versus non-uniform panel shading conditions, and setting protection limits as a form of hot spot suppression all in a unified control routine.
Power Line Communication
The PAMCC 400 may be configured to communicate information to other PAMCC units as well as to centralized controllers or monitoring servers via power line communications over the same wires that deliver generated electric power. As discussed above, the output signal configurations of the PAMCC 400 may include adaptive signals by modifying the output waveforms on a cycle-by-cycle or other time period basis to include symbols modulated or superimposed on the base (carrier) signal. These additional signals may be modulated onto the base signal using any known modulation scheme, including as examples, amplitude modulation (AM), frequency modulation (FM), phase shift keying (PSK), and quadrature amplitude modulation (QAM). Such additional signal may be included as a modulated ripple on the base signal, or as small a modification of the base signal (e.g., in amplitude, frequency or a combination of both) which can be recognized by a receiver circuit configured to detect such modulation without adversely affecting the three-phase power base signal required by the electrical grid. Information may be encoded in such power line modulations using any known information coding technique, including one bit, two bit and four bit encoding. Further, since the power lines coupled to the electrical grid are likely to be noisy, the information encoding mechanisms may also implement well known methods for detecting and correcting errors (e.g., parity bits, forward error correct (FEC) encoding, etc.), and providing protections against data loss (e.g., interleaving, Viterbi encoding, etc.). Such power line communications may be implemented within the PAMCC modules by including a transceiver circuit which includes a data encoding module and a modulator for modulating encoded data onto the power line signal, and a demodulator configured to recognized adaptive signal present on the power line signal and translate (i.e., demodulate) the received adaptive signals into data that may be processed by a processor of the PAMCC, the controller or another computer (e.g., a system server). Circuits for encoding and receiving data signals transmitted over power lines, such as within the power lines of a typical residence, are well known in the art and may be adapted for use in the PAMCC module. Alternatively, the PAMCC controller may be configured to adjust the amplitude modulations of individual pulses to add a secondary adaptive signal to the output power pulses.
By using power line communications PAMCC modules can communicate PV performance data (e.g., current conditions of their respective PV panels), current power output conditions (e.g., control voltages, output current, output power, etc.), synchronizing signals, phase offset settings of each module, system control signals (e.g., from a central controller), error messages, and other information that may facilitate operation of a PV power generation system. Further, multiple signals may be modulated onto the PAMCC output, such as to enable communication of information to two or more different destination devices (e.g., an arbitrary two or more PAMCC modules and a system monitor server) simultaneously.
In an embodiment the controller 2116 illustrated in
The various embodiments described herein may be useful for controlling any source of direct current and converting the direct current to three phase alternating current. Examples of direct current sources include solar panel, wind turbine, battery, geothermal, tidal, hydroelectric, thermoelectric and piezoelectric power systems. For the purpose of discussion, the example of a solar system embodiment is used as an example for describing the functioning and capabilities of the various embodiments. However, one skilled in the art would recognize that the circuits and processes described herein may be applied to other direct current sources as well. Accordingly, the scope of the claims should not be limited to solar power applications except as expressly recited in the claims.
The foregoing method descriptions and the process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the steps of the various aspects must be performed in the order presented. As will be appreciated by one of skill in the art the order of steps in the foregoing aspects may be performed in any order. Words such as “thereafter,” “then,” “next,” etc. are not intended to limit the order of the steps; these words are simply used to guide the reader through the description of the methods. Further, any reference to claim elements in the singular, for example, using the articles “a,” “an” or “the” is not to be construed as limiting the element to the singular.
The various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The hardware used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some steps or methods may be performed by circuitry that is specific to a given function.
In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The steps of a method or algorithm disclosed herein may be embodied in a processor-executable software module executed which may reside on a tangible non-transitory computer-readable medium or processor-readable medium. Non-transitory computer-readable and processor-readable media may be any available media that may be accessed by a computer or processor. By way of example, and not limitation, such non-transitory computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and/or instructions on a non-transitory processor-readable medium and/or computer-readable medium, which may be incorporated into a computer program product.
The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.
This application is a continuation in part of and claims priority to U.S. patent application Ser. No. 12/861,815 entitled “Three Phase Power Generation from a Plurality of Direct Current Sources” filed Aug. 23, 2010. This application also claims the benefit of priority to U.S. provisional Patent Application 61/432,973 entitled “Methods For Controlling A Photovoltaic Panel In A Three Phase Power Generation System” filed Jan. 14, 2011. The entire contents of both applications are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61432973 | Jan 2011 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12861815 | Aug 2010 | US |
| Child | 13277977 | US |
