"Timing Recovery in Digital Synchronous Data receivers", Kurt H. Mueller and Markus Muller, IEEE Transactions on Communications, vol. COM-24, No. 5, pp. 516-531 (May 1976). |
"Fast Timing Recovery for Partial-Response Signalling Systems", F. Dolivo, W. Schott and G. Ungerbock, IBM Research Division, Zurich Research Laboratory, pp. 0573-0577 (1989) IEEE. |
"Fully Integrated Analog Filters Using Bipolar-JFET Technology", Khen-Sang Tan and Paul R. Gray, IEEE Journal of Solid-State Circuits, vol. SC-13, No. 6, December 1978 (1978). |
"The Viterbi Algorithm", G. David Forney, Jr., Proceedings of the IEEE, vol. 61, No. 3, pp. 268-278 (1976). |
"Turbo-PRML: A Compromise EPRML Detector", Roger Wood, IEEE Transactions on Magnetics, vol. 29. No. 6, pp. 4018-4020 (Nov. 1993). |
"Implementation of a Digital Read/Write channel with EEPR4 Detection", Dave Welland et al., IEEE Transactions on Magnetics, vol. 31, No. 2 (Mar. 1995). |
"A High Speed, Low Power PRML Read Channel Device", Jeff Sonntag et al., IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1186-1195 (Mar. 1995). |
"Improving Performance of PRML/EPRML through Noise Prediction", Evangelos Eleftheriou et al., Presented at INTERMAG96 International Magnetics Conference, pp. 1-3 (1996). |
"An Experimental 180 Mb/sec PRML Channel for Magnetic Recording", John Hong et al., IEEE Transactions on Magnetics, vol. 27, No. 6, pp. 4532-4537 (Nov. 1991). |
"A 3.0 V 40 Mb/s hard Disk Drive Read Channel IC", Geert A. De Veirman et al., IEEE Journal of Solid-State of Circuits, vol. 30, No. 7, pp. 788-799 (Jul. 1995). |
"Exact Bounds for Viterbi Detector Path Metric Differences", Paul H. Seigel et al., pp. 1093-1096, (1991). |
"Analog Front-End Architectures for High-Speed PRML Magnetic Read Channels", Patrick K.D. Pai et al., IEEE Transactions on Magnetics, vol. 31, No. 2, (Mar. 1995). |
"Implementation of PRML in a Rigid Disk/Drive", J.D. Coker et al., IEEE Transactions on Magnetics, vol. 27, No. 6, pp. 4538-4543, (Nov. 1993). |
"A Class of Partial Response Systems for Increasing Storage Density in Magnetic Recording", H.K. Thapar et al., IEEE Transactions on Magnetics, vol., Mzag. 23, No. 5, pp. 3666-3668 (Sep. 1987). |
"Integrating a Partial Response Maximum Likelihood Data Channel into the IBM 0681 Disk Drive", J.C. Coker et al., Presented at the Twenty-Fourth Asilomar Conference on Signals, Systems & Computers, pp. 674-677, (1990). |
"A PRML System for Digital Magnetic Recording", Roy D. Cideciyan et al., IEEE Journal on Selected Areas in Communications, vol. 10, No. 1, pp. 38-56 (Jan. 1992). |
"A Survey of Digital Phase-Locked Loops", William C. Lindsey et al., Proceedings of the IEEE, vol. 69, No. 4, pp. 410-431 (Apr. 1981). |
"Design and Performance of a VLSI 120 Mb/s Trellis-Coded Partial Response Channel", J. W. Rae et al., IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1208-1214, (Mar. 1995). |
"Error Rate Performance of Experimental Gigabit Per Square Inch Recording Components", Thomas D. Howell et al., IEEE Transactions on Magnetics, vol. 26, No. 5, pp. 2298-2302 (Sep. 1990). |
"Parallelism in Analog and Digital PRML Magnetic Disk Read Channel Equalizers", Gregory T. Uehara and Paul R. Gray, IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1174-1179 (Mar. 1995). |
"PERD: Partial Error Response Detection", Takushi Nishiya et al., IEEE Transactions on Magnetics, vol. 31, No. 6, pp. 3042-3044 (Nov. 1995). |
"PRML: A Practical Approach", Alexander Taratorin, Guzik Technical Enterprises, pp. 1-93 (1995). |
"Realization of a 1-V Active Filter Using a Linearization Technique Employing Plurality of Emitter-Coupled Paris", Hiroshi Tanimoto et al., IEEE Solid-State Circuits, vol. SC-26, No. 7 pp. 937-945 (Jul. 1991). |
"HD153061TF 130-Mbps PRNL Data Channel Processor", Hitachi Advance Information, pp. 1-3, 29-34, (Jul. 1995). |
"A Digital Chip with Adaptive Equalizer for PRML Detection in Hard-Disk Drives", William L. Abbott et al., ISSC94, Session 17, Disk-Drive Electronics, Paper FA 17.5 pp. 284-285 (1984). |
"A 16MB/s PRML Read/Write Data Channel", Raymond A, Richetta et al., ISSCC95, Session 5, Disk and Arithmetic Signal Processor, Paper WP 5.1, pp. 78-79 and 58-59 (1995). |
"Reduced Complexity Viterbi Detector Architectures for Partial Response Signalling", Gerhard Fettweis et al., Paper presented at Globecom Conference '95, pp. 559-563 (1995). |
"Improving Performance of PRML/EPRML Through Noise Prediction", E. Eleftheriou and W. Hirt, IBM Research Division, (1996). |
"Reduced Complexity Viterbi Detector Architectures for Partial Response Signalling", Gerhard Fettweis et al., IBM Research Division, pp. 1-2,4,6,8,10,12,14,16,18,20,22,24,26,28,30 (1995). |