The field of the invention relates generally to power converters, and more specifically, to methods and systems of calibrating a resonant converter.
Current designs employing inductor-inductor-capacitor (LLC) resonant converter topologies on an output stage use an empirical approach to determine the required input voltage to accommodate all the tolerances in the circuit. For example, tolerances may include a +/−5% to 8% variation in resonant inductor value, and/or a +/−5% variation in capacitor value. This approach does not achieve high efficiency at all load conditions and all output voltages because the empirical approach uses worst case conditions. Known approaches use a look-up table or close-a-loop on the resonant frequency.
In one embodiment, a method of calibrating a resonant converter is provided. The method includes calculating input voltage mathematically as a function of at least one of an output voltage, a load current, and tolerances of components of the LLC converter and operating the LLC converter in an open loop mode at a nominal resonant frequency. The method also includes measuring output voltage of the LLC converter and comparing the measured output voltage to the calculated input voltage.
In another embodiment, an inductor-inductor-capacitor (LLC) resonant converter is provided. The converter includes an inverter, a resonant tank, and a controller coupled to the inverter and to the resonant tank. The controller is configured to calculate input voltage mathematically as a function of at least one of an output voltage, a load current, and tolerances of components of the LLC converter and operate the LLC converter in an open loop mode at a nominal resonant frequency. The controller is also configured to measure output voltage of the LLC converter and compare the measured output voltage to the calculated voltage.
In an exemplary embodiment, rectifier 106 includes a center-tapped transformer 120, a filter capacitor (CF) 122, a first rectifier diode (DP) 124 and a second rectifier diode (DN) 126. Rectifier 106 rectifies the AC waveform from resonant tank 104 into a DC output. Rectifier 106 may be either a half-bridge rectifier, a full-bridge rectifier, or any other type of rectifier that enables rectifier 106 to function as described herein. In low-output voltage, high-current applications, first and second rectifier diodes 124 and 126 are replaced with synchronized rectifiers (not shown) to reduce the voltage drop (conduction losses) across each semiconductor rectifier.
In an exemplary embodiment, LLC converter 100 also includes a controller 108 communicatively coupled to inverter 102, resonant tank 104, and/or rectifier 106. Controller 108 is configured to perform one or more operations of converter 100, as described in more detail herein. For example, controller 108 uses mathematics to calculate an optimal bus voltage as a function of output voltage, load current, input frequency, and/or tolerances in elements of LLC tank 104, namely resonant inductor 118 and resonant capacitor 116. This facilitates operation of each element at peak efficiency without degrading other performances, such as psophometric noise. The mathematics are given by:
Vbus=Vout×Nt×M+Iout×f×y±x (1)
‘Vout’ is an output voltage of LLC converter 100. ‘Nt’ is a turns ratio of transformer 120. ‘M’ is a multiplier, and applies a value of two for a half-bridge rectifier and a value of one for a full-bridge rectifier. ‘Iout’ is real-time output current of LLC converter 100. ‘f’ is the input frequency, ‘y’ is the coefficient representing ripple across a 400V bus, and ‘x’ is the calibration factor that can be obtained during testing.
In an exemplary embodiment, calibration is accomplished by operating LLC converter 100 in an open loop mode at a nominal resonant frequency. Operating LLC converter 100 in an open loop mode may also be accomplished by operating LLC converter 100 at a pre-defined load or at a pre-defined input voltage. During this test, output voltage Vo is measured and compared to the desired nominal value. If the measured output voltage Vo is lower than the expected value, it can be inferred that particular tank has lower resonant frequency and hence, the coefficient x will have a −ve sign and the magnitude is a function of the difference between measured versus expected value. Alternatively, if the measured voltage is higher than expected, it implies that the resonant frequency of that unit is higher than nominal and the coefficient x will have a +ve sign. The magnitude is a function of the difference between measured versus expected value.
The embodiments described herein provide a controller that implements a mathematical method of calculating optimal bus voltage as a function of output voltage, load current, input frequency, and tolerances in LLC tank elements, namely a resonant inductor and a resonant capacitor. The embodiments enable each element to operate at peak efficiency without degrading other performances like psophometric noise. Moreover, the embodiments provide a procedure to obtain a coefficient for compensating tolerances in an LLC resonant converter without measuring tank frequency.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
As used herein, the term controller may refer to an electronic controller, which may include a computer processor or processing device (not shown). The processor is generally any piece of hardware that is capable of processing information such as, for example, data, computer-readable program code, instructions or the like (generally “computer programs,” e.g., software, firmware, etc.), and/or other suitable electronic information. For example, the processor may be configured to execute computer programs or commands, which may be stored onboard the processor or otherwise stored in an associated memory (not shown). In yet another example, the processor may be embodied as or otherwise include one or more application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or the like. Thus, although the processor may be capable of executing a computer program to perform one or more functions, the processor of various examples may be capable of performing one or more functions without the aid of a computer program. As used herein, electronic or computer memory is generally any piece of hardware that is capable of storing information such as data, computer programs and/or other suitable information either on a temporary basis or a permanent basis. In one example, the memory may be configured to store various information in one or more databases. The memory may include volatile and/or non-volatile memory, and may be fixed or removable. Examples of suitable memory include random access memory (RAM), read-only memory (ROM), a hard drive, a flash memory, a thumb drive, a removable computer diskette, an optical disk, a magnetic tape or some combination of the above. Optical disks may include compact disk read-only-memory (CD-ROM), compact disk read/write memory (CD-R/W), digital video disk memory (DVD), or the like. In various instances, the memory may be referred to as a computer-readable storage medium which, as a non-transitory device capable of storing information, may be distinguishable from computer-readable transmission media such as electronic transitory signals capable of carrying information from one location to another. Computer-readable media, as described herein, may generally refer to a computer-readable storage medium or computer-readable transmission medium.
This application claims the benefit of U.S. Provisional Patent Application No. 61/793,763 filed Mar. 15, 2013, which is hereby incorporated by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
5570276 | Cuk et al. | Oct 1996 | A |
5900701 | Guhilot | May 1999 | A |
6437994 | Blom et al. | Aug 2002 | B1 |
8018740 | Sun | Sep 2011 | B2 |
8094466 | Duerbaum et al. | Jan 2012 | B2 |
8259477 | Jin et al. | Sep 2012 | B2 |
20040095164 | Kernahan et al. | May 2004 | A1 |
20060239046 | Zane | Oct 2006 | A1 |
20080298093 | Jin | Dec 2008 | A1 |
20090097280 | Wu | Apr 2009 | A1 |
20090244934 | Wang | Oct 2009 | A1 |
20090303753 | Fu | Dec 2009 | A1 |
20090306914 | Cohen | Dec 2009 | A1 |
20090323380 | Harrison | Dec 2009 | A1 |
20100328969 | Meyer | Dec 2010 | A1 |
20110002145 | Halberstadt | Jan 2011 | A1 |
20110103097 | Wang | May 2011 | A1 |
20120163039 | Halberstadt | Jun 2012 | A1 |
20120275197 | Yan | Nov 2012 | A1 |
Number | Date | Country |
---|---|---|
03055052 | Jul 2003 | WO |
WO2011102910 | Aug 2011 | WO |
Entry |
---|
J. Duncan Glover, Mulukutla S. Sarma, Thomas J. Oberbye, Power System Analysis and Design, 4th Ed. 2008, Thompson Learning Inc. p. 96-99. |
“Sliding Mode Design of Distributed Central Limit Control Strategy for Parallel-Connected Inverters” Ramos et al. IEEE, 2002. |
Lee, “Auxiliary Switch Control of Bidirectional Soft-Switching DC/DC Converter”, IEEE Transactions on Power Electronics, vol. 28, No. 12, Dec. 2013, pp. 5446-5457. |
Number | Date | Country | |
---|---|---|---|
20140268904 A1 | Sep 2014 | US |
Number | Date | Country | |
---|---|---|---|
61793763 | Mar 2013 | US |