METHODS AND SYSTEMS FOR CAPTURING AND REPRESENTING VIDEO IN CONTINUOUS TIME

Abstract

The present invention encompasses methods and systems of representing video in continuous time. Photons incident on pixels in an imaging array are continuously captured using a continuous time imaging sensor array to produce respective continuous time analog signals without any discontinuity in time. At each pixel, the respective continuous time analog signal is modulated into respective continuous time binary analog signals. The continuous time binary analog signals from all pixels are aggregated to produce a frame free video. Each pixel may comprise a continuous time sigma delta modulator and a photodiode having a capacitance. At each pixel, the respective continuous time analog signal is modulated using the continuous time sigma delta modulator to produce the corresponding continuous time binary analog signal. The capacitance of the photodiode functions as a charge integrator. The photodiode may be biased at or near zero volts in order to reduce dark current noise.

Description

BACKGROUND OF THE INVENTION

The present invention relates to the field of video capture and display. More specifically, the present invention relates to methods and systems for capturing and representing video in continuous time (also referred to herein as “frame free video”).

Traditional video is frame-based video. Such frame-based video, including film-based movies, presents one frame of still picture after another in rapid succession, which produces the illusion of motion when the frame update rate is fast enough. Each “frame” is a complete static greyscale picture, which is readily apparent when the video or film is paused on one of the frames.

Eadweard Muybridge is credited with the first capture of motion on film in 1872 using an array of 12 cameras, as shown in FIG. 1. Modern video cameras still use the same basic principle discovered by Eadweard Muybridge in 1872. “Frame Rate” is one of the most prominent parameters in video. The higher the frame rate, the smoother the motion. Currently a frame rate of around 60 fps (frames per second) is used on most cameras. Typically, there is some information lost between the frames, due to shutter opening and closing, resulting in aliasing errors.

FIG. 2 shows an example embodiment of a prior art frame-based video process. In frame-based video, each frame of film or video is exposed when the shutter is open. In FIG. 2, the imaging sensor array 10 is comprised of pixels. The signal x(t) represents the incident photon flux (or photo current) at each pixel in the imaging array 10. An integrator 12 integrates x(t) integrated over T_O, the shutter open duration, to produce the signal y(t). The signal y(t) is sampled at the end of integration by a sample and hold amplifier S/H, reset (by discarding the incident photon) during T_R, the shutter closed duration, to produce the analog signal y_s(t). During T_R, a new piece of film is positioned, or the photodiode is reset. The sample and hold amplifier S/H samples y(t) at down arrows to produce y_s(t). The signal y_s(t) is quantized and digitized by an analog to digital converter 14 to produce a digital signal z(n), which represents peak y(t) sampled and converted to a PCM (pulse code modulation) coded signal, representing one of the pixels in a 2-D image frame, at frame time n (t=nT_S). The digital signal z(n) can then be communicated over a transmission channel and converted at the destination back to an analog signal y′_s(t) at a digital to analog converter 16. The signal y′_s(t) is an approximation of the signal y_s(t), and comprises the signal y_s(t) plus quantization error. The display signal y′(t) at the display array 18 approximates the signal y_s(t) and comprises a greyscale display output of the average brightness over one frame time. The signal y′(t) reproduces y_s(t), which may have a different time profile than the shutter at the imaging sensor. The signal y′(t) is an approximation of x(t) except for the time aliasing due to the shutter time profile, finite integration window, and missing photons. This aliasing error cannot be separated out by any filtering. The bandwidth of y′(t) depends on the frame rate (1/T_S). The human visual system (HVS) has a response up to 60 Hz, requiring a frame rate greater than 120 Hz. However, when there is object motion or quick camera panning the temporal bandwidth of the scene often exceeds 60 Hz, therefore even 120 Hz is not sufficient. In those situations, the viewer sees multiple trailing edges or occasionally a stagecoach wheel turning backward.

It would be advantageous to overcome the inherent limitations of frame-based video and to enable video recording and playback in a manner more consistent with the human visual system. The methods, apparatus and systems of the present invention provide the foregoing and other advantages by providing methods and systems for capturing and representing video in continuous time. Methods and systems are provided for producing a frame free video stream without any frame boundaries.

SUMMARY OF THE INVENTION

The present invention relates to methods and systems for capturing and representing video in continuous time (also referred to herein as “frame free video”).

An example embodiment of a method for representing video in continuous time in accordance with the present invention comprises continuously capturing photons incident on pixels in an imaging array using a continuous time imaging sensor array to produce respective continuous time analog signals without any discontinuity in time. At each pixel, the respective continuous time analog signal is modulated into a respective continuous time binary analog signal. The continuous time binary analog signals from all pixels can then be aggregated to produce a frame free video.

Each pixel comprises a continuous time sigma delta modulator and a photodiode having a capacitance. At each pixel, the respective continuous time analog signal is modulated using the continuous time sigma delta modulator to produce the respective continuous time binary analog signal.

The capacitance of the photodiode may function as a charge integrator. The photodiode may be biased at or near zero volts in order to reduce dark current noise.

At each pixel, the continuous time binary analog signal may be mapped to a discrete time binary digital signal consisting of 1's and 0's. The discrete time binary digital signals from all of the pixels in the imaging array may be aggregated to produce a corresponding binary bit-plane per each clock cycle of the sigma delta modulator to convert the frame free video to a frame free video stream. The frame free video stream may comprise a time series of the binary bit-planes.

The photodiode is not reset throughout the operation of the imaging array. The charge integrator may maintain a voltage range of the photodiode corresponding to a sum of a photo-current of the photodiode and a negative of a feedback current of the sigma delta modulator, in order to maintain the voltage across the photodiode close to a voltage where a photodiode dark current is minimal.

The method may further comprise integrating the photo-current of the photodiode continuously in time without saturating the photodiode by the charge integrator to produce an integrated value which represents total photons converted to electrical charges. Each time the integrated value exceeds a reference value, a fixed value may be subtracted from the integrated value to enable the charge integrator to operate within a narrow operating range with less than one volt deviation. A series of the subtracted fixed values over time may result in an estimate of the total integrated value, enabling the sigma delta modulator to produce the continuous time binary analog signal.

The charge integrator comprises at least one of the capacitance of the photodiode and a capacitor in parallel with the photodiode and coupled to an output of the photodiode.

The sigma delta modulator may comprise: a slicer coupled to the output of the charge integrator for determining whether the integrated value from the charge integrator output exceeds the reference value, the slicer output comprising the discrete time binary digital signals; and a charge digital to analog converter (qDAC) coupled to an output of the slicer and to the charge integrator, which produces the fixed value to be subtracted each time the integrated value exceeds the reference value, enabling the charge integrator to operate within an operating range which is substantially smaller than a power supply voltage of the pixel.

When the photodiode operates in a photovoltaic mode, the photo-current is used to power the qDAC. When operating in the photovoltaic mode, accumulated photocurrent is drained to ground or to a lower potential node through the qDAC.

When the charge integrator is biased near zero volts, a qDAC bias voltage may be applied to the qDAC, enabling the qDAC to generate a programmable amount of a qDAC current which is applied to the photodiode in order to maintain the photodiode voltage near zero volts. In addition, a slicer bias voltage may be applied to the slicer which sets a voltage threshold. In such an embodiment, the slicer compares the photodiode voltage with the slicer bias voltage to determine whether a fixed amount of charge is added to the photodiode by the qDAC current in order to maintain a desired voltage across the photodiode.

The qDAC current may be adjusted based on output from the slicer. For example, one of ones or zeroes output from the slicer may be counted to determine the qDAC bias voltage. Alternatively, a ratio of ones and zeroes output from the slicer over time may be calculated to determine the qDAC bias voltage.

The qDAC gain may also be controlled by one of duty cycle modulation of the qDAC current, voltage modulation of a qDAC bias voltage source, and averaging of the qDAC bias voltage over time.

The method may further comprise applying at least one of an offset and a scale factor to confine a black level and a white level of the frame free video between a minimum and a maximum of an output of the sigma delta modulator. A predefined offset may be applied to a black level of the frame free video. Any predefined offset may be used, for example 1/16 of a full level range. The predefined offset may be achieved by applying a small black level offset current to the charge integrator that drains the integrated charge and simulates a small photocurrent. The amount of the black level offset current may be programmable.

An average qDAC current applied to the charge integrator may be equivalent to the black level offset current when there is no photo-current due to lack of incident photons.

The predefined offset may be achieved by remodulating the continuous time binary analog signals from the sigma delta modulator in the digital domain using a discrete time sigma delta modulator.

The predefined offset may be removed for signal manipulation, including the signal display. The same offset or a different offset may be added back for subsequent processing of the signal.

A white level of the frame free video may be controlled via qDAC feedback gain.

The sigma delta modulator may further comprise a storage capacitor at the output of the slicer. The storage capacitor may be charged after each slicer decision. A row select switch may share the charge with a column capacitance connected to column readout circuitry of the imaging array. A further slicer senses a voltage change due to the charge on the column capacitance and makes a binary decision, where the binary decision output over time comprises a discrete time binary digital signal.

The column capacitance may be reset to a pre-determined voltage after each slicer decision.

The storage capacitor may enable a global shutter mode.

The method may further comprise processing the frame free video to provide multiple frame-based video streams at different resolutions and frame rates.

The present invention also encompasses a system for representing video in continuous time. Such a system may comprise a continuous time imaging sensor array for continuously capturing photons incident on pixels of the imaging array to produce respective continuous time analog signals without any discontinuity in time. Each of the pixels may comprise a photodiode and a sigma delta modulator circuit for modulating the respective continuous time analog signal into a respective continuous time binary analog signal. A processor may be provided for aggregating the continuous time binary analog signals from all the pixels to produce a frame free video stream. A continuous time display array may be provided for displaying the frame free video stream. In such a system, the photodiode may have a capacitance, and the capacitance of the photodiode may function as a charge integrator. The photodiode may be biased at or near zero volts in order to reduce dark current noise. The modulator circuit may comprise a continuous time sigma delta modulator.

The present invention may also encompass a pixel for a continuous time imaging sensor array. The array may be made up of a plurality of pixels, each of which may comprise a photodiode for capturing incident photons to produce a continuous time analog signal without any discontinuity in time and a sigma delta modulator circuit for modulating the continuous time analog signal into a continuous time binary analog signal. The photodiode may have a capacitance and the capacitance of the photodiode may function as a charge integrator. The photodiode may be biased at or near zero volts in order to reduce dark current noise. The continuous time binary analog signals from all pixels in an imaging sensor array may be aggregated to produce a frame free video stream.

Various embodiments of the system and pixel of the present invention may also encompass the features and functionality of the method embodiments discussed above.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction with the appended drawing figures, wherein like reference numerals denote like elements, and:

FIG. 1 shows a prior art image of the first motion capture on film;

FIG. 2 shows an example of a prior art frame-based video process;

FIG. 3 shows an example embodiment of a high-level frame free video process in accordance with the present invention;

FIG. 4 shows a further example embodiment of a frame-free video process in accordance with the present invention;

FIG. 5 shows an example embodiment of basic first order continuous time sigma delta modulator in accordance with the present invention;

FIG. 6 shows an example embodiment of a high-level pixel design in accordance with the present invention;

FIG. 7 shows a further example embodiment of a pixel design in accordance with the present invention where the charge integration is accomplished by an inverting op-amp integrator;

FIG. 8a shows a further example embodiment of a pixel design in accordance with the present invention where the charge integration is accomplished by the capacitance of the photodiode;

FIG. 8b shows a further example embodiment of a pixel design in accordance with the present invention where the charge integration is accomplished by a capacitor in parallel with the photodiode;

FIGS. 9-11 show example plots of operation of a single frame free video pixel in accordance with the present invention;

FIG. 12 shows an example of output from a prior art conventional pixel;

FIG. 13 shows an example of a prior art second order continuous time sigma delta modulator which may be used in an example embodiment of the present invention;

FIG. 14 shows an example embodiment of a frame free video system in accordance with the present invention;

FIG. 15 shows a further example embodiment of a pixel design in accordance with the present invention where the photodiode is biased at or near zero volts;

FIG. 16 shows a further example embodiment of a pixel design in accordance with the present invention with the photodiode operating in a photovoltaic mode;

FIG. 17 shows a further example embodiment of a pixel design in accordance with the present invention with a black level offset;

FIG. 18 shows an example embodiment of a discrete time sigma delta modulator in accordance with the present invention adapted to apply a black level offset to the output of the pixel; and

FIG. 19 shows a further example embodiment of a pixel design in accordance with the present invention which provides a low voltage readout of the pixel.

DETAILED DESCRIPTION

The ensuing detailed description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the ensuing detailed description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an embodiment of the invention. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention as set forth in the appended claims.

The present invention relates to methods, apparatus, and systems for representing video in continuous time, also referred to herein as “frame-free video”. Frame-free video refers to the fact that the video is captured without using traditional “frames” but rather as a continuous time representation, without any frame breaks.

Frame free video results in the capture and display of motion without the traditional frame breaks of frame-based video. The inventive process is based on the principal that frame rate is not fundamental in capturing motion, as the human eye does not have a frame rate. High temporal bandwidth is desirable, however.

Thus, frame free video is based on capturing video where the concept of frame rate is not used. Instead, video is captured in continuous time without any frame boundary. Sampling and digitization operations are performed, but these do not result in a traditional “frame”. However, many samples (e.g., bit-planes) can be aggregated to reproduce a traditional frame if desired, in which case the frame boundary can be arbitrarily defined to suit the needs of the intended application. The continuous time video may be modulated into an oversampled signal representation using sigma delta modulation (SDM). The corresponding display can also use sigma delta modulation to reproduce the original video. Integration (LPF) that happens in the eye reproduces the complete scene.

Frame free video provides many advantages over frame-based video. Such advantages include:

• • More accurate representation of the real world
    • No aliasing error
    • No loss of photons, no missing information
    • Signal captured is continuous, analytic, differentiable, virtually analog
    • Closest to how human eye works
    • Improved realism
    • Potentially easier to compress
    • Suitable for computer vision analysis
  • Improved camera capability
    • In-pixel A/D conversion, producing digital readout and less circuit noise
    • HDR, High Dynamic Range (potentially 1 to 2 orders of magnitude improvement)
    • Adaptive exposure time for still images, possibly motion adaptive
    • Signal to Noise Ratio (SNR) very high at slow motion, moderate at fast motion
      • Eye tracking of fast-moving objects results in high SNR
      • Avoids multiple trailing edges when eye tracks a moving object
  • Transcoding for backward compatibility
    • Easy conversion to and from frame based PCM video
    • Motion adaptive denoising, blur control possible
  • All digital display possible using SDM, that maps exactly what the camera produced
  • Low delay from camera to display, for low latency applications
    • RPV, drones, autonomous driving, computer games, anything involving fast reaction time

The frame free video camera sensor array may be a retrofit to an existing CMOS sensor array(e.g., with some circuit changes). The frame free video display array may be implemented with existing display technologies that offer fast binary modulation of pixels.

Frame free video may be implemented as an end-to-end system, starting with continuous photon capture, all the way to a native frame free video display system. Frame-based video requires integration in the human eye to see continuous motion. Frame Free Video causes integration in the eye as well, but requires less effort and produces less artifacts. In the frame free video process, a 1-bit oversampled representation of photon flux on each pixel is produced. If needed, the signal can be re-modulated after gamma correction, color processing, etc. or to higher order SDM. Second or third order SDM at the pixel level is also possible with more transistors. Charge mode sensing of the photodiode, direct modulation into SDM without conversion to voltage can all be implemented. Charge mode feedback to the photodiode that avoids diode reset is used to keep the photodiode constantly biased and to avoid a gap between samples. This also reduces chances of non-linearity and photodiode saturation, and leads to high dynamic range. The system advantageously produces an all digital readout of pixel values, without the need for an analog sense amplifier for the imaging array, resulting in less noise.

In many cases, there is no shutter needed at the sensor level. A shutter introduces unwanted time aliasing, unless a specific visual effect is desired. The system may include electronic gain control by way of changing the feedback gain in the SDM loop, e.g., for low light situations. A continuous time SDM typically incorporates an op-amp circuit to implement an integrator. This op-amp supply current may be increased for high photon flux. Alternatively, the op-Amp bias current may be modulated on and off with an adaptable duty cycle to save power consumption. For example, a lower on/off frequency or shorter “on” duty cycle may be used when the photon flux is low. SDM modulation rate may be dynamically adjusted to avoid saturation and to increase dynamic range and SNR. SDM modulation rate can also be changed to adapt to different motion bandwidth needs. Mechanical or electronic iris (or dimming) may be employed for intense lighting conditions. For extremely intense lighting conditions, the op-amp integrator input can be reconfigured to integrate only a portion of the photodiode current during each SDM clock cycle.

With the present invention, manipulation is possible in the SDM bit-stream domain. For example: temporal filtering (time domain blur or sharpening) and re-modulation back to SDM; motion axis filtering (in the direction of motion) and remodulation back to SDM; color space conversion, matrixing, and remodulation back to SDM; gamma correction and remodulation back to SDM; video gain and offset control, and remodulation back to SDM, and the like.

In some cases, the continuous time video may be represented by a series of SDM binary bit-planes without any frame boundary, which can be displayed directly by a display that displays SDM binary bit-planes. In some cases, all photons are captured without any discontinuity. In such cases, the photodiode is never reset, and the diode voltage is kept constant.

In an ideal conceptualization of the present invention, as shown in FIG. 3, a continuous time imaging sensor array 20 is used to map, continuously in time for each pixel, the pixel value x(t) (photons incident on the pixel) directly to a continuous time display pixel value x′(t) for display at a continuous time display array 40. However, many factors reduce the bandwidth of x(t), including the sensor response speed of the imaging sensor array 20, the communications channel bandwidth, and the display pixel response at the display array 40. Also, accurately transferring all the analog pixel values from the sensor array to the display array is very difficult through a single communications channel. Temporarily and permanently storing the analog pixel values is difficult as well without some form of digitization. Thus, such an implementation is conceptually possible but not practical.

FIG. 4 shows a more practical embodiment of the present invention. In the FIG. 4 example embodiment, a continuous time sigma delta modulator (SDM) 22 is employed between the imaging sensor array 20 and the display array 40. In the FIG. 4 embodiment, the output x(t) for each pixel of the sensor array 20 is a continuous time analog signal. The continuous time analog signal x(t) is modulated by the continuous time SDM at high clock rate to produce y(t), which is a continuous time binary analog signal. Y(t) can be digitized into a discrete time binary digital signal z(n) for transmission and storage. The signal y(t) contains x(t), with additive noise that can be filtered out by a low pass filter (LPF). The display array 40 reproduces y′(t), an approximation of y(t). The human visual system (HVS) filters out the noise in y(t), and sees a close approximation of x(t). The LPF operation becomes easier as the SDM clock rate is increased.

FIG. 5 shows an example embodiment of a basic first order continuous time sigma delta modulator 22 in accordance with the present invention, which comprises an integrator 42 and a slicer 44, that can be employed in the system of FIG. 4. The photodiode signal x(t) is integrated continuously in time by the integrator 42. The resultant signal is then fed into a slicer 44, which outputs the continuous time binary analog signal y(t), which can then be digitized to produce the discrete time binary digital signal z(n). A feedback loop is provided between the output of the slicer 44 and the input of the integrator 42 such that the integrator 42 operates only on the difference signal produced by the delta operation (e.g., performed by a differential amplifier circuit). This completes the SDM loop that keeps the integrator stable, and produces y(t) representing the continuous time binary analog signal that closely approximates the photodiode signal x(t).

FIG. 6 shows an example embodiment of an individual pixel circuit of a sensor array 20 which comprises a high-level SDM design in accordance with the present invention. The pixel circuit of FIG. 6 includes the photodiode 43 which outputs the signal x(t) into a delta operation 41. In this example embodiment, the feedback loop now includes a charge DAC (digital to analog converter) which produces the signal y(t) from the output of the slicer 44 for subtraction from the input signal x(t). In this embodiment, x(t) and y(t) are represented in current, not voltage.

The slicer 44 comprises a dynamic comparator that compares two analog values and makes a decision at a given time instance, usually defined by a clock signal S_CLK. In the present invention, the clock signal indicates the bit-plane time.

It is important to note that the photodiode is not reset and the integrator 42 is not reset either. It is possible to view that the integrator output is A/D converted using a 1-bit A/D converter, which is the slicer 44 (threshold to high or low binary decision). In that case, the quantization error is rather large. The advantage of the SDM loop is that the quantization error is fed-back to the integrator 42, which gets combined with the next input value. This error value in each cycle gets integrated over time, and averages out so that a very high SNR can be achieved. In contrast, in frame-based systems, the quantization error in one cycle (frame time) gets lost, due to the reset process, and the SNR is limited by the resolution of the A/D converter, typically 8-bits.

It should also be appreciated that a traditional implementation of an SDM is in voltage. However, with the present invention, the SDM circuit is either charge or current based (which are interchangeable in a real implementation). Signal y(t) is shown as a plot of current output. Current integrated over a period of time is charge.

FIG. 7 shows a further example embodiment of a pixel circuit with a more detailed SDM design than that of FIG. 6, in accordance with the present invention. In FIG. 7, the SDM comprises a 1-bit continuous time sigma delta modulator in the charge domain, which employs an inverting op-amp charge integrator circuit.

It should be appreciated that in various embodiments of the present invention, the sigma delta modulator comprises a feedback-based charge integrator that is connected to the photodiode. The photodiode is not reset throughout the operation of the imaging array. Continuous feedback from the feedback-based charge integrator maintains a constant photodiode voltage.

The photodiode current x(t) is integrated continuously in time without saturating the photodiode 43 by the feedback-based charge integrator to produce an integrated value which represents total photons converted to electrical charges. Each time the integrated value exceeds a reference value, a fixed value is subtracted from the integrated value to bring the integrator output to below the reference value. The series of subtracted values over time results in a close approximation of the total integrated value, enabling the sigma delta modulator to produce the continuous time binary analog signal y(t) that can be mapped to the discrete time binary digital signal z(n).

As shown in FIG. 7, the sigma delta modulator further comprises an op-amp 48 with a non-inverting input held at a constant voltage and an inverting input coupled to an output of the photodiode 43. The op-amp 48 outputs the integrated value. A feedback capacitor C₁ is coupled to an output of the op-amp 48 and the output of the photodiode 43 to maintain the constant photodiode voltage. The slicer 44 is coupled to the output of the op-amp 48 for determining whether the integrated value from the op-amp 48 output exceeds the reference value. The slicer output comprises the discrete time binary digital signals z(n). A charge digital to analog converter (qDAC) 46 is coupled to an output of the slicer 44 and the inverting input of the op-amp 48 which produces the fixed value to be subtracted.

It should be noted that the slicer output can often be considered an analog signal y(t). However, in a practical implementation, it is easier to obtain the digital signal z(n) from the slicer, and then insert a D/A converter (charge DAC 46 in FIG. 7) in the feedback loop to generate y(t).

With the present invention, the signal y(t) is a continuous time binary analog signal produced by the slicer 44 and the qDAC 46, and z(n) is the discrete time binary digital signal produced by the slicer 44. In certain implementations, sometimes the slicer can generate y(t) directly if it produces the right two voltage levels, but with the present invention, since charge injection is needed, it is advantageous for the slicer to output the digital signal z(n) and employ a charge DAC to generate y(t).

The photodiode 43 is reverse biased at V_D1 (indirectly by the op-amp voltage V_DB). As the photodiode 43 receives photons, the photo electric current x(t) is generated. This in turn discharges the built-in capacitance of this reverse biased diode 43. Diode voltage V_D1, which is connected to the negative input of the Op-Amp 48, would drop. The feedback from the Op-Amp 48 charges up the capacitor C₁ to keep its negative input V_D1 constant at V_DB. This results in the photo electric current being transferred to the integrator capacitor C₁. The end result is that the photo electric current x(t) from the diode is continuously accumulated in C₁ while keeping the diode voltage V_D1 held constant at V_DB. This forms the “charge domain integrator” part of the SDM circuit.

The feedback capacitor C₁ accumulates the charge for the charge-based SDM. Voltage on the capacitor is the total charge divided by its capacitance. In order to maintain a fixed voltage on the photodiode 43, the output voltage of the op-amp 48 changes by this capacitor voltage.

Assuming the Op-Amp 48 has a high gain, the diode bias voltage V_DB applied to the positive input of the Op-Amp 48 will keep the negative input of the Op-Amp also at V_DB. The voltage output of the Op-Amp 48 is proportional to the total charge accumulated into C₁. Once the integrator output (Op-Amp output) exceeds a threshold set by V_SB, the Slicer 44 makes a one-bit decision and outputs z(n)=1. The qDAC 46 produces y(t), a fixed amount of charge that gets subtracted from the integrator. This discharges C₁ without changing the diode voltage, due to the Op-Amp feedback. When the Slicer decision z(n)=0, no charge is subtracted from the integrator. This outer feedback (SDM feedback) keeps the integrator output stable, within the set voltage range centered around V_SB. This Slicer decision z(n) is also the output of the FFV pixel at that time instance (SDM clock). Each 1-bit decision z(n) from an array of pixels in an image sensor form the “SDM bit-plane”, for an L×M array. The frame free video stream is comprised of a series of these SDM bit-planes in time, with L×M binary values per bit-plane.

It should be noted that there are a number of alternative ways to connect the photodiode to the inverting op-amp charge integrator in FIG. 6. One alternative would be to connect the anode of the photodiode to the inverting input of the op-amp and connect the cathode of the photodiode to another voltage. Another alternative would be to connect the anode of the photodiode to another voltage instead of the ground. Yet another alternative would be to connect the anode of the photodiode to the non-inverting input of the op-amp. They all lead to the continuous integration of the photo current from the photodiode but may provide different design optimizations, including linearity and dark current.

Because the photon has been integrated continuously without a gap in time, the frame free video is an analog representation of the photon flux at each pixel. It should be noted that the representation is a continuous time analog representation but has a large amount of noise introduced, where noise is mitigated by oversampling.

The over sampling ratio (OSR) determines the quality of the signal. A useable range is typically between 8× to 128× for video. For a 60 Hz(FPS) conventional video, the highest motion bandwidth allowed is 30 Hz. At 16× OSR, frame free video will have 960 Hz bit-plane rate (SDM clock rate), which allows a motion bandwidth up to 480 Hz.

The integrator in the frame free video pixel is a low-pass filter in the continuous time domain. It avoids aliasing that is present in conventional frame-based video. The Human Visual System (HVS) has a bandwidth that peaks around 20 Hz, and drops off to zero around 60 Hz. HVS (naked eye) will provide sufficient temporal filtering to see the original video content from the FFV stream, but not the noise.

FIGS. 8a and 8b show further example embodiments of a pixel circuit with a simplified SDM design as compared to that of FIG. 7, in accordance with the present invention. In FIG. 8a, the SDM comprises a 1-bit continuous time sigma delta modulator in the charge domain as in FIG. 7, but without the op-amp charge integrator circuit and the feedback capacitor of the FIG. 7 design. In FIG. 8a, the capacitance of the photodiode 43 functions as the charge integrator. In FIG. 8b, the op-amp charge integrator circuit and the feedback capacitor are replaced by a simple capacitor C₁ in parallel with the photodiode 43, with the photodiode capacitance and the capacitor functioning as the charge integrator 42.

The embodiments shown in FIGS. 8a and 8b provide a more sensitive slicer circuit with a higher SDM (qDAC) update rate, which keeps V_D1 close to V_SB with the slicer 44 biased at V_SB.

As in the FIG. 7 embodiment discussed above, the signal x(t) is the current flowing into the reverse biased photodiode 43 when the diode 43 is exposed to light. The signal y(t) is a continuous time binary analog signal produced by the slicer 44 and the qDAC 46, and z(n) is the discrete time binary digital signal produced by the slicer 44. The output of the photodiode in FIG. 8a (or the combined output of the photodiode and capacitor C1 in FIG. 8b) is non-inverting and so is connected to the negative input of the slicer 44 (whereas the op-amp 48 of the FIG. 7 embodiment is inverting and so is connected to the positive input of the slicer 44). Signals z(n) and y(t) (output of qDAC 46) add charge (positive current) to the integrator 42 (e.g., the photodiode with or without the capacitor C₁) in a manner to compensate for the charge (current) taken out of the integrator by the photo diode. If the integrator 42 is too low, it adds a fixed amount of charge. If the integrator is high, it skips the cycle and waits for the photo diode to bring it low. This feedback keeps the integrator stable, by keeping it within a narrow range.

The design of FIGS. 8a and 8b can be implemented with fewer transistors and reduced power consumption as compared to the design of FIG. 7. Replacing the op-amp with the diode capacitance and/or one or more capacitors eliminates power otherwise consumed by the op-amp. The slicer 44 can be implemented such that current is only used when switching or making a decision. The charge DAC (qDAC) 46 can be duty cycled to reduce power consumption, especially for low light conditions (low photo current), but still has to cancel out the total photo current to keep the SDM feedback loop working. It is also possible to clamp the photodiode 43 (duty cycled) by additional transistors such that part of the photo current gets dumped. Doing so may reduce the current consumption in extremely high illumination conditions.

In an example embodiment of a method of representing video in continuous time in accordance with the present invention which uses the pixel circuit shown in FIG. 8a, the method may comprise continuously capturing photons incident on pixels in an imaging array using a continuous time imaging sensor array 20 (see FIG. 14) to produce respective continuous time analog signals x(t) without any discontinuity in time. At each pixel, the respective continuous time analog signal x(t) is modulated into a respective continuous time binary analog signal y(t). The continuous time binary analog signals y(t) from all pixels are aggregated to produce a frame free video. Each pixel may comprise a continuous time sigma delta modulator 22 and a photodiode 43 having a capacitance. At each pixel, the respective continuous time analog signal x(t) is modulated using the continuous time sigma delta modulator 22 to produce the respective continuous time binary analog signal y(t). The capacitance of the photodiode 43 functions as a charge integrator 42.

The sigma delta modulator 22 may be one of charge-based or current-based.

At each pixel, the continuous time binary analog signal y(t) may be mapped to a discrete time binary digital signal z(n) consisting of 1's and 0's. The discrete time binary digital signals z(n) from all of the pixels may be aggregated in the imaging array to produce a corresponding binary bit-plane per each clock cycle of the sigma delta modulator to convert the frame free video to a frame free video stream. The frame free video stream may comprise a time series of the binary bit-planes (as discussed in detail below in connection with FIG. 14).

The frame free video stream may be converted into a frame free video signal by at least one of manipulating, format converting, encoding, transcoding, compressing, storing, transmitting, and otherwise representing the frame free video stream.

The binary 1's and 0's from the discrete time binary digital signal may be mapped to a maximum value and a minimum value, respectively, to enable continuous time video processing or display.

The photodiode 43 is not reset throughout the operation of the imaging array. The charge integrator 42 maintains a voltage range of the photodiode 43 corresponding to a sum of a current of the photodiode 43 and a negative of a feedback current of the sigma delta modulator 22. The voltage of the photodiode 43 voltage is proportional to the total charge, V=Q/C, but the capacitance of the photodiode can be voltage dependent.

The current of the photodiode is integrated continuously in time without saturating the photodiode by the charge integrator 42 to produce an integrated value which represents total photons converted to electrical charges. Each time the integrated value exceeds a reference value, a fixed value is subtracted from the integrated value to enable the charge integrator 42 to operate within an operating range. The series of subtracted values over time may result in a close approximation of the total integrated value, enabling the sigma delta modulator 22 to produce the continuous time binary analog signal y(t).

Those skilled in the art will appreciate that the subtracting of the fixed value from the integrated value may actually encompass “adding” of the fixed value, depending on the sign of the integrated quantity. If the photo current is subtracting from the charge integrator 42, we subtract a negative feedback value which is the same as adding to the charge integrator 42. A typical SDM modulator assumes the input signal is adding to the integrator and the feedback signal subtracts from the integrator. In practice, the photo current does “add” electrons to the capacitor integrator and the feedback qDAC “subtracts” electrons, which are negatively charged.

In an example embodiment as shown in FIG. 8b, the charge integrator 42 may comprise the capacitance of the photodiode 43 and a capacitor C₁ in parallel with the photodiode 43 and coupled to an output of the photodiode 43. Alternatively, the charge integrator 42 may comprise the capacitance of the photodiode 43 and one or more capacitors C₁ in parallel with the photodiode 43 and coupled to an output of the photodiode 43.

The optional capacitor C₁ would increase the total capacitance of the charge integrator 42, when the capacitance of the photodiode alone is not sufficient. With the added capacitor, the integrator 42 will be able to store more charges, which therefore increases the dynamic range (which can be useful when the scene is very bright—i.e., more incident photons).

The sigma delta modulator May 22 comprise: a slicer 44 coupled to the output of the charge integrator 42 for determining whether the integrated value from the charge integrator output exceeds the reference value, the slicer output comprising the discrete time binary digital signals z(n); and a charge digital to analog converter (qDAC) 46 coupled to an output of the slicer 44 and to the charge integrator 42, which produces the fixed value to be subtracted each time the integrated value exceeds the reference value, enabling the charge integrator 42 to operate within an operating range.

The discrete time binary digital signals z(n) output by the slicer may be mapped to the continuous time binary analog signals y(t) by the qDAC 46.

The sigma delta modulator 22 may have an output which is 1-bit binary valued. Alternatively, the sigma delta modulator 22 has an output which is more than 1-bit binary valued.

It should also be appreciated that if the photodiode 43 is operated at near zero volts, the dark current will be extremely small. Conventional CMOS image sensors reset the reverse diode voltage to a fixed value, to at least 2 to 3 volts at the beginning of the frame. The photo current reduces this voltage and the diode voltage drop is measured at the end of the frame time. This incurs a lot of noise in a dark part of the image where the voltage drop is small.

At very high illumination conditions, it is acceptable to increase the voltage (reverse bias) since the dark current will be relatively small compared to the photo current. This provides a wider linear range before diode saturation, therefore a high dynamic range

A small diode voltage fluctuation may occur and is acceptable, since the photo current is extremely linear to illumination, and not affected by the diode voltage, unless the illumination level is extremely high. This is one of the key advantages of charge-based sensing, rather than voltage-based sensing of current CMOS sensors. In a real implementation in CMOS, the photodiode capacitance might be sufficiently high relative to rest of the circuit elements, and the C1 integrator capacitor may not be needed.

The plots at FIGS. 9-11 show an example of a single FFV pixel operation. FIG. 9 shows a simulated photo current into the photodiode, x(t), plotted against time in clock cycles. Each value represents a brightness at that pixel location at that time instance.

FIG. 10 shows the FFV pixel SDM output y(t) at the oversampling ratio (OSR) of 1× as an overlay on top of the FFV photodiode current of FIG. 9. The signal z(n) is the discrete version of the signal y(t). The SDM output y(t) is binary valued. I_max=255. In this plot, either y(t)=255 (z(n)=1) or y(t)=0 (z(n)=0).

FIG. 11 shows the reconstruction from the FFV pixel SDM output y(t) for an oversampling ratio (OSR) of 8×. The clock rate has increase by 8×, generated 8× more data, which was filtered and decimated by 8× to match the input time scale. Most of the reconstruction noise is in the high frequency, which improves as OSR increases.

FIG. 12 shows a simulation of an output of a conventional (prior art) imaging pixel with a shutter opening at 50% duty cycle as an overlay on top of the FFV photodiode current of FIG. 9. Notice that the output values do not always track the input because of the frame boundary and short shutter duration. In this example, a low frame rate was chosen for easier illustration.

FIG. 13 shows a prior art of a second order sigma delta modulator that can be utilized in the pixel circuitry of the present invention. In the FIG. 13 embodiment, two integrator circuits 42 are arranged in series with the DAC 46 in a feedback loop which feeds into the input of the first integrator 42 and the input of the second integrator 42. The second order SDM typically provides an improved signal-to-noise ratio (SNR) for the same OSR compared to a first order SDM circuit, or a similar SNR for a reduced OSR compared to the first order SDM. A disadvantage with the second order SDM is a reduced dynamic range in order to prevent loop instability and a higher circuit complexity. An alternative would be to have a first order SDM modulator at the pixel and implement a re-modulation elsewhere, to convert it to second order or higher order SDM.

Those skilled in the art will appreciate that present invention can be implemented with higher order SDMs as well.

FIG. 14 shows an example embodiment of end-to-end frame free video system in accordance with an example embodiment of the present invention. A continuous time video (CTV) camera 50 may comprise a lens 52 and a continuous time imaging sensor array 20 comprising L×M pixels, for continuously capturing photons incident on pixels of the imaging array to produce respective continuous time analog signals without any discontinuity in time. Each of the pixels of the imaging array 20 may comprise a photodiode and a modulator circuit (as discussed above) for modulating the respective continuous time analog signal into respective continuous time binary analog signal. For example, the pixel circuit for each pixel in the sensor array may be as shown in FIGS. 5, 6, 7, 8a and 8b and discussed above.

A processor 61 may be provided for aggregating the continuous time binary analog signals from all the pixels to produce a frame free video stream. A continuous time display array 40 for displaying the frame free video stream may comprise an L′×M′ array of light modulators. Each light modulator may be responsive to the SDM digital output of the corresponding pixel in the imaging array.

As discussed in detail above, for each pixel, the incident photon is integrated and converted to photo electric current x(t) continuously in time without photodiode reset or interruption. The SDM 22 converts the variation of the photo electric current at each pixel into a continuous time binary analog signal y(t) by continuous time sigma delta modulation. The slicer 44 outputs the discrete time binary digital signal z(n), which may be mapped to the continuous time binary analog signals y(t). The discrete time binary digital signals z(n) output from all pixels in the imaging array 20 can be aggregated into SDM bit-planes 54. A frame free video stream 56 comprising a time series of SDM bit-planes can then be produced. The frame free video stream 56 can then be subjected to various processing 58 (e.g., at processor 61 or other hardware and/or software components) to produce a frame free video signal 60. Such processing may include, but not be limited to, at least one of manipulating, format converting, encoding, transcoding, compressing, storing, transmitting, and otherwise representing the frame free video stream.

The frame free video signal 60 may then be transmitted, received, and subsequently processed 62 (e.g., decoded, decompressed, stored, transcoded, format converted or otherwise processed) to convert the frame free video signal 60 back into frame free video stream 56 (e.g., at processor 63 or other hardware and/or software components). The frame free video stream 56 may be converted back into SDM bit-planes 54 that can be subjected to display processing and format conversion 64 (e.g., at processor 63 or other hardware and/or software components), for display via the display array 40 that comprises L′×M′ binary light modulators. The format conversion may include changing the resolution of the original frame free video stream from L×M to L′×M′ that corresponds to the display resolution. Further format conversion may include changing the SDM clock rate.

The present invention also encompasses a system for representing video in continuous time comprising the pixel circuit of FIG. 8a or FIG. 8b. Such a system may comprise a continuous time imaging sensor array 20 for continuously capturing photons incident on pixels of the imaging array to produce respective continuous time analog signals without any discontinuity in time. Each of the pixels comprising a photodiode 43 and a sigma delta modulator circuit 22 for modulating the respective continuous time analog signal into a respective continuous time binary analog signal. The system may also comprise a processor 61 for aggregating the continuous time binary analog signals from all the pixels to produce a frame free video stream and a continuous time display array 40 for displaying the frame free video stream. In such a system, the photodiode 43 has a capacitance and the capacitance of the photodiode 43 functions as a charge integrator. The modulator circuit 22 may comprise a continuous time sigma delta modulator.

The present invention also encompasses a pixel for a continuous time imaging sensor array 20. The array may be made up of a plurality of pixels, each of which may comprise a photodiode 43 for capturing incident photons to produce a continuous time analog signal without any discontinuity in time and a sigma delta modulator circuit 22 for modulating the continuous time analog signal into a continuous time binary analog signal. The photodiode 43 has a capacitance and the capacitance of the photodiode 43 functions as a charge integrator. The continuous time binary analog signals from all pixels in the imaging sensor array 20 are aggregated to produce a frame free video stream.

Various embodiments of the system and pixel of the present invention may also encompass the features and functionality of the method embodiments discussed above.

Those skilled in the art will appreciate that various functionalities of the system may be carried out by one or more processors running on one or more computer devices. For example, the discrete time binary digital signals from all of the pixels in the imaging array may be aggregated by a processor to produce a corresponding binary bit-plane per each clock cycle of the sigma delta modulator to convert the frame free video to a frame free video stream. Encoders, transcoders, and other processing devices and/or software programs may be used for the various processing of the frame free video stream into a frame free video signal and vice versa.

With the present invention, the pixel circuit integrates incident photons continuously in time, without reset. Thus, there is no loss of photons, and no time aliasing. The pixel value corresponds to the number of photons integrated over unit time. The unit time corresponds to the SDM clock period. The SDM modulated output is a continuous time analog signal, its amplitude is quantized to binary values and the amplitude is constant during each SDM clock period. The SDM discrete time output maps those levels to 1's and 0's (binary). For example, a 2 volt level can be coded to a binary 1, and a 0 volt level can be coded to binary 0. The SDM bit-plane is an L×M collection of the discrete SDM output from each pixel. Each SDM bit-plane is produced for each SDM clock. The frame free video stream is the raw data out of the L×M imaging array, equivalent to a series of SDM bit-planes (L×M bits per bit-plane, every clock cycle).

The frame free video signal is an alternative representation of the frame free video stream (e.g., a compressed version of frame free video stream). Format conversion of the frame free video stream includes changing the dimension of the SDM bit-plane (to L′×M′) or changing the SDM clock rate for the bit-planes. The binary light modulator at the display 40 reproduces the continuous time analog signal of each SDM pixel, y(t). When the light modulator update rate (SDM clock rate) is fast enough, human eye sees the average brightness and the video is reconstructed in the eye.

The binary 1's and 0's from the discrete time binary digital signal may be mapped to a maximum value and a minimum value, respectively, to enable continuous time video processing or display.

FIG. 15 shows a further example embodiment of a pixel circuit adapted to reduce or eliminate dark current noise. The pixel circuit is similar to that of FIG. 8b discussed above, and comprises a photodiode 43 and a sigma delta modulator 22, the operation of which is discussed in detail above. However, in the FIG. 15 embodiment, the photodiode 43 may be biased at or near zero volts in order to reduce dark current noise. Many photodiodes produce lowest dark current at zero volt. Some photodiodes produce the lowest dark current at non-zero voltage, such as a PIN diode photodetector. The other terminal of the photodiode may be connected to ground or to a photodiode bias voltage source (PD_BIAS).

The photodiode 43 is not reset throughout the operation of the imaging array. The charge integrator 42 may maintain a voltage range of the photodiode 43 corresponding to a sum of a photo-current of the photodiode 43 and a negative of a feedback current of the sigma delta modulator 22, in order to maintain the voltage across the photodiode 43 close to a voltage where a photodiode dark current is minimal.

The method may further comprise integrating the photo-current of the photodiode 43 continuously in time without saturating the photodiode 43 by the charge integrator 42 to produce an integrated value which represents total photons converted to electrical charges. Each time the integrated value exceeds a reference value, a fixed value may be subtracted from the integrated value to enable the charge integrator 42 to operate within a narrow operating range with less than one volt deviation. A series of the subtracted fixed values over time may result in an estimate of the total integrated value, enabling the sigma delta modulator 22 to produce the continuous time binary analog signal representative of the brightness value at the pixel.

The charge integrator 42 may comprise at least one of the capacitance of the photodiode 43 and a capacitor C₁ in parallel with the photodiode 43 and coupled to an output of the photodiode 43.

The sigma delta modulator 22 may comprise: a slicer 44 coupled to the output of the charge integrator 42 for determining whether the integrated value from the charge integrator output exceeds the reference value, the slicer output comprising the discrete time binary digital signals; and a charge digital to analog converter (qDAC) 46 coupled to an output of the slicer 44 and to the charge integrator 42, which produces the fixed value to be subtracted each time the integrated value exceeds the reference value, enabling the charge integrator 42 to operate within an operating range which is substantially smaller than a power supply voltage (V_DD) of the pixel. For example, the charge integrator 42 typically can operate within 10 to 100 mV range, whereas the power supply voltage (V_DD) is typically 2 to 3 volts. The higher the V_DD, the higher the well capacity and better dynamic range, but at the cost of higher dark current noise.

When the charge integrator 42 is biased near zero volts, a qDAC bias voltage QD_BIAS may be applied to the qDAC 46 (e.g., from a current mirror circuit shared among many pixels), enabling the qDAC 46 to generate a programmable amount of a qDAC current I_qDAC which is applied to the photodiode 43 in order to maintain the photodiode voltage V_PD near zero volts. In addition, a slicer bias voltage (S_BIAS, that sets a threshold voltage) may be applied to the slicer 44. In such an embodiment, the slicer 44 compares the photodiode voltage V_PD with the slicer bias voltage S_BIAS to determine whether a fixed amount of charge is to be added to the photodiode 43 by the qDAC current I_qDAC in order to maintain a desired voltage across the photodiode 43. For example, by setting the slicer comparator bias voltage S_BIAS to PD_BIAS, the SDM loop will maintain the photodiode voltage V_PD slightly higher or slightly lower than PD_BIAS, but rarely at PD_BIAS exactly. The average voltage across the photodiode 43 will be zero. Alternatively, if the photodiode 43 has the lowest dark current at some other voltage, the photodiode 43 can be biased at a certain PD_BIAS and the slicer 44 could be biased at a certain S_BIAS, such that the difference is the desired voltage across the photodiode.

The qDAC current I_qDAC may be adjusted based on output from the slicer 44. For example, one of ones or zeroes output from the slicer 44 may be counted to determine the qDAC bias voltage QD_BIAS. Alternatively, a ratio of ones and zeroes output from the slicer 44 over time may be calculated to determine the qDAC bias voltage QD_BIAS.

An amount of gain applied to the qDAC 46 may be controlled by one of duty cycle modulation of the qDAC current I_qDAC (this can be accomplished by either a duty cycle modulation of the QD_BIAS voltage or a duty cycle modulation of the qDAC input), voltage modulation of a qDAC bias voltage source, and averaging of the qDAC bias voltage over time.

As shown in FIG. 16, when the photodiode 43 operates in a photovoltaic mode, the photo-current is used to power the qDAC 46. This helps to reduce power consumption when incident light is bright and generates too much photo-current, as V_DD is not needed to power the qDAC 46. The photovoltaic mode may occur when operating below the threshold voltage (e.g., both V_PD and PD_BIAS below 0.5 volts). However, when operating in photovoltaic mode, a slightly higher dark current will result since V_PD is not set to zero. When operating in the photovoltaic mode, accumulated photocurrent is drained to ground or to a lower potential node through the qDAC 46.

In a further example embodiment, at least one of an offset and a scale factor is applied to the pixel circuit to confine a black level and a white level of the frame free video between a minimum and a maximum of an output of the sigma delta modulator 22. A predefined offset may be applied to a black level of the frame free video. For example, the predefined offset may comprise 1/16 of a full level range.

As shown in FIG. 17, the predefined offset may be achieved by applying a small black level offset current I_BL to the charge integrator 42 that drains the integrated charge and simulates a small photocurrent, even in total darkness. The black level offset current I_BL may be provided by a black level offset current source 49 connected to the photodiode 43. The amount of the black level offset current I_BL may be programmable.

An average qDAC current I_qDAC applied to the charge integrator 42 may be equivalent to the black level offset current I_BL when there is no photo-current due to lack of incident photons on the photodiode 43.

Alternatively, as shown in FIG. 18, the predefined offset may be achieved by remodulating the continuous time binary analog signals Z from the sigma delta modulator 22 in the digital domain using a discrete time sigma delta modulator 23 (e.g., comprised of integrator 42′ and slicer 44′). In the FIG. 18 embodiment, a 1/16 offset value ( 16/256) is added to the output Z from the sigma delta modulator 22. The 1/16 offset used in the example embodiment shown in FIG. 18 is compatible with existing video standards. Those skilled in the art will appreciate that other offset factors may be used.

The predefined offset may be removed for signal manipulation and added back for subsequent processing of the signal.

A white level of the frame free video may be controlled via qDAC feedback gain (e.g. the total amount of charge applied to the photodiode 43 per slicer clock period via the SDM loop and the qDAC current I_qDAC). For example, the qDAC current I_qDAC may be set for the maximum photodiode current expected. The white level is usually defined to be below this maximum in order to reserve some headroom. A typical practice is to set this white level to 235/256 of the maximum. If the black level is defined as 16/256, then the full useable range of the video signal will be between 16/256 to 235/256 where 256 represents the maximum qDAC current.

In a further example embodiment of the present invention, the pixel circuitry may be modified to provide a low voltage readout of the pixel. Each pixel in the array performs continuous time sigma delta modulation and generates bits at a high rate (10 KHZ or higher bit-plane rate). When multiplied by the total number of pixels in an array(e.g., a 10-megapixel camera), the total data readout power can be very high. The present invention implements a low voltage readout strategy, where the power required is only ½ CV². For example, lowering the voltage swing at the column read out circuitry by 10× would result in 100× lower power.

As shown in FIG. 19, such a low voltage readout is achieved by having the sigma delta modulator 22 further comprise a storage capacitor C_SC at the output of the slicer 44. The storage capacitor C_SC may be charged after each slicer decision. A row select switch 66 may share the charge (e.g., from M12 transistor) with a column capacitance C_COL connected to column readout circuitry of the imaging array. A further slicer 68 senses a small voltage change due to the charge on the column capacitance C_COL and makes a binary decision, where the binary decision output over time comprises a discrete time binary digital signal.

The column capacitance C_COL may be reset to a predetermined voltage after each slicer decision. The total column capacitance consists of all the pixel capacitances connected to that column line which can be many thousands of rows. On the other hand, the storage capacitor at each pixel can be much smaller than the total column capacitance which results in a lower voltage swing on the column line. Therefore this low voltage read out scheme significantly lowers the read out power consumption.

In case a differential read-out is desired, a pair of column lines may be provided such that the LVRO slicer can compare the difference between the two column lines and make a more reliable decision. In that case, both column lines would get reset before the next row read. Either one or two storage capacitors can be used at each pixel for this purposes. In case of one storage capacitor, the storage capacitor can be connected to receive the differential output of the pixel slicer 44, Z and Z\ (complement of Z).

The storage capacitor C_SC may enable a global shutter mode. That is, all storage capacitors in every pixel in the array can be clocked in from the respective slicer and read out at different times (e.g., one row at a time). For example, the global clock (G_CLK) would store the pixel slicer decision for the entire array all at once, then let each row be read out sequentially. Other strategies are also possible. If the global clock is only for each row in the pixel array, then a rolling shutter mode is achieved where each row has a slight offset in capture timing.

The method may further comprise processing the frame free video to provide multiple frame-based video streams at different resolutions and frame rates.

The present invention also encompasses a system for representing video in continuous time utilizing the pixel circuitry discussed above in connection with FIGS. 15-19. For example, the system described above in connection with FIG. 14 may be implemented with the pixel circuit of FIG. 15 to provide an output with a substantially reduced dark current noise. The system may also be implemented with the pixel circuitry of FIGS. 16-19 discussed above.

Those skilled in the art will appreciate that the frame free video signal may be used for other than display purposes. For example, such purposes may include but not be limited to artificial intelligence, computer vision, autonomous driving, drones (e.g., where the video information is not for human visual consumption). Because of the nature of alias free, continuous time representation of frame free video, the content is easier to analyze mathematically, especially with respect to motion. Thus, capture and transport of frame free video (as described above) with computer vision analysis is possible, instead of or in addition to the display of the video.

It should now be appreciated that the present invention provides advantageous methods, apparatus, and systems for representing video in continuous time, without frame breaks.

Although the invention has been described in connection with various illustrated embodiments, numerous modifications and adaptations may be made thereto without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A method for representing video in continuous time, comprising: continuously capturing photons incident on pixels in an imaging array using a continuous time imaging sensor array to produce respective continuous time analog signals without any discontinuity in time;modulating, at each pixel, the respective continuous time analog signal into a respective continuous time binary analog signal; andaggregating the continuous time binary analog signals from all pixels to produce a frame free video;

2. The method in accordance with claim 1, further comprising: at each pixel, mapping the continuous time binary analog signal to a discrete time binary digital signal consisting of 1's and 0's.

3. The method in accordance with claim 2, further comprising: aggregating the discrete time binary digital signals from all of the pixels in the imaging array to produce a corresponding binary bit-plane per each clock cycle of the sigma delta modulator to convert the frame free video to a frame free video stream;wherein the frame free video stream comprises a time series of the binary bit-planes.

4. The method in accordance with claim 1, wherein: the photodiode is not reset;the charge integrator maintains a voltage range of the photodiode corresponding to a sum of a photo-current of the photodiode and a negative of a feedback current of the sigma delta modulator in order to maintain the voltage across the photodiode close to a voltage where a photodiode dark current is minimal.

5. The method in accordance with claim 4, further comprising: integrating the photo-current of the photodiode continuously in time without saturating the photodiode by the charge integrator to produce an integrated value which represents total photons converted to electrical charges;each time the integrated value exceeds a reference value, subtracting a fixed value from the integrated value to enable the charge integrator to operate within a narrow operating range with less than one volt deviation;wherein a series of the subtracted fixed values over time results in an estimate of the total integrated value, enabling the sigma delta modulator to produce the continuous time binary analog signal.

6. The method in accordance with claim 5, wherein the charge integrator comprises at least one of: the capacitance of the photodiode; anda capacitor in parallel with the photodiode and coupled to an output of the photodiode.

7. The method in accordance with claim 5, wherein the sigma delta modulator comprises: a slicer coupled to the output of the charge integrator for determining whether the integrated value from the charge integrator output exceeds the reference value, the slicer output comprising the discrete time binary digital signals; anda charge digital to analog converter (qDAC) coupled to an output of the slicer and to the charge integrator, which produces the fixed value to be subtracted each time the integrated value exceeds the reference value, enabling the charge integrator to operate within an operating range which is substantially smaller than a power supply voltage of the pixel.

8. The method in accordance with claim 7, wherein when the photodiode operates in a photovoltaic mode the photo-current is used to power the qDAC.

9. The method in accordance with claim 8, wherein accumulated photocurrent is drained to ground or to a lower potential node through the qDAC.

10. The method in accordance with claim 7, wherein: the charge integrator is biased near zero volts;a qDAC bias voltage is applied to the qDAC, enabling the qDAC to generate a programmable amount of a qDAC current which is applied to the photodiode in order to maintain the photodiode voltage near zero volts;a slicer bias voltage is applied to the slicer which sets a voltage threshold; andthe slicer compares the photodiode voltage with the slicer bias voltage to determine whether a fixed amount of charge is added to the photodiode by the qDAC current in order to maintain a desired voltage across the photodiode.

11. The method in accordance with claim 10, wherein the qDAC current is adjusted based on output from the slicer.

12. The method in accordance with claim 11, further comprising counting one of ones or zeroes output from the slicer to determine the qDAC bias voltage.

13. The method in accordance with claim 11, further comprising calculating a ratio of ones and zeroes output from the slicer over time to determine the qDAC bias voltage.

14. The method in accordance with claim 10, further comprising one of: duty cycle modulation of the qDAC current; voltage modulation of a qDAC bias voltage source; and averaging of the qDAC bias voltage over time.

15. The method in accordance with claim 1, wherein: applying at least one of an offset and a scale factor to confine a black level and a white level of the frame free video between a minimum and a maximum of an output of the sigma delta modulator.

16. The method in accordance with claim 15, wherein a predefined offset is applied to a black level of the frame free video.

17. The method in accordance with claim 16, wherein the predefined offset comprises 1/16 of a full level range.

18. The method in accordance with claim 16, wherein the predefined offset is achieved by applying a small black level offset current to the charge integrator that drains the integrated charge and simulates a small photocurrent.

19. The method in accordance with claim 18, wherein the amount of the black level offset current is programmable.

20. The method in accordance with claim 18, wherein an average qDAC current applied to the charge integrator is equivalent to the black level offset current when there is no photo-current due to lack of incident photons.

21. The method in accordance with claim 16, wherein the predefined offset is achieved by remodulating the continuous time binary analog signals from the sigma delta modulator in the digital domain using a discrete time sigma delta modulator.

22. The method in accordance with claim 16, wherein the predefined offset is removed for signal manipulation and added back for subsequent processing of the signal.

23. The method in accordance with claim 15, wherein a white level of the frame free video is controlled via qDAC feedback gain.

24. The method in accordance with claim 7, wherein sigma delta modulator further comprises a storage capacitor at the output of the slicer.

25. The method in accordance with claim 24, wherein: the storage capacitor is charged after each slicer decision;a row select switch shares the charge with a column capacitance connected to column readout circuitry of the imaging array;a further slicer senses a voltage change due to the charge on the column capacitance and makes a binary decision, the binary decision output over time comprises a discrete time binary digital signal.

26. The method in accordance with claim 25, wherein the column capacitance is reset to a predetermined value after each slicer decision.

27. The method in accordance with claim 25, wherein the storage capacitor enables a global shutter mode.

28. The method in accordance with claim 1, further comprising processing the frame free video to provide multiple frame-based video streams at different resolutions and frame rates.

29. A system for representing video in continuous time, comprising: a continuous time imaging sensor array for continuously capturing photons incident on pixels of the imaging array to produce respective continuous time analog signals without any discontinuity in time;each of the pixels comprising a photodiode and a sigma delta modulator circuit for modulating the respective continuous time analog signal into a respective continuous time binary analog signal;a processor for aggregating the continuous time binary analog signals from all the pixels to produce a frame free video stream; anda continuous time display array for displaying the frame free video stream;wherein:the photodiode has a capacitance;the capacitance of the photodiode functions as a charge integrator;the photodiode is biased at or near zero volts in order to reduce dark current noise; andthe modulator circuit comprises a continuous time sigma delta modulator.

30. A pixel for a continuous time imaging sensor array, comprising: a photodiode for capturing incident photons to produce a continuous time analog signal without any discontinuity in time;a sigma delta modulator circuit for modulating the continuous time analog signal into a continuous time binary analog signal,wherein:the photodiode has a capacitance;the capacitance of the photodiode functions as a charge integrator;the photodiode is biased at or near zero volts in order to reduce dark current noise; andthe continuous time binary analog signals from all pixels in an imaging sensor array are aggregated to produce a frame free video stream.