Patent Application
20160344398
Aspects of the present disclosure relate to signal processing. More specifically, various implementations of the present disclosure relate to cascaded phase-locked loops (PLLs).
Conventional approaches for implementing and using phase-locked loops (PLLs), such as voltage-controlled-oscillator (VCO) based PLLs, may be costly, cumbersome, or inefficient—e.g., they may have limited frequency ranges. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present disclosure as set forth in the remainder of the present application with reference to the drawings.
System and methods are provided for cascaded phase-locked loops (PLLs), substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
These and other advantages, aspects and novel features of the present disclosure, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.
As utilized herein the terms “circuits” and “circuitry” refer to physical electronic components (e.g., hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y.” As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y, and z.” As utilized herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “for example” and “e.g.” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled or not enabled (e.g., by a user-configurable setting, factory trim, etc.).
The electronic system 100 may comprise suitable circuitry for implementing various aspects of the present disclosure. The electronic system 100 may be configured to support performing, executing or running various operations, functions, applications and/or services. The electronic system 100 may be used, for example, in executing computer programs, playing video and/or audio content, gaming, performing communication applications or services (e.g., Internet access and/or browsing, email, text messaging, chatting and/or voice calling services), providing networking services (e.g., WiFi hotspot, Bluetooth piconet, Ethernet networking, cable or satellite systems, and/or active 4G/3G/femtocell data channels), or the like.
In some instances, the electronic system 100 may enable and/or support communication of data. In this regard, the electronic system 100 may need to communicate with other systems (local or remote), such as during executing, running, and/or performing of operations, functions, applications and/or services supported by the electronic system 100. For example, the electronic system 100 may be configured to support (e.g., using suitable dedicated communication components or subsystems) use of wired and/or wireless connections/interfaces, which may be configured in accordance with one or more supported wireless and/or wired protocols or standards, to facilitate transmission and/or reception of signals (carrying data) to and/or from the electronic system 100. In this regard, the electronic system 100 may be operable to process transmitted and/or received signals in accordance with applicable wired or wireless protocols.
Examples of wireless standards, protocols, and/or interfaces that may be supported and/or used by the electronic system 100 may comprise wireless personal area network (WPAN) protocols, such as Bluetooth (IEEE 802.15); near field communication (NFC) standards; wireless local area network (WLAN) protocols, such as WiFi (IEEE 802.11); cellular standards, such as 2G/2G+(e.g., GSM/GPRS/EDGE, and IS-95 or cdmaOne) and/or 2G/2G+(e.g., CDMA2000, UMTS, and HSPA); 4G standards, such as WiMAX (IEEE 802.16) and LTE; Ultra-Wideband (UWB), and/or the like.
Examples of wired standards, protocols, and/or interfaces that may be supported and/or used by the electronic system 100 may comprise Ethernet (IEEE 802.3), Fiber Distributed Data Interface (FDDI), Integrated Services Digital Network (ISDN), cable television and/or internet access standards (e.g., ATSC, DVB-C, DOCSIS, etc.), in-home distribution standards such as Multimedia over Coax Alliance (MoCA), and Universal Serial Bus (USB) based interfaces.
Examples of signal processing operations that may be performed by the electronic system 100 may comprise, for example, filtering, amplification, analog-to-digital conversion and/or digital-to-analog conversion, up-conversion/down-conversion of baseband signals, encoding/decoding, encryption/decryption, and/or modulation/demodulation.
In some instances, the electronic system 100 may be configured to support input/output (I/O) operations, to enable receiving input from and/or providing output to users. Accordingly, the electronic system 100 may comprise components or subsystems for obtaining user input and/or providing output to the user. For example, the electronic system 100 may support input/output (I/O) operations for allowing user interactions which may be needed for controlling the electronic system 100 or operations thereof—e.g., allowing users to provide input or commands, for controlling certain functions or components of the electronic system 100, and/or to output or provide feedback pertaining to functions or components. The electronic system 100 may also support input/output (I/O) operations in conjunction with use of data (e.g., multimedia content). For example, the electronic system 100 may support generating, processing, and/or outputting of video and/or acoustic signals, such as via suitable output devices or components (e.g., displays, loudspeakers, etc.). In this regard, the output signals may be generated based on content, which may be in digital form (e.g., digitally formatted music or the like). Similarly, the electronic system 100 may support capturing and processing of video and/or acoustic signals, such as via suitable input devices or components (e.g., cameras, microphones, etc.), to generate (e.g., to store or communicate) corresponding data. The corresponding data may be in digital form (e.g., digitally formatted music, video, or the like).
The electronic system 100 may be a stationary system (e.g., being installed at, and/or configured for use only in particular location). In other instances, however, the electronic system 100 may be a mobile device—i.e. intended for use on the move and/or at different locations. In this regard, the electronic system 100 may be designed and/or configured (e.g., as handheld device) to allow for ease of movement, such as to allow it to be readily moved while being held by the user as the user moves, and the electronic system 100 may be configured to perform at least some of the operations, functions, applications and/or services supported on the move.
Examples of electronic systems may comprise handheld electronic devices (e.g., cellular phones, smartphones, or tablets), computers (e.g., laptops, desktops, or servers), dedicated media devices (e.g., televisions, game consoles, or portable media players, etc.), set-top boxes (STBs) or other similar receiver systems, and the like. The disclosure, however, is not limited to any particular type of electronic system.
In operation, the electronic system 100 may be operable to perform various operations, functions, applications and/or services. For example, in some instances, electronic system 100 may be operable to communicate (send and/or receive) data, and to process the communicated data. In this regard, communication of data, whether over wired or wireless interfaces, may typically comprise transmitting and/or receiving signals that are communicated over wireless and/or wired connections. For example, analog radio frequency (RF) signals may be used to carry data (e.g., content), with the data being embedded into the analog signals in accordance with particular analog or digital modulation schemes. For analog communications, data is transferred using continuously varying analog signals, and for digital communications, the analog signals are used to transfer discrete messages in accordance with a particular digitalization scheme.
Accordingly, handling of the various operations, functions, applications and/or services supported or performed in the electronic system 100 may require performing various signal processing operations—e.g., to facilitate processing of data, reception and processing signals, generation and transmission of signals, extracting of data from or embedding into signals, and the like. Such signal processing may require use of various circuits that may perform and/or support various functions or operations.
For example the electronic system 100 may comprise one or more phase lock loops (PLLs). Each PLL 100 may comprise suitable circuitry for generating an output signal whose phase may be related to the phase of an input signal. In this regard, PLLs may be used to generate outputs (signals) that may be kept locked, in phase, to the PLLs' inputs (e.g., signals). In other words, PLLs may be configured such that their output signal(s) and the input signal(s) remain locked to one another—e.g., in phase. Keeping the input and output phase in lock may also allow keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a phase locked loop may be used to track an input frequency, or it can generate a frequency that is a multiple of the input frequency.
Therefore, PLLs may be utilized as control systems or components, providing signals for use in such operation as clock synchronization, demodulation, frequency synthesis, and the like. For example, PLLs may be utilized in radio, television, communications, computers and other electronic applications. In this regard, PLLs may be utilized in these systems to demodulate signals, recover signals (e.g., from noisy communication channels), generate a stable frequency at multiples of an input frequency (e.g., for frequency synthesis), and/or distribute precisely timed clock pulses (e.g., in digital circuits such as microprocessors).
Various architectures and/or designs may be used in implementing phase lock loops (PLLs). In its most basic implementation, a conventional phase locked loop may comprise, for example, a variable frequency oscillator component and a phase detector, with the frequency oscillator component generating a periodic signal and the phase detector comparing the phase of that generated signal with the phase of an input signal of the phase detector—e.g., to adjust the oscillator component generating, based on the comparison, to keep the phases matched. PLLs may function based on feeding back. In this regard, the output signal of the PLL may be “fed back” toward the input signal of the PLL—that is the output signal is brought back toward the input signal for comparison, thus forming a loop. An example implementation is shown in
The PLL 200 may be similar to the PLL 100 of
The PFD/CHP block 210 may comprise suitable circuitry for detection of phase and/or frequency difference, and for applying adjustments (e.g., to a block input), such as based on detected differences and/or other inputs. In particular, with respect to the phase and/or frequency detection, the PFD/CHP block 210 may be operable to detect the difference in phase and/or frequency between the input signal 115 (a reference signal) and feedback signal 241 (outputted by the divider 240), and generate a corresponding error information (e.g., signal) based on (e.g., proportional to) the phase differences. The error information (signal) may be used in adjusting the frequency at which the VCO 230 is operating (e.g., adjust the VCO 230 to operate at a higher or lower frequency). The PFD/CHP block 210 may be operable to output charge (or current) adjustment based on the error information (signal), such as using charge pumping. For example, via the output 211, the PFD/CHP block 210 may be operable to drive current into LPF 220 to ‘up’ (increase) the frequency, or draw current from the LPF 220 to ‘down’ (lower) the frequency.
The LPF 220 may comprise suitable circuitry for applying the changes to the VCO 230, such as by converting the charge (current) adjustments 211 applied by the PFD/CHP block 210 into a control voltage 221 that is used to bias the VCO 230. The LPF 220 may be, for example, a low-pass filter.
The VCO 230 may comprise suitable circuitry that may be operable to function as an electronic oscillator whose oscillation frequency is controlled by a voltage input (e.g., the control voltage 221). The VCO 230 may generate an output 231 representing the output of the PLL 200. In addition to the actual intended uses (for the PLL 200), the output 231 of VCO 230 may be looped back, for use in controlling phase (and frequency) of signals of the PLL 200. In this regard, the divider 240 may be inserted in the feedback loop to produce a frequency synthesizer, so as to allow the VCO 230 frequency above the frequency of the reference signal Fref 201.
In accordance with the present disclosure, performance of conventional PLLs may be enhanced, in an optimized manner. For example, in various example implementations of the present disclosure, modified architectures may be used to enable use of PLLs with a large programmable frequency range while using an input reference frequency of relaxed phase-noise. Such architectures may be used, for example, to provide a low phase-noise clock synthesizer with large programmable frequency range. In a conventional PLL (e.g., PLL 200), the loop-bandwidth may be limited (e.g., to 1/10th of frequency of the input (reference) signal) for stability. Further, beyond the unity-gain bandwidth (UGB) of the PLL-loop, PLL phase-noise is typically limited by VCO phase-noise. To generate a low phase-noise clock with large programmable frequency-range, a low phase-noise VCO with large tuning-range may be required. Low phase-noise VCOs may be invariably designed with high-Q inductor/capacitor (LC) tanks; but low phase-noise LC-based VCOs typically may have small tuning-range.
To obtain different frequencies, VCOs with different oscillation frequency may be multiplexed. Such approach may, however, increase circuit complexity, power-consumption, noise and area as multiplexing at high-frequency comes with added complexity, power consumption, its associated noise and area. Further, power-supply noise leaks into output clock through the multiplexing switches degrading its phase-noise and spurious performance. Implementations in accordance with the present disclosure may be incorporated modified and optimized architecture that may address such problems. Such architecture may comprise a low phase-noise VCO with small tuning range combined with another VCO having large tuning range whose phase-noise requirement may be relaxed. An example of such architecture is described in more detail with respect to
The architecture 300 may essentially include multiple PLLs (e.g., two PLLs, as shown in the example implementation depicted in
For example, each of the VCOs 3301 and 3302 may be configured to oscillate at particular frequency and/or may to have particular tuning range. Thus, the VCOs 3301 and 3302 may have different frequencies and/or different tuning ranges. Further, each of the dividers 3401 and 3402 may be configured to apply a particular division factor. Thus, the dividers 3401 and 3402 may apply different division factors (e.g., factor N for divider 3401 for and factor M for divider 3402, with N and M being non-zero integers). In some instances, the components may be adjusted adaptively and/or dynamically—e.g., division factors N and M may be adjusted.
As illustrated in
The unity-gain frequency of Loop_1 (UGB1) may be kept arbitrarily low to filter-out phase-noise from the input (reference) Fref. Thus, phase-noise of the output Fout may be determined by phase-noise of the VCO 3301 in the frequency range [UGB1, f1/10]. Frequency of the output Fout may be adjusted, such as by adjusting the division factor M applied in Loop_2. Further, the tuning range of the VCO 3301 may be minimized, such as by adjusting (simultaneously) the division factor N applied in Loop_1 to a suitable value. Accordingly, overall performance of the architecture 300 may adjusted adaptively and/or dynamically, by adjusting one of more of each of the VCO frequencies (f1 and f2) and the division factors applied in the feedback loops (M and N).
Table 1, below, illustrates different combinations of values for M, N, f1 and f2 in particular user scenario (e.g., with input (reference) Fref of 100 MHz.). As shown in the table, to vary f2, frequency of the VCO 3302, (which corresponds to the frequency of output Fout) between 20 GHz to 42 GHz, the frequency of VCO 3301, f1, need only vary from 1.9 GHz to 2 GHz. Thus, the VCO 3302 has a range of 20 GHz to 42 GHz, but its phase-noise can be relaxed as unity-gain frequency of Loop_2 (UGB2) may be increased to 190 MHz while keeping the unity-gain frequency of Loop_1 (UGB1) arbitrarily low to filter-out phase-noise of Fref. Since the range of the VCO 3301 is lower, it may achieve desired phase-noise with lower power-consumption compared to a conventional solution of multiplexed high-frequency VCOs. Further, the cascaded approach may also achieve better power-supply rejection as it avoids multiplexing switches that leak supply-noise into the output Fout as may occur in conventional approaches.
In step 402, an input (reference) signal (Fref) may be received.
In step 404, desired frequency range for the output (Fout) may be determined.
In step 406, suitable combination(s), for achieving the desired performance, for various operational parameters relating to functions of elements in cascaded PLL arrangement (e.g., M, N, f1, etc.) may be determined.
In step 408, the parameters (as determined in the prior step) may be applied to the corresponding elements.
In step 410, performance of the arrangement may be monitored, and (if needed) necessary adjustment may be made—e.g., in a similar manner as described with respect to steps 406-408.
Other embodiments of the invention may provide a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the processes as described herein.
Accordingly, various embodiments in accordance with the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computing system with a program or other code that, when being loaded and executed, controls the computing system such that it carries out the methods described herein. Another typical implementation may comprise an application specific integrated circuit or chip.
Various embodiments in accordance with the present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.
While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1453/DEL/2015 | May 2015 | IN | national |
This patent application makes reference to, claims priority to and claims benefit from each of Indian Provisional Patent Application Serial No. 1453/DEL/2015, filed May 22, 2015, and U.S. Provisional Patent Application Ser. No. 62/194,561, filed Jul. 20, 2015. Each of the above identified applications is hereby incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62194561 | Jul 2015 | US |
