Patent Application
20050102468
1. Field of the Invention
The invention relates to storage devices coupled to multiple initiators and more specifically relates to an interposer for coupling serial ATA devices to multiple storage controllers.
2. Discussion of Related Art
Computer storage subsystems often utilize multiple storage devices within the subsystem for improving reliability and/or performance of the storage system. Reliability is enhanced in storage subsystems utilizing multiple storage devices by generation and storage of redundant information on storage devices within the storage subsystem. For example, RAID storage subsystems (Redundant Array of Independent Drives) generate and store redundant information on storage devices of the storage subsystem so that failure of a single storage devices (e.g., disk drive) allows continued operation of the subsystem and prevents loss of data. A variety of RAID management techniques known as RAID “levels” are well known to those of ordinary skill in the art to provide such redundancy. Performance of a storage subsystem may be enhanced by utilizing multiple storage devices through techniques known as striping. In essence, striping distributes data over multiple storage devices so that a single read or write I/O request may utilize data transfer bandwidth of multiple, simultaneously operable, storage devices. I/O requests so processed utilizing multiple, concurrently operable storage devices complete data transfer more rapidly by utilizing the parallel bandwidth available from multiple storage devices as compared to the time to complete the operation from a single storage device.
To further enhance both reliability and performance in storage subsystems it is also known to provide multiple storage controllers within such a storage subsystem. Multiple controllers may be utilized to enhance reliability by permitting continued storage system operation in the event of a storage controller failure. A second controller may assume responsibility for the I/O operations of the failed controller. In addition, multiple storage controllers may be utilized to enhance performance of the storage subsystem by utilizing processing capabilities of multiple storage controllers for processing I/O operations in parallel.
In such a multiple controller storage subsystem, each controller typically uses its own communication path to the storage devices—or even multiple redundant communication paths. Hence, it is common to utilize storage devices generally configured to permit such multiple controllers (i.e., multiple initiators) to access the storage device substantially concurrently.
To enable such high performance storage subsystems having multiple controllers each coupled to each storage device and including the capability of concurrent access to storage devices by multiple storage controllers, storage devices and controllers supporting SCSI protocols and communication media are often utilized. SCSI protocols and communication media inherently permit such multiple concurrent access between storage controllers and storage devices. Utilization of SCSI protocols and communication media tends to increase cost of the storage subsystem as compared to other, lower cost, mass market storage devices supporting other protocols and communication media generally available in the market. For example, ATA storage devices tend to be substantially lower cost as compared to SCSI storage devices providing similar storage capacity. In particular, serial ATA (SATA) storage devices provide similar storage capacity and similar performance by utilizing high speed serial interfacing techniques to couple the storage controllers to SATA storage devices. However, ATA and SATA devices do not inherently support multiple controllers concurrently accessing the storage device.
The SATA Working Group is a trade association that has developed, maintains and publishes specifications for SATA device interfacing standards. SATA Working Group has also produced specifications for a multiplexing device referred to as a Port Selector for permitting enhanced operation of SATA storage devices by permitting multiple, concurrently operating storage controllers to access an SATA storage device. Specifications for SATA devices and for an SATA Port selector are publicly available at http://www.serialata.org.
The Port Selector specification suggests such a design implemented as an electronic signal multiplexer where the selection input of the multiplexer determines which of multiple storage controllers is presently coupled to the storage device. In general, the specification calls for a multiplexer device (also referred to herein as a port selector or interposer) be provided as an electronic circuit card coupled between the multiple storage controllers and a corresponding SATA storage device. The specification suggests that port selection may be provided by either of two specified approaches: protocol based port selection or sideband port selection. In protocol based port selection, each host storage controller may generate out-of-band signals directed to the port selector instructing the port selector to select the corresponding storage controller as the presently active controller coupled to the SATA storage device. Sideband port selection merely specifies that other protocols outside the scope of SATA standards may be used for selecting the presently active storage controller for coupling to the storage device.
A problem with protocol based port selection arises in that the storage controllers must be aware of the presence of the interposer (port selector) so that they may properly direct the port selector to select the desired coupling to a storage controller. Such a requirement imposes changes on existing storage controller architectures and operation. An existing storage controller architecture adapted to control SATA devices must add support for control of the port selector (interposer) if multiple storage controller may concurrently access the devices.
It is evident from the above discussion that a need access for an improved interposer architecture for coupling SATA storage devices to multiple storage controllers in a manner that is transparent to both the storage controllers and attached storage devices.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing methods and systems that automatically select an active port for coupling an SATA storage device to one of multiple storage controllers and that do so in a manner transparent to both the controllers and the storage devices. Features and aspects hereof provide and interposer circuit and methods for operation of an interposer electronically positioned between signals exchanged between SATA devices and corresponding storage controllers. Features and aspects of such an interposer include logic to automatically detect which of multiple storage controllers should be selected as the presently active controller coupled to the SATA storage device and to couple the appropriate controller thereto thus permitting multiple initiators to actively and concurrently submit commands to a storage device in an independent and uncoordinated fashion by comparison with prior techniques the required careful coordination.
One feature hereof therefore provides an interposer for coupling multiple active storage controllers to a SATA storage device, the interposer comprising: a multiplexer for selectively coupling SATA signals between the SATA storage devices and a selected storage controller of the multiple active storage controller; and control logic coupled to the multiplexer for automatically controlling the multiplexer to select the selected storage controller.
Another aspect hereof further provides that the multiplexer further comprises: a receive signal multiplexer for selectively coupling a transmit signal from the selected storage controller to a receive signal path of the SATA storage device; and a transmit signal multiplexer for selectively coupling a transmit signal from the SATA storage device to a receive signal path of the selected storage controller.
Another aspect hereof further provides that the control logic further comprises: an idle signal generator for generating an idle signal, such that the transmit signal multiplexer is operable to selectively couple the idle signal generator to all non-selected controllers of the multiple active storage controller to apply the idle signal to each of the non-selected controllers.
Another aspect hereof further provides that the idle generator is adapted to generate ATA SYNC primitives to the non-selected controllers.
Another aspect hereof further provides that the control logic further comprises: a detector for detecting the initiation of a transfer by a requesting controller of the multiple active storage controller, such that the control logic is operable to select the requesting controller as the selected controller in response to detection of initiation of a transfer by the requesting controller.
Another aspect hereof further provides buffers associated with each controller of the multiple active storage controllers and with the SATA storage device and coupled to the control logic for maintaining alignment of transferred information in conjunction with selection of the multiplexer by the control logic.
Another feature hereof provides an interposer for selectively coupling a SATA storage device and a plurality of controllers, the interposer comprising: detection means for detecting a request by a select controller of the plurality of controller to initiate a transfer to the storage device; and multiplexing means responsive to the detection means for coupling the select controller to the storage device.
Another aspect hereof further provides that the storage device has a transmit signal and a receive signal and such that each controller of the plurality of controllers has a transmit signal and a receive signal, and such that the multiplexing means further comprises: means for coupling the transmit signal of the select controller to the receive signal of the storage device; and means for coupling the receive signal of the select controller to the transmit signal of the storage device.
Another aspect hereof further provides idle generation means for generating SATA SYNC primitives, such that the multiplexing means further comprises: means for coupling the receive signal of each non-selected controller of the plurality of controllers to the idle generation means.
Another aspect hereof further provides that the idle generation means further comprises: a plurality of SATA SYNC primitive generators each associated with a corresponding controller of the plurality of controllers.
Another aspect hereof further provides that the detection means detects the request based on in-band SATA information from the select controller.
Another feature hereof provides a storage system comprising: a plurality of storage controllers; a SATA storage device; and an interposer coupled between the SATA storage device and each of the plurality of storage controllers for selectively coupling a selected controller of the plurality of storage controllers to the SATA storage device such that the interposer is operable to select the selected controller based solely on in-band SATA information generated by the plurality of storage controllers.
Another feature hereof provides a method for selectively coupling multiple active storage controllers to a SATA device comprising the steps of: a) detecting a request to start a transfer between a requesting controller of the plurality of storage controllers and the SATA storage device; b) coupling the requesting controller to the SATA device; and c) transmitting idle information to the plurality of storage controllers other than the requesting controller.
In like manner, multiplexer M2352 and M3354 may be used to select a source signal from multiple signals that may be applied to the receive data signal path of either controller 302 and controller 304, respectively. Selection signal R1S 336 may be generated by control logic 308 and applied to a selection input signal of multiplexer M2352. Selection signal R2S 334 may be generated by control logic 308 and applied to a selection input signal of multiplexer M3354.
More specifically, multiplexer M1350 receives signal H1T 332 (the transmit signal from controller 302) as a first input signal and H2T 330 (the transmit signal from controller 304) as a second input to multiplexer M1350. Based on the selection signal HTS 338 generated by control logic 308, either signal H1T 332 or signal H2T 330 is selected for application to storage device 310 via signal path 360. M2352 receives a transmit signal DT from storage device 310 on path 344 as one input and H1T 342 as a second input generated from control logic 308. H1T 342 is a signal generated by control logic 308 to provide SYNC primitives in accord with SATA standards during periods in which controller 302 is not the selected controller coupled to the storage deice 310. Based on selection input signal R1S 336, multiplexer M2352 will select either DT 344 or H1T 342 for application to the receive signal path 362 of controller 302. Similarly, multiplexer M3354 receives device transmit signal 344 as a first input and H2R 340, generated by control logic 308, as a second input. H2R 340 is a signal generated by control logic 308 to provide SYNC primitives in accord with SATA standards during periods in which controller 304 is not the selected controller coupled to the storage device 310. Based on selection signal R2S 334 generated by control logic 308, multiplexer M3354 will apply either DT 344 or H2R 340 to receive signal path 364 of controller 304.
H1T 342 and H2R 340 represent signals generated by control logic 308 for application to a presently non-selected controller while the selected controller receives the actual data transmission (DT 344) from storage device 310. Essentially, when controller 302 is presently selected as the active controller by control logic 308, DT 344 is coupled to receive signal 362 of controller 302 and H1T 332 is coupled to receive signal 360 of storage device 310. When controller 304 is presently selected as the active controller, DT 344 is coupled to receive signal 364 of controller 304 and transmit signal H2T 330 of controller 304 is applied to receive signal 360 of storage device 310. The transmit signal of one of the multiple controller (i.e., H1T 332 or H2T 330) is always coupled to the receive signal path 360 of the storage device 310 so that the device always perceives connection to some controller. The receive signal corresponding to the controller presently having its transmit line coupled to the storage device is preferably coupled through M2 or M3 to the transmit signal DT 344 of the storage device 310. However, the receive signal of all controllers (i.e., both 362 and 364) may be simultaneously coupled to the corresponding sync generation signal path (H1R and H2R) if required for a particular application.
A more complete description of signals received and generated by control logic 308 may be as follows:
Those of ordinary skill in the art will recognize that multiplexer configurations shown in
As a matter of design choice, one implementation for assuring such word alignment provides that control logic 308 maintains a one word (i.e., 40 bit) buffer for each of the various receive line signal paths associated with the interposer 300 (i.e., receive paths 360, 362 and 364). When switching between transmission sources to be applied to a corresponding received path, the receive signal buffer is first filled with successive transmission words from the selected source and is only then shifted into the actual stream of the receive signal only when the previous transmission has been completed. Although such a design introduces of latency of, at most, 40 bit times, such an effect has a negligible impact on performance. In addition, in order to avoid potential received data discrepancies, the internal mechanisms of control logic 308 may also include the ability to replace a given transmission word with its equivalent, opposite-RD-polarity variant in accordance with SATA standards. Such designs and design choices are well known to those of ordinary skill in the art and are discussed in SATA specifications. Those of ordinary skill in the art will recognize that
Upon detection of such a request to initiate a transfer by element 500, element 502 is operable to select the requesting controller as the presently selected or presently active controller. This process couples the transmit and receive signal paths of the selected controller to the corresponding receive and transmit signal paths of the storage device. As noted above, such coupling may be accomplished through simple multiplexing schemes or through more robust multiplexing schemes wherein buffering features of the interposer help assure proper alignment of the information exchanged between a selected controller and the data storage device (i.e., alignment through multiple, distinct clock domains). Element 504 is then operable to start (or continue) the requested transfer between the selected controller and the SATA storage device. In addition, element 504 is further operable to generate idle sequences (SYNC primitives) for application to receive signal paths of other, non-selected controllers. Providing such idle sequences (SYNC primitives) to non-selected controllers permits each controller to maintain the perception that it is directly connected to the SATA storage device.
While idle information is transmitted to other non-selected controllers, the selected controller and storage device interact according to standard SATA protocols to exchange desired information. Element 506 monitors the transfer between he selected controller an the SATA storage device to detect completion of the transmission. The interposer may detect completion of the exchange in accordance with the SATA specifications by detecting a framed information sequence having a type “Register—Device to Host” in which the Status register field has both the BSY and DRQ bits set to zero. Such an indication, in accordance with SATA standard, in-band exchanges indicates completion of the previously initiated request. Processing continues with elements 504 and 506 iteratively operable until completion is detected by element 506. Upon detection of completion of the previously initiated transfer, processing continues by looping back to element 500 to await a controller requesting initiation of a transfer to the storage device. As noted above, the presently coupled controller may remain coupled to the storage device until another request to initiate a transfer is detected above by element 500. Element 502 will then select the next appropriate controller for coupling to the storage device and couple other controller receive signals to a corresponding SYNC generation signal. Where multiple controllers substantially simultaneously request initiation of a transfer, well known arbitration techniques may be employed to determine which requesting controller is next serviced.
The flowchart of
As shown in the state machine diagram of
The following table describes the events that cause state transitions within the state diagram shown in
Those of ordinary skill in the art will recognize a wide variety of equivalent state machine models that may be used to describe the desired operation of the interposer. Further, those skilled in the art will readily recognize variations to the state machine models described herein to provide for any number of hosts/controllers coupled to the associated SATA device. The state machine models described herein and depicted in
While the invention has been illustrated and described in the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character. One embodiment of the invention and minor variants thereof have been shown and described. Protection is desired for all changes and modifications that come within the spirit of the invention. Those skilled in the art will appreciate variations of the above-described embodiments that fall within the scope of the invention. In particular, those of ordinary skill in the art will readily recognize that features and aspects hereof may be implemented equivalently in electronic circuits or as suitably programmed instructions of a general or special purpose processor. Such equivalency of circuit and programming designs is well known to those skilled in the art as a matter of design choice. As a result, the invention is not limited to the specific examples and illustrations discussed above, but only by the following claims and their equivalents.
