Patent Grant
8786592
This disclosure is related to methods and systems for driving electromechanical systems such as interferometric modulators.
Electromechanical systems (EMS) include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (such as mirrors and optical film layers) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of electromechanical systems device is called an interferometric modulator (IMOD). As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an interferometric modulator may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. In an implementation, one plate may include a stationary layer deposited on a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Interferometric modulator devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in a method of driving a display including a plurality of segment lines. The method may include transferring charge between segment lines through at least one inductor.
According to some aspects, a circuit for driving a display including a plurality of segment lines is disclosed. The circuit includes a power supply, a first segment line, and a second segment line. The circuit further includes at least one inductor, a first switching circuit configured to selectively connect the first segment line to one of the power supply and the at least one inductor, and a second switching circuit configured to selectively connect the second segment line to one of the power supply and the at least one inductor.
According to some aspects, a circuit for driving a display including a plurality of segment lines is disclosed. The circuit includes a power source selectively coupled to the plurality of segment lines and means for transferring charge between segment lines through at least one inductor.
According to some aspects, a computer program product for processing data for a program configured to drive a display including a plurality of segment lines is disclosed. The computer program product including a non-transitory computer-readable medium having stored thereon code for causing a computer to transfer charge between segment lines through at least one inductor.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following description is directed to certain implementations for the purposes of describing the innovative aspects of this disclosure. However, a person having ordinary skill in the art will readily recognize that the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device or system that can be configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the described implementations may be included in or associated with a variety of electronic devices such as, but not limited to: mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (i.e., e-readers), computer monitors, auto displays (including odometer and speedometer displays, etc.), cockpit controls and/or displays, camera view displays (such as the display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (such as in electromechanical systems (EMS), microelectromechanical systems (MEMS) and non-MEMS applications), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of EMS devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art.
According to some implementations, a switching circuit is provided for selectively connecting an interferometric modulator component to a positive voltage VS+, a negative VS−, a first switching rail, and a second switching rail. Each of the first and second switching rails is connected to an inductor through a switch. The polarity of the driving voltage is switched in order to reduce a build up of charge in the interferometric modulator component. When the polarity is switched, the interferometric modulator component is connected to an inductor through a switching rail by closing the associated switches. The component is thereby discharged through the switching rail and the connected inductor. A component which is being switched to the opposite polarity is also connected to the inductor through the second switching rail such that it is charged through the inductor. With this process, the discharged voltage of one segment may be used to charge the voltage of another segment, thereby reducing the amount of power consumption in the system.
According to some implementations, each switching rail may be connected to a separate inductor, such that there at least two inductors in the circuit. In a circuit having two inductors, the number of components being switched from a positive voltage to a negative voltage may not be equal to the number of components being switched from the negative voltage to the positive voltage. A charging current through each inductor may be used to charge any number of components undergoing a polarity switch. With this process, the discharged voltage of any number of first components may be used to charge any number of second components, thereby reducing the amount of power consumption in the system.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. An amount of energy consumed in driving a display device may be reduced by reusing energy in the system. The energy consumption may also be reduced even when a polarity switching operation is non-symmetric. The energy consumed may be reduced by up to 75% over prior art segment switching operations.
An example of a suitable EMS or MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the interferometric modulator. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity. One way of changing the optical resonant cavity is by changing the position of the reflector.
The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when unactuated, absorbing and/or destructively interfering light within the visible range. In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.
The depicted portion of the pixel array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, such as chromium (Cr), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and electrical conductor, while different, electrically more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or an electrically conductive/optically absorptive layer.
In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having ordinary skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be approximately 1-1000 um, while the gap 19 may be less than <10,000 Angstroms (Å).
In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the pixel 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, for example, a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD
In some implementations, hold voltages, address voltages, and segment voltages may be used which produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators from time to time. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.
During the first line time 60a: a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example,
As illustrated in
In implementations such as those shown in
The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (see block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting interferometric modulators 12 illustrated in
The process 80 continues at block 86 with the formation of a support structure such as post 18, illustrated in
The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in
The process 80 continues at block 90 with the formation of a cavity, such as cavity 19 illustrated in
One implementation of a driving circuit for driving a display, for example a passive matrix display similar to the IMOD displays discussed above or other passive matrix displays, will now be described in greater detail with reference to
Each of the segment lines 100, 102, 104, and 106 are connected to a switching circuit 314, 316, 318, and 320 respectively. Each of the switching circuits 314, 316, 318, and 320 includes four switches for selectively connecting segment lines 100, 102, 104, and 106 to a positive voltage VS+, a negative voltage VS−, the first switching rail 310, and the second switching rail 312. For example, switching circuit 314 includes switches S1-S4. Likewise, switching circuit 316 includes switches S5-S8, switching circuit 318 includes switches S9-S12, and switching circuit 320 includes switches S13-S16.
The first switching rail 310 is also connected to a first end of an inductor 300 through switch S17. Similarly, the second switching rail 312 is connected to the second end of the inductor 300 through switch S18. The inductor 300 may have an inductance of approximately 10 μH, but is not limited thereto. For example, the inductor 300 may have an inductance within a range of between about 5 μH to about 15 μH, but is not limited thereto. Each of switches S1-S18 may be provided as a single pole switch, and may be provided as a transistor implemented switch, or the like. The transistor can be a thin film transistor (TFT) or metal-oxide-semiconductor field effect transistor (MOSFET). The switches S1-S18, may have an effective resistance of approximately 1Ω, but is not limited thereto. For example, the switches S1-S18 may have an effective resistance of between about 0.5Ω to about 3Ω.
Although switching circuits 314, 316, 318, and 320, and switches S17 and S18 are illustrated as separate switching elements, one having ordinary skill in the art will recognize that the configuration is not limited thereto. For example, each of switches S1-S18 may be provided in a single switching circuit which is configured to provide switches S1-S18 as illustrated in
The operation of the driving circuit illustrated in
At a first time, T1, the polarities of segment lines 100, 102, 104, and 106 are triggered to be switched by the segment driver 26. The polarity switch may be initiated in order to reduce a build up of charge in the components of the display as discussed above. With reference to
Following the operation at T1, the segment driver 26 is configured to connect the switching rails 310 and 312 to the inductor 300 during a second phase, phase 2, of the polarity switching operation. As illustrated in
With reference to
After T3, as current continues to flow through the inductor, the voltage on segment lines 100 and 106 goes negative and the voltage on segment lines 102 and 104 goes positive. This reversal in the polarity of the voltage across the inductor causes the current through the inductor to decrease after time T3 while charge continues to be transferred from segment lines 100 and 106 to segment lines 102 and 104.
As the current through the inductor reaches zero (0) (or substantially zero, such as close enough to zero to prevent an excessive voltage spike across the inductor and to achieve close to maximum charge transfer in the forward direction through the inductor) at time T4, the voltage on segment lines 100 and 106 (which was initially VS+) approaches VS−, and the voltage on segment lines 102 and 104 (which was initially VS−) approaches VS+. At this point, the segment driver 26 is configured to disconnect the segment lines 100, 102, 104, and 106 from the inductor 300. For example, the circuit may include a current sensor (not shown) for sensing a current through the inductor 300. When the current through the inductor reaches zero (0) or substantially zero, the current sensor may be configured to send a signal to the segment driver 26. In response, the segment driver is configured to disconnect the segment lines from the inductor, and connect the segment lines 100, 102, 104, and 106 to the new respective power source voltage terminals to continue the polarity switching operation.
For example, with reference to
As a result of this polarity switching operation, a charge of a segment line which is switched from a first polarity to a second polarity can be used to charge a segment line which is being switched to from a second polarity to the first polarity. With reference to
In the example described above, the segment lines which are initially connected to the positive voltage VS+, segment lines 100 and 106, are switched to the first switching rail 310, while the segment lines which are initially connected to the negative voltage VS−, segment lines 102 and 104, are switched to the second switching rail 312. However, the operation of the segment driver 26 is not limited to this example. Alternatively, segment lines which are connected to the positive voltage VS+ may be switched to second switching rail 312, and segment lines which are connected to the negative voltage VS− may be switched to the first switching rail 310 by operation of the corresponding switches. In some implementations, the segment driver 26 may be configured to alternate which switching rail is used for the different polarity segment lines when the switches are closed at time T1. In a first operation, switching rail S17 may be connected to positive segment lines and switching rail S18 may be connected to negative segment lines at time T1. In the next operation, switching rail S17 may be connected to negative segment lines and switching rail S18 may be connected to positive segment lines at time T1. Furthermore, the segment driver may be configured to periodically switch the segment line having a voltage, positive or negative, which is connected to each of the switching rails 310 and 312 at time T1 in order to reduce a build up of charge in the switching rails 310 and 312.
The example described with reference to
The operation of one implementation of a segment driver 26 in a non-symmetric polarity switching operation will be described with reference to
In phase 2, only one of the segment lines 100, 102, and 104 is connected to a first end of the inductor 300. For example, segment line 104 is connected to a first end of the inductor 300 by closing switches S11 and S17, and opening switch S9. Segment line 106 is connected to the other end of inductor 300 by closing switches S16 and S18, and opening switch S14. Segment lines 100 and 102 are directly connected to VS−, by closing switches S2 and S6, and opening switches S1 and S5. In phase 3 of the polarity switching operation, switches S17 and S18 are set to an open position such that the first switching rail 310 and the second switching rail 312 are disconnected from the inductor 300. Subsequently, segment line 104 is connected to voltage VS− by closing switch S10 and opening switch S11, while segment line 106 is connected to voltage VS+ by closing switch S13 and opening switch S16. As a result, only segment lines 104 and 106 are configured to reuse energy during the polarity switching operation, while segment lines 100 and 102 are charged by connecting directly to power supply 54.
Alternatively, the segment driver 26 may be configured with two inductors in order to provide an efficient polarity switching operation even when the segment lines being switched are not symmetric.
The operation of the circuit of
In phase 2, each of segment lines 100, 102, and 104 is connected to a first end of the first inductor 302. These connections may be established by closing switches S3, S7, S11, and S17, and opening switches S1, S5, and S13. Segment line 106 is connected to the second end of the second inductor 304 by closing switches S16 and S18, and opening switch S14. As a result, a current I1 flows through the first inductor 302, and a current 12 flows through the second inductor 304. Since the configuration of
In phase 3 of the polarity switching operation, switches S17 and S18 are set to an open position such that the first switching rail 310 and the second switching rail 312 are disconnected from the first inductor 302 and the second inductor 304. Subsequently, segment lines 100, 102, and 104 are connected to voltage VS− by closing switches S2, S6, and S10 and opening switches S3, S7, and S11. Segment lines 100, 102, and 104 are charged by the connection to the power supply 54 to the negative voltage VS−. Segment line 106, which is fully charged, is connected to voltage VS+ by closing switch S13 and opening switch S16. As a result, a charge of segment lines 100, 102, 104 may be efficiently used to charge segment line 106, and the total energy used in the system during a polarity switch may be reduced as compared to a system that does not recover energy in the display when switching polarity, for example, by using inductors.
Any number of inductors may be provided in the circuit to achieve a combined inductance corresponding to the inductors 300, 302, and 304. For example, a plurality of inductors may be provided in series to provide a combined inductance value. Inductors may also be provided in parallel through switching circuits in order to change or control the inductance based on the requirements of the circuit during a polarity switching operation.
A method of driving a display during a polarity switch will now be described with reference to
The method may be implemented in the form of a computer program executed by a processor.
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48 and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an interferometric modulator display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, for example, data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g, n, and further implementations thereof. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1xEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, in some implementations, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (such as an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (such as an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (such as a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation can be useful in highly integrated systems, for example, mobile phones, portable-electronic devices, watches or small-area displays.
In some implementations, the input device 48 can be configured to allow, for example, a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, a touch-sensitive screen integrated with display array 30, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In implementations using a rechargeable battery, the rechargeable battery may be chargeable using power coming from, for example, a wall socket or a photovoltaic device or array. Alternatively, the rechargeable battery can be wirelessly chargeable. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The steps of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above also may be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other possibilities or implementations. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of an IMOD as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, a person having ordinary skill in the art will readily recognize that such operations need not be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
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