Patent Application
20110019760
The invention relates to the suppression of power-supply and reference-voltage noise in and between integrated circuits.
Transmitters and receivers in typical high-speed digital communication systems communicate data as series of symbols, each symbol representing a different logical value for a time period called a “unit interval,” or “UI.” Commonly, each symbol represents a single binary “bit” that represents either a logic one as a relatively high voltage or a logic zero as a relatively low voltage. A transmitter can thus convey data as bit patterns expressed as a voltage signal that transitions between the relatively high and low voltage levels. Adjacent like-symbols are represented by maintaining the same voltage over multiple UIs, whereas adjacent dissimilar symbols are represented by transitioning between voltage levels between UIs. A receiver can recover the bit patterns, and therefore the original data, by comparing the voltage signal against a reference voltage to distinguish between the high and low voltage levels during each UI.
Transmitters draw current from a power supply to express voltage levels and to transition between them. In high-speed systems, most supply current is drawn during the transitions. Patterns with few transitions thus tend to draw less supply current than transition-rich patterns. Average supply current thus varies with the data pattern being communicated.
Power supplies are imperfect. For example, the lines and pads used to convey supply current exhibit parasitic resistive, inductive, and capacitive impedances. Unfortunately, this impedance and the data-dependent supply current together cause the supply voltage to fluctuate. The reference voltage employed by the receiver can also be affected. The resulting supply and reference noise effect signal integrity and therefore limit performance.
Many systems support higher data rates by transmitting multiple data streams in parallel. For example, eight data channels may transmit eight data streams in parallel to communicate eight bits per UI. Unfortunately, simultaneously transmitting and recovering multiple bits exacerbates the problems of data-dependent supply noise because supply current can vary dramatically between UIs. In a simple eight-bit example, from zero to eight bits might change values from one UI to the next. The resulting problem is referred to by those of skill in the art as simultaneous switching noise, or SSN. Such instability can introduce significant errors in supply and reference voltages, and thus adversely impact performance.
Efforts to minimize SSN have focused in two general areas of improvement. The first attempts to reduce supply impedance and improve voltage regulation to reduce a system's sensitivity to changing supply current. Unfortunately, these improvements require complex and area-intensive circuitry. The second area of improvement encodes the transmitted data into more or less balanced symbol patterns to reduce changes in supply current between UIs. These solutions include the so-called 8b/10b code that maps eight-bit symbols into ten-bit symbols that draw a relatively constant supply current over time. While effective, this coding scheme requires the insertion of two additional bits for each eight-bit byte, and consequently reduces speed performance. Parallel systems address SSN using a coding scheme called “dynamic bus inversion,” or DBI. In an eight-bit example, a system employing DBI uses an extra channel to convey a ninth bit, or DBI bit, that inverts a subset of eight-bit data bytes that would otherwise draw the most supply current. Some DBI schemes are capable of reducing the total current drawn from a supply voltage to half that of a similar non-DBI systems. This improvement comes at the cost of additional circuit complexity and an additional communication channel, both of which increase cost.
The subject matter disclosed is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Transmitter 105 may be a memory component or part of a memory component that conveys data, addresses, and commands. Transmitter 105 includes a data source 120 that provides the parallel streams Di1(n)-Di4(n), and that may include e.g. a serial-to-parallel converter. A pair of pull-up amplifiers T1 and T3 amplify data streams Di1(n) and D3(n), respectively, using a relatively high supply voltage Vio on a like-named supply node to produce a respective pair of amplified versions of bit streams Di1(n) and Di3(n) as signals Da1(t) and Da3(t). In doing so, amplifiers T1 and T3 periodically draw respective supply currents Ip1 and Ip2 from supply node Vio. A pair of pull-down amplifiers T2 and T4 amplify data streams Di2(n) and Di4(n), respectively, using a relatively low voltage Gnd on a second supply node to produce a respective pair of amplified versions of the bit streams as continuous-time signals Da2(t) and Da4(t). Amplifiers T1 and T3 periodically send respective supply currents In1 and In2 to supply node Gnd. The amplifiers are single MOS transistors in this example, but may be implemented differently in other embodiment. At a minimum, each amplifier will have a control terminal (e.g. a gate) coupled to a signal source, a first current-handling terminal (e.g. a source) coupled to a supply node, and a second current-handling terminal (e.g. a drain) coupled to one of the channels. Although only four channels are shown connected to transmitter 105 for ease of illustration, transmitter 105 may support more or fewer channels in other embodiments.
The difference between common-mode voltage Vcmp and voltage Vio/2 is less than half the voltage swing of signal Da1(t), and the difference between voltage Vio/2 and common-mode voltage Vcmn is less than half of the voltage swing of signal Da2(t). Output signals Da1(t) and Da2(t) thus do not overlap in the voltage space. The remaining two data signals Da3(t) and Da4(t) have the similar characteristics and are thus omitted for ease of illustration. Expressing signals on alternate channels using non-overlapping voltage ranges reduces cross-talk, and thus improves signaling performance.
To further explain this advantage of transmitter 105, consider a conventional transmitter having four drivers each including a pull-up amplifier and a pull-down amplifier coupled in series between Vio and ground. For each driver, the pull-up amplifier can be used to drive a logic “1” over a link and the pull-down amplifier can be used to drive a logic “0” over the same link. In a worst case scenario, each driver is driving a logic “0” onto its respective link so that all four pull-down amplifiers are “on” while all four pull-up amplifiers are “off” at the same time. This results in a maximum supply current to ground, four times the maximum current i drawn by each pull-down amplifier, and a minimum supply current from node Vio. If, in the next unit interval, each driver drives a logic “1” so that all four pull-down amplifiers change at about the same time from being “on” to being “off” while all four pull-down amplifier change at about the same time from being “off” to being “on”, the supply current at the ground node could change from the maximum supply current, or 4i, to about zero, while supply current at the Vio node could change from zero to a maximum supply current of 4i.
Now consider transmitter 105 in
Returning to
Reference voltages V+ and V− can be developed locally in receiver 110, or can be sourced externally from e.g. transmitter 105. In one embodiment voltage V+ is calibrated during power-up using test patterns and voltage V− is derived from voltage V+, using an operational amplifier configured as an inverter and referenced from voltage Vio/2 for example. Termination voltage Vio/2 is developed using a local voltage reference 130 in this embodiment, but can also be developed elsewhere in other embodiments. Many methods of establishing and maintaining appropriate reference voltages are well known to those of skill in the art and are therefore omitted for brevity. Further, though omitted for brevity, system 100 can include control circuitry that calibrates and maintains termination resistances and drive currents to maintain optimal voltage swings for signals Da1(t)-Da4(t).
Voltage reference 130 maintains voltage Vio/2 by supplying or drawing a current Iterm from the termination node. Significant magnitudes and fluctuations of current Iterm induce noise on the termination node, and consequently reduce performance. The termination scheme of receiver 110 reduces the magnitude of current Iterm to reduce noise.
The following Table 1 relates each of the 16 possible data patterns Di[4:1] to termination current Iterm. As a simplifying assumption, termination current Iterm is the difference between the sum of the currents Ip1 and Ip2 and the sum of currents In1 and In2 (i.e., Iterm≈Ip1+Ip2−In1−In2). Also for simplicity, the on current for each amplifier T1, T2, T3, and T4 is assumed to be i and the off current zero. Those of skill in the art will appreciate that the precise current Iterm and its relationship to currents Ip1, Ip2, In1, and In2 is more complex than these assumptions, but will readily understand the operation of system 100 based on these illustrations.
Amplifiers T1 and T3 are implemented using PMOS transistors through which current passes when their respective control terminals are presented with relatively low voltages, whereas amplifiers T2 and T4 are implemented using NMOS transistors through which current passes when their respective control terminals are presented with relatively high voltages. Table 1 follows a convention in which data symbols Di[4:1] represent respective logic zero and one symbols using relatively low and high voltages. Logic zero data symbols thus turn amplifiers T1 and T3 on and amplifiers T2 and T4 off.
Pull-up currents Ip1 and Ip2 flow to termination node Vio/2 at receiver 110 via respective channels 115(1) and 115(3). In contrast, pull-down currents In1 and In2 flow away from termination node Vio/2 via respective channels 115(2) and 115(4), and thus tend to offset the pull-up currents. As illustrated in Table 1, the sum of the drive currents is zero for six of the sixteen possible four-bit symbols, plus or minus i for eight, and plus or minus 2i for the remaining two. In contrast, a similar transmitter implemented using four pull-down amplifiers would draw a worst-case current of 4i from node Vio/2. Receiver 110 thus provides for a factor-of-two reduction in worst-case termination current Item.
The background section above introduced dynamic bus inversion, or DBI, as a coding scheme that adds a ninth bit to eight-bit parallel data to reduce the total current drawn from the power supply for what would otherwise be power-intensive bytes. Assume, for example, an eight-bit parallel bus that conveys logic zero symbols by drawing current from a supply node. The worst-case current in such a case would occur when transmitting eight zero bits in parallel during one UI. Using DBI, the ninth channel is used to invert the bits for each byte that has more zeros then ones. For example, 00000111—1 (the last bit is the DBI bit) becomes 11111000—0. Setting the DBI bit to zero in this example tells the receiver to invert the bits to restore the original byte.
Using DBI in this example reduces the worst-case supply current used to express eight-bit bytes from eight to four (from 8i to 4i). By comparison, the eight-bit embodiment of
Systems in accordance with other embodiments support coding schemes that take advantage of additional channels to achieve still greater reductions in worst-case supply current. For example, an additional channel can be added, as in the aforementioned DBI technique, to support an additional bit encoded to reduce the worst-case current below |4i|, and thus to achieve better performance than DBI systems having the same number of channels. The additional channel may be implemented using a dedicated additional line or by reusing resources that are normally idle when transmitter 105 is active. The additional channel can use the same or a different signaling scheme. In one embodiment the additional channel is driven by a push-pull amplifier disposed between supply nodes Vio and ground. The push-pull amplifier can then be enabled in either direction to counter current imbalances created by the other channels.
For the transition of
Dashed lines in multiplexers DM1/2 and multiplexers M1/2 highlight the connectivity selected for the depicted two-channel, push-pull configuration. Transistors P1 and N1 form a CMOS amplifier that drives data signal Di1 to a receiver 605 via a channel 610; transistors P2 and N2 likewise form a CMOS amplifier that drives data signal Di3 to a receiver 605 via a channel 610. Data signals Di2 and Di4 are not used, and the pads associated therewith are not connected to receiver 610.
Receiver 610 can be a conventional receiver, and includes a pair of receive amplifiers RX1 and RX2 connected to respective channels to receive signals D1(t) and D3(t) from transmitter 605. The data terminals of the receive amplifiers include parallel terminations, though other methods of parallel and serial termination might also be used, as will be evident to those of skill in the art. Receive amplifiers RX1 and RX2 compare the incoming signal with a reference voltage Vio/2 from a regulator 615 to obtain output signals Do1(t) and Do3(t), which are then sampled by circuitry omitted from
Push-pull circuits like those of the programming option depicted in transmitter 600 have excellent drive characteristics and have been adapted to digital and analog applications as varied as stepping motor control, audio loudspeakers, and memory systems. Ideally, the complementary transistors for each driver switch simultaneously when the output voltage transitions between levels. In practice, however, process variations in the fabrication of the complementary devices, as well as variations in device performance due to operating voltage and temperature variations, prevent the realization of this ideal. As a consequence, it is common for both transistors in a complementary driver to be biased on or off for a very brief instant during output transitions.
Having both transistors momentarily on leads to what is colloquially referred to as “shoot-through” current between the supply nodes at the transmitter. The shoot-through phenomenon wastes power and transmits considerable noise onto the supply terminals and data channel. Having both transistors momentarily off creates a discontinuity in the signal transition that introduces noise on the channel. Considerable effort has been put into solving these problems, and a number of innovative solutions are available. The embodiment of
Avoidance of mismatched push and pull drivers is just one advantage of the embodiment of
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved.
An output of a process for designing an integrated circuit, or a portion of an integrated circuit, comprising one or more of the circuits described herein may be a computer-readable medium such as, for example, a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing circuitry that may be physically instantiated as an integrated circuit or portion of an integrated circuit. Although various formats may be used for such encoding, these data structures are commonly written in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), or Electronic Design Interchange Format (EDIF). Those of skill in the art of integrated circuit design can develop such data structures from schematic diagrams of the type detailed above and the corresponding descriptions and encode the data structures on computer readable medium. Those of skill in the art of integrated circuit fabrication can use such encoded data to fabricate integrated circuits comprising one or more of the circuits described herein.
While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, the unidirectional, point-to-point, chip-to-chip embodiments detailed previously are easily extensible to bidirectional systems, multi-drop buses, and to communication within and between larger or smaller systems. Furthermore, the advantages provided by the amplifiers and receivers depicted above can be extended to other types of signals. For example, continuous-time clock signals conveyed in parallel on an integrated circuit can suffer from SSN and may benefit from the solutions provided herein. In still other embodiments the transmitted signals can be multi-pulse-amplitude-modulated (multi-PAM) signals.
Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. Section 112.
| Number | Date | Country | |
|---|---|---|---|
| 61227204 | Jul 2009 | US |
