This invention relates to optical waveguide tapers and more particularly to a new class of optical waveguide tapers that exhibit constant loss per taper segment with reduced loss to prior art tapers.
Silicon photonics exploiting silicon photonic integrated circuits (PICs) relates to the application of photonic systems which use silicon as an optical medium. The silicon is usually patterned with sub-micrometer precision, into photonic components and photonic integrated circuits which operate in the infrared, most commonly at the 1550 nm (1.55 μm) wavelength window used by most fiber optic telecommunication systems as it is the lowest attenuation region for singlemode silica optical fibers. In reality the silicon typically lies on top of a layer of silica in what by analogy with a similar construction in microelectronics for transistors is known as silicon on insulator (SOI).
Silicon photonic devices exploit existing semiconductor fabrication techniques, and because silicon is already used as the substrate for most integrated circuits, it is possible to create hybrid devices in which the optical and electronic components are integrated onto a single microchip. Consequently, silicon photonics is being actively researched by many electronics manufacturers as well as by academic research groups.
Accordingly, within SOI waveguides the high index contrast between silicon (nSI=3.47), the underlying silica (silicon dioxide, SiO2, nSILICA=1.6), and either air (nAIR=1) or silica cladding, does not allow light, at 1550 nm, to extend into the silicon oxide beyond a fraction of a micron. The use of a rib loaded waveguide structure on the top surface of a silicon chip guides the optical power in the plane of the silicon as the effective refractive index in the region with the rib is higher than the adjacent regions without the rib. The resulting SOI waveguide is tightly confined vertically and loosely confined laterally and due to the index contrast Δn˜57% SOI waveguides have a small mode field diameter (MFD≈0.3 μm).
In contrast singlemode fiber (SMF) with a germanium doped silica core with silica cladding or silica core with fluorine doped silica cladding have a low index contrast, Δn≈0.036%, such that the typical MFD≈10.4 μm. Accordingly, when a silicon photonic device is to be interfaced to SMF optical fiber then the ratio of mode area ratio between SOI and SMF is approximately 1:1000 (SOI˜0.09 μm2:SMF˜85 μm2). Accordingly, it is necessary to implement silicon-on-insulator-based adiabatic waveguide tapers with a high coupling efficiency and small footprint in order to couple into the silicon photonic integrated circuits from the SMF optical fiber or vice-versa.
Within the prior art linear and parabolic tapers have been described and implemented to provide such transitions onto and off of the silicon photonic integrated circuit. However, these tend to be high loss and absorb valuable die footprint such that it would be beneficial to provide SOI PIC designers with a taper geometry that offers lower insertion loss and smaller footprint than the prior art but maintains compatibility with standard manufacturing methodologies.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
It is an object of the present invention to mitigate limitations in the prior art relating to optical waveguide tapers and more particularly to a new class of optical waveguide tapers that exhibit constant loss per taper segment with reduced loss to prior art tapers.
In accordance with an embodiment of the invention, there is provided a method comprising designing an optical waveguide taper by segmenting the optical waveguide taper into a number of segments such that the incremental loss between each consecutive pair of segments is approximately constant.
In accordance with an embodiment of the invention there is provided a waveguide comprising:
In accordance with an embodiment of the invention there is provided a device comprising a silicon-on-insulator (SOI) optical waveguide comprising an input of a first predetermined width and an output of a second predetermined width wherein the SOI optical waveguide varies according to a predetermined profile between the input and the output.
In accordance with an embodiment of the invention there is provided method of using a design rule for an optical waveguide structure in the design of said optical waveguide structures wherein the design rule relates to an optical waveguide taper such the optical loss versus propagation distance within the optical waveguide taper is approximately constant.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
The present invention is directed to optical waveguide tapers and more particularly to a new class of optical waveguide tapers that exhibit constant loss per taper segment with reduced loss to prior art tapers.
The ensuing description provides exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It being understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope as set forth in the appended claims.
A: Constant Loss Tapers
A1. Introduction
The large index of refraction contrast of a silicon-on-insulator (SOI) platform enables high density, cost-effective photonics on a chip. The typical interconnecting channel waveguide on 220 nm SOI has a 450 nm width resulting in a tightly confined mode profile. This type of waveguide is often used to connect integrated devices together since it minimizes the mode area of the waveguide, thereby enabling high-density optical circuitry while keeping the propagation loss small over short distances. However, at the junction between the interconnecting waveguide and the chip external coupling interface there is an intrinsic mode mismatch requiring mode conversion. Tapers are used to gradually convert the mode area and the effective index of the guided mode, typically by varying the waveguide width. In
The top-left inset in
Between points (w=450 nm)→(w=1000 nm), the EMA undergoes a direct, linear expansion as shown in the bottom inset of
From point (c) of
A2. Taper Tip Optimization
The coupling efficiency between an optical fiber and a SOI waveguide is determined by two main factors: the overlap integral of the electromagnetic fields between the fiber and the SOI waveguide at the tip of the taper, and the efficiency of the mode conversion process between the taper tip and the interconnecting waveguide.
The overlap integral is maximized for w0 of 155 nm and 100 nm at η=0.92 (0.36 dB) for the quasi-TE and -TM modes, respectively. The overlap integral sets the upper limit of coupling efficiency since additional loss is expected as the mode propagates through the taper. In the calculation of the overlap integral, the magnetic field should not be simplified as a direct function of its electric counterpart because the SOI waveguide modes are not well approximated by propagating plane waves as they are quasi-TE/TM modes. Accounting for the magnetic components of the guided modes leads to the calculation of optimal tip widths that are 20-30 nm larger than those previously reported.
A3. Constant-Loss Framework
Now that the overlap integral is maximized at the taper's tip, the tapering function needs to be optimized for maximum light coupling efficiency between the tip and the interconnecting waveguide. The range of different, monotonically increasing taper functions to connect the taper tip (width, w0) to the waveguide (width, wout) in a given taper length, L, is bounded by the two taper functions shown in
The optimal taper function w(z) that minimizes L{w} can be derived by solving the Euler-Lagrange differential equation given by Equation (4).
Assuming that α does not depend explicitly on z, which is a reasonable hypothesis under the assumption that an untapered waveguide is lossless, e.g. the taper is not within an absorbing waveguide, and that w(z) is a monotonically varying function, then simplified Equation (5) is obtained.
This implicit equation provides a clear guideline for designing an optimal taper function: the instantaneous loss at any point z within w(z) should be constant. Equation (5) establishes a general design principle that can be applied to engineer different types of photonic devices with varying shape functions. For an inverse taper, α(w,{dot over (w)}) depends on the coupling between the guided mode and the radiation modes. Given the infinite number of radiation modes, this calculation is computationally intensive. However, because at any point z along the taper only a single guided mode is supported, the instantaneous transmitted (T) and reflected (R) powers between the guided modes at z− and z+ can be tracked. This approach is complementary to computing the instantaneous power loss to the radiation modes, i.e. α=1−R−T.
A4. Results
A4.1. Power Tracking
In
A4.2. Taper Length Dependency
A4.3. Taper Robustness to Fabrication
In
In order to further demonstrate the robustness of the constant-loss taper to fabrication, 15 μm-long tapers were perturbed using an exponential autocorrelation roughness model with a standard deviation of 25 nm and a autocorrelation length of 250 nm. A total of 100 perturbation profiles were generated for each coupler and then simulated in 3D FDTD.
A4.4. Experimental Results
Inverted tapers were fabricated using a 220 nm silicon-on-insulator wafer with 3 mm buried oxide layer. The structures were defined using a hydrogen silsesquioxane (HSQ) resist with a inductively coupled, SF6-C4F8 plasma etching and covered in a 3 mm thick plasma enhanced chemical vapor deposition (PECVD) oxide. In
The measured efficiencies are reported in
B. Segmented Constant Loss Tapers
Referring to
As depicted the waveguide taper starts from an initial width W(1)=20 nm and over its length L increases in taper width to W(2)=250 nm. The resulting linear taper is then broken into a number of sections each of an intermediate width. At the transition from one waveguide section 710 to another waveguide section 720 then there are the following optical signals to consider:
Accordingly, each of these is associated with a term in the equation depicted in
Referring to
Now referring to
The inventors have also modelled the different tapers using finite difference time domain (FDTD) modeling for prior art linear and parabolic tapers together with a SEG-CLT according to an embodiment of the invention. The resulting modelled geometry for a SEG-CLT taper is depicted in
C: Extensions of Constant Loss Tapers and Segmented Constant Loss Tapers
It would be evident to one skilled in the art that whilst the embodiments of the invention have been presented based upon SOI waveguides that alternate embodiments may be implemented with the same waveguide material system and other material systems. For example, other material systems including, but not limited to, SiO2, Si3N4, SiOXNY, Si, LiNbO3, InP, InGaAsP, GaAs, AlGaAs, GaInN, AlInGaP, GaInNAs, and polymers may be employed.
It would be evident to one skilled in the art that whilst the embodiments of the invention have been presented based upon optical waveguides within the near infrared (λ=1550 nm) that alternate embodiments may be implemented at other optical wavelengths according to the waveguide material(s) from ultra-violet to far infra-red. Further embodiments of the invention may be implemented for microwave waveguides and other electromagnetic waveguides.
It would be evident to one skilled in the art that the optical waveguides exploiting embodiments of the invention may be formed through a range of techniques including, but not limited to, material composition, rib-loading, ridges, doping, ion-implantation, and ion-exchange.
It would be evident to one skilled in the art that optical waveguides exploiting X-on-insulator may include, but not be limited to, silicon, germanium, silicon nitride—silicon, intrinsic BOX layers, fabricated BOX layers, and silicon-oxide clad silicon.
Further, the embodiments of the invention may be exploited to provide short low loss waveguide tapers in order to provide enhanced small footprint bends and 90° bends. Accordingly, a SEG-CLT or CLT may be employed as depicted in
Within silicon microphotonics, optical interconnection almost exclusively occurs in plane, since Si microphotonics are based on the low-loss Si layer of an SOI substrate. As optical devices and interconnection becomes denser it becomes necessary to build efficient cross links in order to transport an optical signal across another optical signal. Currently, this is achieved through X-crossings or directional couplers. However, in many instances an optical waveguide must cross multiple waveguides to achieve the desired circuit layout which requires multiple waveguide crossings or multiple directional couplers which also move the intermediate optical signals to different optical waveguides. In contrast, the inventors have demonstrated the use of waveguide tapers, e.g. CLT tapers, to achieve optical coupling over larger distances between two optical waveguides than previously achieved. Further this optical coupling between the optical waveguides can be achieved over an intermediate optical waveguide or waveguides without physically crossing the waveguides or using multiple directional couplers.
Referring to
Within many optical circuits it is important that the circuit have equal TE and TM polarization dispersion and/or performance at least in part or fully. However, this is difficult to achieve in many instances as TE and TM polarized light travel at different velocities within the waveguide and is seen within Si microphotonic waveguides as well as those in compound semiconductors, ferroelectrics, etc. However, the inventors have established that it is possible to engineer a dispersionless taper. For example, within a SOI waveguide when the width (w) of the on-chip waveguide is smaller than the thickness of the SOI (hSOI), i.e. w<hSOI, then the effective index of the TM mode is larger than the TE mode. However, when w>hSOI the effective index of the TE mode is then larger than the TM. Thus, by carefully engineering the shape of a taper that spans waveguide widths that are both smaller and larger than hSOI it is possible to engineer the taper in such a manner that the TE and TM modes exit the taper phase matched or with a predetermined phase shift that counters the phase shift introduced by a following polarisation splitter/rotator or any other TE/TM phase shifting element.
However, in addition to the phase matching it is important that the TE and TM losses are also balanced for ensuring polarisation independent performance. Accordingly, referring to
Accordingly, in order to design a low-loss dispersionless taper, i.e. total TE losses=total TM losses, then the taper shape should be established such that when the total TE and total TM losses are calculated they are equal. As such this means limiting designs to taper shapes in which the TE and TM losses are approximately equal and then choosing those taper shapes which have a low total loss. One method to achieving such a design goal would be to use a Monte Carlo approach to generate different taper shapes which will traverse the TE/TM curves such as depicted in first and second graphs 1800A and 1800B in
It would be evident to one skilled in the art that embodiments of the invention may be derived from an iterative design and simulation process wherein an initial design is iterated in a number of segments and/or loss per segment and/or width variation per segment until a constant loss per segment transition is achieved within a predetermined tolerance.
The foregoing disclosure of the exemplary embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many variations and modifications of the embodiments described herein will be apparent to one of ordinary skill in the art in light of the above disclosure. The scope of the invention is to be defined only by the claims appended hereto, and by their equivalents.
Further, in describing representative embodiments of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.
This patent application claims the benefit of priority from U.S. Provisional Patent Application 62/163,498 filed May 19, 2015, currently pending, entitled “Methods and Systems Relating to Optical Waveguide Tapers”, the entire contents of which are incorporated herein by reference.
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