This disclosure relates generally to artificial intelligence and, more particularly, to methods, apparatus, and articles of manufacture to re-parameterize multiple head networks of an artificial intelligence model.
Machine learning models, such as neural networks, are useful tools that have demonstrated their value solving complex problems regarding object detection, pattern recognition, natural language processing, automatic speech recognition, etc. Neural networks operate, for example, using artificial neurons arranged into layers that process data from an input layer to an output layer, applying weighting values to the data during the processing of the data. Such weighting values are determined during a training process.
software/firmware/instructions distribution platform (e.g., one or more servers) to distribute software, instructions, and/or firmware (e.g., corresponding to the example machine readable instructions of
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
Artificial intelligence (AI), including machine learning (ML), deep learning (DL), and/or other artificial machine-driven logic, enables machines (e.g., computers, logic circuits, etc.) to use a model to process input data to generate an output based on patterns and/or associations previously learned by the model via a training process. For instance, the model may be trained with data to recognize patterns and/or associations and follow such patterns and/or associations when processing input data such that other input(s) result in output(s) consistent with the recognized patterns and/or associations. In general, implementing a ML/AI system involves two phases, a learning/training phase and an inference phase.
In the learning/training phase, a training algorithm is used to train a model to operate in accordance with patterns and/or associations based on, for example, training data. In general, the model includes internal parameters that guide how input data is transformed into output data, such as through a series of nodes and connections within the model to transform input data into output data. Additionally, hyperparameters are used as part of the training process to control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). Hyperparameters are defined to be training parameters that are determined prior to initiating the training process.
Once trained, the deployed model may be operated in an inference phase to process data. In the inference phase, data to be analyzed (e.g., live data) is input to the model, and the model executes to create an output. This inference phase can be thought of as the AI “thinking” to generate the output based on what it learned from the training (e.g., by executing the model to apply the learned patterns and/or associations to the live data). In some examples, input data undergoes pre-processing before being used as an input to the machine learning model. Moreover, in some examples, the output data may undergo post-processing after it is generated by the AI model to transform the output into a useful result (e.g., a display of data, an instruction to be executed by a machine, etc.).
In some examples, output of the deployed model may be captured and provided as feedback. By analyzing the feedback, an accuracy of the deployed model can be determined. If the feedback indicates that the accuracy of the deployed model is less than a threshold or other criterion, training of an updated model can be triggered using the feedback and an updated training data set, hyperparameters, etc., to generate an updated, deployed model.
Different types of training may be performed based on the type of ML/AI model and/or the expected output. For example, supervised training uses inputs and corresponding expected (e.g., labeled) outputs to select parameters (e.g., by iterating over combinations of select parameters) for the ML/AI model that reduce model error. As used herein, labelling refers to an expected output of the machine learning model (e.g., a classification, an expected output value, etc.). In supervised training, labels are generally applied to data by a human. Despite the ease of collecting large amounts of data, research on unsupervised training is being actively conducted because of the large burden involved with labeling data. Unsupervised training (e.g., used in deep learning, a subset of machine learning, etc.) involves inferring patterns from inputs to select parameters for the ML/AI model (e.g., without the benefit of expected (e.g., labeled) outputs).
In some examples, semi-supervised training may be performed. Semi-supervised training, also referred to as semi-supervised learning (SSL), combines pretraining an ML/AI model and finetuning the ML/AI model into a single training pipeline. SSL involves utilizing a large amount of unlabeled data and a small amount of labeled data (compared to the unlabeled data) together to select parameters for an ML/AI model. As such, SSL is favored by AI practitioners because ML/AI models trained via SSL can produce accurate results with less computationally intensive training compared to unsupervised learning while also avoiding as large of a labeling burden as supervised training (e.g., since less labeled data is utilized in SLL).
One technique to perform SSL is referred to as pseudo-labeling. Pseudo-labeling involves generating an artificial label for unlabeled data. To generate artificial labels for the large amount of unlabeled data used in SSL, an ML/AI model is trained using a small amount of labeled data and then used to classify the unlabeled data. These classifications are captured and assigned to the unlabeled data as artificial labels for the unlabeled data. Such artificial labels may be referred to as pseudo-labels. Subsequently, the pseudo-labeled data and the labeled data can be used together to train (e.g., retrain, further train, etc.) the ML/AI model.
Another technique to perform SSL is referred to as consistency regularization. Consistency regularization involves utilizing unlabeled data to find a manifold (e.g., pattern) to which the training dataset subscribes. For example, consistency regularization involves reducing the loss (e.g., difference) between training data and perturbed (e.g., augmented) training data. Consistency regularization is predicated on the idea that realistic perturbations to input data should not change the classification generated by an ML/AI model. Consistency regularization can utilize a weakly augmented version (e.g., a small adjustment relative to an original image) of unlabeled data and a strongly augmented version (e.g., a large adjustment relative to the original image) of the unlabeled data. Weak augmentations of unlabeled data may be imperceptible to humans whereas strong augmentations of unlabeled data may be more perceptible.
Modern ML/AI models (e.g., neural networks) suffer from an over-confidence characteristic. As such, in SSL, modern ML/AI models exclude correct pseudo-labels during early training (e.g., during the first several epochs of training) or include incorrect pseudo-labels during later training (e.g., during the later several epochs) when the ML/AI models are matured (e.g., more fully trained). Examples disclosed herein introduce apre-hoc calibration method for SSL that leverages ensembles only at the head portion of a network to resolve the over-confidence characteristic of modern ML/AI models. Techniques to solve the over-confidence characteristic can be categorized as pre-hoc and post-hoc calibrations of predictive uncertainty. As used herein, pre-hoc calibration refers to calibration of the predictive uncertainty of an ML/AI model by the ML/AI model. As used herein, post-hoc calibration refers to post-processing of the predictive uncertainty of an ML/AI model by an external calibrator.
In ML/AI applications, a model may be represented as a head network and a backbone network. A backbone network refers to the portion of a network that extracts features from an input sample and encodes the features into a feature vector. A head network refers to the portion of a network that determines an output of the network. For example, a head network may be a classification head network responsible for classifying an input sample. Another example of a head network is a regression head network which may be responsible for modeling an input dataset. Yet another example of a head network is a prediction head network which may be responsible for predicting an output (e.g., a next event, a next sample, etc.) given an input sample.
In ML/AI applications, ensembling refers to implementing multiple instances of at least some portions of a network and utilizing some combination of the outputs of the multiple instances to generate an output for the network. For example, ensembling may be implemented at the layer level, where multiple instances of each layer of a network are trained. In examples disclosed herein, by exploiting ensembles at the head portion of a network (e.g., exclusively at the head portion and not at the backbone portion), disclosed methods, apparatus, and articles of manufacture maintain nearly the same computational cost during training as a traditional network. Furthermore, to avoid architectural changes when employing ensembles, examples disclosed herein incorporate structural reparameterization, which allows models that incorporate complex non-linear topology during the training phase to be restructured (e.g., into a single fully connected (FC) layer) during the inference phase. For example, structural reparameterization utilizes different model architectures at training and inference time while maintaining computational equivalence. Example structural reparameterization disclosed herein not only improves performance with non-linear operators during training but also prevents additional overhead through an equivalent transformation during deployment.
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In some examples, the interface circuitry 202 accesses the labeled data 214 from publicly available datasets. In additional or alternative examples, a developer of the AI model(s) trained by the model training circuitry 102 may generate the labeled data 214. In some examples, the interface circuitry 202 accesses the unlabeled data 216 from publicly available datasets. In additional or alternative examples, the interface circuitry 202 accesses the unlabeled data 216 from a camera and/or image sensor in communication with the model training circuitry 102. Example publicly available datasets include the CIFAR-10 dataset, the CIFAR-90-M dataset, the CIFAR-100 dataset, the ImageNet dataset, the Tiny-ImageNet dataset, the SVHN dataset, the STL10 dataset, the Euro-SAT dataset, the Euro-SAT-9-M dataset, the Tissue MNIST dataset, and the Semi-Ayes dataset. In some examples, the interface circuitry 202 is instantiated by programmable circuitry executing interfacing instructions and/or configured to perform operations such as those represented by the flowchart(s) of
In some examples, the model training circuitry 102 includes means for interfacing. For example, the means for interfacing may be implemented by the interface circuitry 202. In some examples, the interface circuitry 202 may be instantiated by programmable circuitry such as the example programmable circuitry 812 of
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In the example first training phase, after an AI model has processed the weakly augmented version(s) of the labeled data 214, the training control circuitry 204 computes a loss value for the AI model according to Equation 1 below.
Equation 1 is an example of a cross-entropy loss function. When implementing Equation 1, the training control circuitry 204 computes a cross-entropy loss value, Is, by summing the cross-entropy loss, H, for each head network, k, over a batch of the labeled data 214. By implementing example Equation 1, the training control circuitry 204 maintains consistency regularization by minimizing the distance between two output distributions that come from weak and strong augmentation pairs of the same sample. In the example of Equation 1, there are K head networks in an AI model (e.g., k=[1, K]) and a batch of the labeled data 214 includes B samples (e.g., b=[1, B]). In the example of Equation 1, xb, represents a sample of the labeled data 214, yb represents a label for a sample of the labeled data 214, and pwk(xb) represents the output of a head network, k, for a weakly augmented (w) sample, xb, of the labeled data 214. In examples disclosed herein, pwk(xb) is implemented according to Equation 2 below.
p
w
k(xb)=SoftMax(hwk(xb)) Equation 2
In the example of Equation 2, SoftMax represents the softmax function which takes an input vector of N real numbers and normalizes the input vector into a probability distribution of N probabilities proportional to the exponentials of the input numbers. In the example of Equation 2, hwk(xb) represents the vector output of a head network, k, for a weakly augmented (w) sample, xb, of the labeled data 214. In the example of Equation 2, hwk(xb) can be defined as hwk(xb)=fk((g(Tw(xb)))) where fk( ) represents a head network, g( ) represents a feature encoder, and Tw( ) represents a weak augmentation operator.
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Equation 3 is an example of an unsupervised loss function. When implementing Equation 3, the training control circuitry 204 computes an unsupervised loss value, lu, by summing the cross-entropy loss, H, for each head network, k, over a batch of the unlabeled data 216 when the predictive uncertainty of a pseudo-label is below a threshold (e.g., the probability associated with a classification of the AI model is greater than a threshold). By implementing example Equation 3, the training control circuitry 204 encourages an AI model to confidently classify unlabeled data (e.g., classify unlabeled data with a high probability value).
In the example of Equation 3, p represents a ratio of the unlabeled data 216 to the labeled data 214, qw(ub) represents a logit vector generated by a head network, k, for a weakly augmented (w) sample, ub, of the unlabeled data 216, {circumflex over (q)}w(ub) represents a pseudo-label for the weakly augmented (w) sample, ub, of the unlabeled data 216, and psk(ub) represents the output of a head network, k, for a strongly augmented (s) sample, ub, of the unlabeled data 216. Additionally, in the example of Equation 3,1( ) represents an indicator function that indicates that the cross-entropy loss, H, should be computed when the maximum value of the logit vector, qw(ub), satisfies (e.g., is greater than) a threshold value. In examples disclosed herein, qw(ub) is implemented according to Equation 4 below.
In the example of Equation 4, hwk(ub) represents the vector output of a head network, k, for a weakly augmented (w) sample, ub, of the unlabeled data 216. In the example of Equation 2, hwk(ub) can be defined as hwk=fk((g(Tw(ub)))) where fk( ) represents a head network, go represents a feature encoder, and Tw( ) represents a weak augmentation operator. In examples disclosed herein, {circumflex over (q)}w(ub) is implemented according to Equation 5 below.
{circumflex over (q)}
w(ub)=argmax(qw(ub)) Equation 5
In the example of Equation 5, argmax represents the argmax function which outputs the argument(s) that provide the maximum value of an input function. In examples disclosed herein, psk(ub) is implemented according to Equation 6 below.
p
s
k(ub)=SoftMax(hsk(ub)) Equation 6
In the example of Equation 6, hsk(ub) represents the vector output of a head network, k, for a strongly augmented (s) sample, ub, of the unlabeled data 216. In the example of Equation 2, his' (ub) can be defined as hsk(ub)=fk((g(Ts(ub)))) where fk( ) represents a head network, go represents a feature encoder, and Ts( ) represents a strong augmentation operator.
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In some examples, the model training circuitry 102 includes means for controlling training. For example, the means for controlling training may be implemented by the training control circuitry 204. In some examples, the training control circuitry 204 may be instantiated by programmable circuitry such as the example programmable circuitry 812 of
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In some examples, the model training circuitry 102 includes means for encoding features. For example, the means for encoding features may be implemented by the feature encoder circuitry 206. In some examples, the feature encoder circuitry 206 may be instantiated by programmable circuitry such as the example programmable circuitry 812 of
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In some examples, the model training circuitry 102 includes means for executing head networks. For example, the means for executing head networks may be implemented by the head network execution circuitry 2081-208K. In some examples, the head network execution circuitry 2081-208K may be instantiated by programmable circuitry such as the example programmable circuitry 812 of
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{tilde over (g)}=diag(γ)diag({circumflex over (σ)})−1((Wz+b)−{circumflex over (μ)})+β Equation 7(a)
{tilde over (g)}=diag(γ)diag({circumflex over (σ)})−1Wz+diag(γ)diag({circumflex over (σ)})−1(b−{circumflex over (μ)})+β Equation 7(b)=
{tilde over (g)}=W*z+13*β* Equation 7(c)
In Equations 7(a)-7(c), W represents a weight matrix of an FC layer (e.g., W∈C×C) b represents a bias vector of the FC layer (e.g., b∈
C), and z represents an input vector to the FC layer where the input vector, z, includes a C-dimensional channel. Additionally, in Equations 7(a)-7(c), {circumflex over (μ)} (e.g., {circumflex over (μ)}∈
C), & (e.g., {circumflex over (σ)}∈
C), γ (e.g., γ∈
C), and β(e.g., β∈
C) represent running statistics and learnable parameters of a BN layer.
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Equation 8 represents the average operator for an input over n samples. Equation 9 represents n fully connected layers yi having an input x with weights Wi and biases bi. Equation 10 converts the n fully connected layers yi and the average operator
to a linear operator for an input x. In the illustrated example of
In some examples, the model training circuitry 102 includes means for re-parameterizing. For example, the means for re-parameterizing may be implemented by the structural reparameterization circuitry 210. In some examples, the structural reparameterization circuitry 210 may be instantiated by programmable circuitry such as the example programmable circuitry 812 of
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In additional or alternative examples, the example datastore 212 may be implemented by one or more mass storage devices such as hard disk drive(s), compact disk drive(s), digital versatile disk drive(s), solid-state disk drive(s), etc. While in the illustrated example the datastore 212 is illustrated as a single database, the datastore 212 may be implemented by any number and/or type(s) of databases. Furthermore, the data stored in the datastore 212 may be in any data format such as, for example, binary data, comma delimited data, tab delimited data, structured query language (SQL) structures, etc.
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As described above, at inference time, the structural reparameterization circuitry 210 re-parameterizes the multiple head networks of an AI model into a single fully connected layer. In the example of
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Tables 1-3 illustrate further performance benefits achieved by examples disclosed herein. Table 1 illustrates unified SSL benchmark (USB) results for computer vision (CS) with the top-1 model accuracy when incorporating examples disclosed herein into FixMatch, AdaMatch, and SimMatch. All results are obtained by taking an average of over 3 seeds. USB results for CV may be referred to as USB-CV results.
Table 1 illustrates the accuracies of some SSL algorithms reported in USB-CV, the accuracies of those SSL algorithms when implementing examples disclosed herein (identified by +EnsembleHead), and the gains over baselines. USB-CV provides five CV datasets from different domains: CIFAR-100, STL-10, Euro-SAT, TissueMNIST, and Semi-Ayes. The gain, averaged across datasets, shows that examples disclosed herein provide AI models with an accuracy gain over other SSL algorithms. For example, examples disclosed herein provide a 2.02% accuracy gain over FixMatch, examples disclosed herein provide a 1.04% accuracy gain over AdaMatch, and examples disclosed herein provide a 0.73% accuracy gain over SimMatch.
Table 1 also illustrates that examples disclosed herein provide an additional model accuracy gain for the SSL algorithms equipped with the post-hoc calibration as examples disclosed herein are orthogonal to post-hoc calibration techniques. Table 2 illustrates experimental results in extremely low labeled data regimes where the number of labels per class is set to one for all datasets.
Table 2 illustrates additional experiment results for datasets including extremely small labeled data. Unlike USB-CV, which includes at least two labeled data samples per class, Table 2 illustrates experimental results for classification on datasets including only one labeled data sample per class (e.g., a one-shot transfer case). Overall, examples disclosed herein (identified as EnsembleHead) provide a much larger gain compared to the original USB-CV benchmark in the extremely small labeled data regime. For all datasets except TissueMNIST, the accuracy gains achieved by incorporating examples disclosed herein are greater in the extremely small labeled data regime. As such, examples disclosed herein improve the quality of unsupervised learning. Table 3 illustrates experimental results when incorporating examples disclosed herein (identified as EnsembleHead) into FixMatch on the CIFAR-90-M dataset and the Euro-SAT-9-M dataset, where the CIFAR-90-M dataset and the Euro-SAT-9-M dataset are artificially generated to simulate the class distribution mismatch like the STL-10 dataset.
Table 3 illustrates that examples disclosed herein provide an accuracy gain on all class distributional mismatched datasets. Class distributional mismatched datasets are more common in the practical uses of SSL because matching class distribution between labeled and unlabeled data requires paying data cleansing costs additionally. In Table 3, the CIFAR-90-M dataset and the Euro-SAT-9-M dataset are synthesized from the CIFAR-100 dataset and the Euro-SAT dataset, respectively to simulate class distributional mismatched datasets. In Table 3, the labeled data of the CIFAR-90-M dataset is prepared with 90 classes randomly chosen from the CIFAR-100 dataset and the other 10 classes of the CIFAR-100 dataset are only included in the unlabeled data. Additionally, in Table 3, the labeled data of the Euro-SAT-9-M dataset is prepared by randomly choosing 9 out of 10 classes of the Euro-SAT data for labeled data. In both the CIFAR-90-M dataset and the Euro-SAT-9 dataset as well as in data settings including a different number of labeled data, examples disclosed herein provide more than 1.45% model accuracy gains.
While an example manner of implementing the model training circuitry 102 of
Flowchart(s) representative of example machine readable instructions, which may be executed by programmable circuitry (e.g., instructions to cause programmable circuitry) to implement and/or instantiate the model training circuitry 102 of
The program may be embodied in instructions (e.g., software and/or firmware) stored on one or more non-transitory computer readable and/or machine readable storage medium such as cache memory, a magnetic-storage device or disk (e.g., a floppy disk, a Hard Disk Drive (HDD), etc.), an optical-storage device or disk (e.g., a Blu-ray disk, a Compact Disk (CD), a Digital Versatile Disk (DVD), etc.), a Redundant Array of Independent Disks (RAID), a register, ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., Random Access Memory (RAM) of any type, etc.), and/or any other storage device or storage disk. The instructions of the non-transitory computer readable and/or machine readable medium may program and/or be executed by programmable circuitry located in one or more hardware devices, but the entire program and/or parts thereof could alternatively be executed and/or instantiated by one or more hardware devices other than the programmable circuitry and/or embodied in dedicated hardware. The machine readable instructions may be distributed across multiple hardware devices and/or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and/or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, the non-transitory computer readable storage medium may include one or more mediums. Further, although the example program is described with reference to the flowchart(s) illustrated in
The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as portion(s) of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices, disks and/or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and/or stored on separate computing devices, wherein the parts when decrypted, decompressed, and/or combined form a set of computer-executable and/or machine executable instructions that implement one or more functions and/or operations that may together form a program such as that described herein.
In another example, the machine readable instructions may be stored in a state in which they may be read by programmable circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and/or the corresponding program(s) can be executed in whole or in part. Thus, machine readable, computer readable and/or machine readable media, as used herein, may include instructions and/or program(s) regardless of the particular format or state of the machine readable instructions and/or program(s).
The machine readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: C, C++, Java, C #, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.
As mentioned above, the example operations of
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more,” and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
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In the illustrated example of
The programmable circuitry platform 800 of the illustrated example includes programmable circuitry 812. The programmable circuitry 812 of the illustrated example is hardware. For example, the programmable circuitry 812 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The programmable circuitry 812 may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the programmable circuitry 812 implements the example training control circuitry 204, the example feature encoder circuitry 206, the example head network execution circuitry 2081-208K, and the example structural reparameterization circuitry 210.
The programmable circuitry 812 of the illustrated example includes a local memory 813 (e.g., a cache, registers, etc.). The programmable circuitry 812 of the illustrated example is in communication with main memory 814, 816, which includes a volatile memory 814 and a non-volatile memory 816, by a bus 818. The volatile memory 814 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory 816 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 814, 816 of the illustrated example is controlled by a memory controller 817. In some examples, the memory controller 817 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data going to and from the main memory 814, 816.
The programmable circuitry platform 800 of the illustrated example also includes interface circuitry 820. The interface circuitry 820 may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface.
In the illustrated example, one or more input devices 822 are connected to the interface circuitry 820. The input device(s) 822 permit(s) a user (e.g., a human user, a machine user, etc.) to enter data and/or commands into the programmable circuitry 812. The input device(s) 822 can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and/or a voice recognition system.
One or more output devices 824 are also connected to the interface circuitry 820 of the illustrated example. The output device(s) 824 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry 820 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.
The interface circuitry 820 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network 826. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc. In this example, the interface circuitry 820 implements the example interface circuitry 202.
The programmable circuitry platform 800 of the illustrated example also includes one or more mass storage discs or devices 828 to store firmware, software, and/or data. Examples of such mass storage discs or devices 828 include magnetic storage devices (e.g., floppy disk, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and/or solid-state storage discs or devices such as flash memory devices and/or SSDs. In this example, the one or more mass storage discs or devices 828 implement the datastore 212. As described above, the datastore 212 may include the labeled data 214, the unlabeled data 216, the model parameters 218, and the pseudo-labeled data 220.
The machine readable instructions 832, which may be implemented by the machine readable instructions of
The cores 902 may communicate by a first example bus 904. In some examples, the first bus 904 may be implemented by a communication bus to effectuate communication associated with one(s) of the cores 902. For example, the first bus 904 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 904 may be implemented by any other type of computing or electrical bus. The cores 902 may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry 906. The cores 902 may output data, instructions, and/or signals to the one or more external devices by the interface circuitry 906. Although the cores 902 of this example include example local memory 920 (e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor 900 also includes example shared memory 910 that may be shared by the cores (e.g., Level 2 (L2 cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory 910. The local memory 920 of each of the cores 902 and the shared memory 910 may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory 814, 816 of
Each core 902 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 902 includes control unit circuitry 914, arithmetic and logic (AL) circuitry 916 (sometimes referred to as an ALU), a plurality of registers 918, the local memory 920, and a second example bus 922. Other structures may be present. For example, each core 902 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry 914 includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core 902. The AL circuitry 916 includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core 902. The AL circuitry 916 of some examples performs integer based operations. In other examples, the AL circuitry 916 also performs floating-point operations. In yet other examples, the AL circuitry 916 may include first AL circuitry that performs integer-based operations and second AL circuitry that performs floating-point operations. In some examples, the AL circuitry 916 may be referred to as an Arithmetic Logic Unit (ALU).
The registers 918 are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry 916 of the corresponding core 902. For example, the registers 918 may include vector register(s), SIMD register(s), general-purpose register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers 918 may be arranged in a bank as shown in
Each core 902 and/or, more generally, the microprocessor 900 may include additional and/or alternate structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged/common mesh stops (CMSs), one or more shifters (e.g., barrel shifter(s)) and/or other circuitry may be present. The microprocessor 900 is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.
The microprocessor 900 may include and/or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and/or efficiently than can be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs such as those discussed herein. A GPU, DSP and/or other programmable device can also be an accelerator. Accelerators may be on-board the microprocessor 900, in the same chip package as the microprocessor 900 and/or in one or more separate packages from the microprocessor 900.
More specifically, in contrast to the microprocessor 900 of
In the example of
In some examples, the binary file is compiled, generated, transformed, and/or otherwise output from a uniform software platform utilized to program FPGAs. For example, the uniform software platform may translate first instructions (e.g., code or a program) that correspond to one or more operations/functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions that correspond to the one or more operations/functions in an HDL. In some such examples, the binary file is compiled, generated, and/or otherwise output from the uniform software platform based on the second instructions. In some examples, the FPGA circuitry 1000 of
The FPGA circuitry 1000 of
The FPGA circuitry 1000 also includes an array of example logic gate circuitry 1008, a plurality of example configurable interconnections 1010, and example storage circuitry 1012. The logic gate circuitry 1008 and the configurable interconnections 1010 are configurable to instantiate one or more operations/functions that may correspond to at least some of the machine readable instructions of
The configurable interconnections 1010 of the illustrated example are conductive pathways, traces, vias, or the like that may include electrically controllable switches (e.g., transistors) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 1008 to program desired logic circuits.
The storage circuitry 1012 of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry 1012 may be implemented by registers or the like. In the illustrated example, the storage circuitry 1012 is distributed amongst the logic gate circuitry 1008 to facilitate access and increase execution speed.
The example FPGA circuitry 1000 of
Although
It should be understood that some or all of the circuitry of
In some examples, some or all of the circuitry of
In some examples, the programmable circuitry 812 of
A block diagram illustrating an example software distribution platform 1105 to distribute software such as the example machine readable instructions 832 of
From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that re-parameterize multiple head networks of an artificial intelligence model into a single fully connected layer. Additionally, example systems, apparatus, articles of manufacture, and methods have been disclosed that improve (e.g., enhance) the calibration of predictive uncertainty through deep ensembles and structural reparameterization so that model training is leveraged by high-confident samples (e.g., through Equation 3). Furthermore, examples disclosed herein exploit ensembles of non-linear paths at training time, but at inference time, examples disclosed herein transform (e.g., via structural reparameterization) the non-linear paths into a single linear classifier. Disclosed systems, apparatus, articles of manufacture, and methods improve the efficiency of using a computing device by improving classification accuracy of an AI model through the use of non-linear layers at training time and re-parameterizing the non-linear layers at inference time to reduce the computational burden of implementing the AI model. Disclosed systems, apparatus, articles of manufacture, and methods are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device.
Disclosed pre-hoc calibration for SSL can applied to any SSL algorithm. Example systems, apparatus, articles of manufacture, and methods disclosed herein achieve state-of-the-art performance on SSL. Examples disclosed herein can also be applied to supervised learning and/or unsupervised learning. Additionally, examples disclosed herein alter training cost by negligible amounts and do not increase computational cost during deployment. Examples disclosed herein can be implemented in computer vision platforms to allow end-users to build high-quality vision AI models when large amounts of labeled data is not available.
Example methods, apparatus, systems, and articles of manufacture to re-parameterize multiple head networks of an artificial intelligence model are disclosed herein. Further examples and combinations thereof include the following:
Example 1 includes an apparatus to re-parameterize multiple head networks of an artificial intelligence (AI) model, the apparatus comprising interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to train an AI model using labeled data and pseudo-labeled data, the AI model including multiple head networks, and after the AI model has been trained, re-parameterize the multiple head networks of the AI model into a fully connected layer without re-parameterizing other portions of the AI model.
Example 2 includes the apparatus of example 1, wherein the programmable circuitry is to generate, with the AI model, the pseudo-labeled data by classifying unlabeled data with the multiple head networks.
Example 3 includes the apparatus of any of examples 1 or 2, wherein the programmable circuitry is to re-parameterize the multiple head networks into multiple fully connected layers, and re-parameterize the multiple fully connected layers and an average operator into the fully connected layer.
Example 4 includes the apparatus of any of examples 1, 2, or 3, wherein the fully connected layer is a first fully connected layer, respective head networks of the multiple head networks include multiple non-linear layers, an identity layer, an average operator, and a second fully connected layer, and respective non-linear layers of the multiple non-linear layers include a third fully connected layer and a batch normalization layer.
Example 5 includes the apparatus of example 4, wherein to re-parameterize the respective head networks of the multiple head networks, the programmable circuitry is to re-parameterize the multiple non-linear layers of the respective head networks into multiple fully connected layers, re-parameterize the identity layer of the respective head networks into a fourth fully connected layer, and re-parameterize the multiple fully connected layers, the fourth fully connected layer, the average operator, and the second fully connected layer into a fifth fully connected layer.
Example 6 includes the apparatus of example 5, wherein to re-parameterize the identity layer of the respective head networks into the fourth fully connected layer, the programmable circuitry is to define a weight matrix and a bias vector for the fourth fully connected layer, the weight matrix including an identity matrix, the bias vector including a zero vector.
Example 7 includes the apparatus of any of examples 1, 2, 3, or 4, wherein the programmable circuitry is to determine whether the AI model has been trained for a threshold number of epochs.
Example 8 includes a non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least train an artificial intelligence (AI) model using labeled data and pseudo-labeled data, the AI model including multiple head networks, and after the AI model has been trained, re-parameterize the multiple head networks of the AI model into a fully connected layer without re-parameterizing other portions of the AI model.
Example 9 includes the non-transitory machine readable storage medium of example 8, wherein the instructions cause the programmable circuitry to generate the pseudo-labeled data by classifying unlabeled data with the multiple head networks.
Example 10 includes the non-transitory machine readable storage medium of any of examples 8 or 9, wherein the instructions cause the programmable circuitry to re-parameterize the multiple head networks into multiple fully connected layers, and re-parameterize the multiple fully connected layers and an average operator into the fully connected layer.
Example 11 includes the non-transitory machine readable storage medium of any of examples 8, 9, or 10, wherein the fully connected layer is a first fully connected layer, respective head networks of the multiple head networks include multiple non-linear layers, an identity layer, an average operator, and a second fully connected layer, and respective non-linear layers of the multiple non-linear layers include a third fully connected layer and a batch normalization layer.
Example 12 includes the non-transitory machine readable storage medium of example 11, wherein to re-parameterize the respective head networks of the multiple head networks, the instructions cause the programmable circuitry to re-parameterize the multiple non-linear layers of the respective head networks into multiple fully connected layers, re-parameterize the identity layer of the respective head networks into a fourth fully connected layer, and re-parameterize the multiple fully connected layers, the fourth fully connected layer, the average operator, and the second fully connected layer into a fifth fully connected layer.
Example 13 includes the non-transitory machine readable storage medium of example 12, wherein to re-parameterize the identity layer of the respective head networks into the fourth fully connected layer, the instructions cause the programmable circuitry to define a weight matrix and a bias vector for the fourth fully connected layer, the weight matrix including an identity matrix, the bias vector including a zero vector.
Example 14 includes the non-transitory machine readable storage medium of any of examples 8, 9, 10, or 11, wherein the instructions cause the programmable circuitry to determine whether the AI model has been trained for a threshold number of epochs.
Example 15 includes a method to re-parameterize multiple head networks of an artificial intelligence (AI) model, the method comprising training, by executing an instruction with programmable circuitry, the AI model using labeled data and pseudo-labeled data, the AI model including multiple head networks, and after the AI model has been trained, re-parameterizing, by executing an instruction with the programmable circuitry, the multiple head networks of the AI model into a fully connected layer without re-parameterizing other portions of the AI model.
Example 16 includes the method of example 15, further including generating, with the AI model, the pseudo-labeled data by classifying unlabeled data with the multiple head networks.
Example 17 includes the method of any of examples 15 or 16, further including re-parameterizing the multiple head networks into multiple fully connected layers, and re-parameterizing the multiple fully connected layers and an average operator into the fully connected layer.
Example 18 includes the method of any of examples 15, 16, or 17, wherein the fully connected layer is a first fully connected layer, respective head networks of the multiple head networks include multiple non-linear layers, an identity layer, an average operator, and a second fully connected layer, and respective non-linear layers of the multiple non-linear layers include a third fully connected layer and a batch normalization layer.
Example 19 includes the method of example 18, further including re-parameterizing the respective head networks of the multiple head networks by re-parameterizing the multiple non-linear layers of the respective head networks into multiple fully connected layers, re-parameterizing the identity layer of the respective head networks into a fourth fully connected layer, and re-parameterizing the multiple fully connected layers, the fourth fully connected layer, the average operator, and the second fully connected layer into a fifth fully connected layer.
Example 20 includes the method of example 19, further including re-parameterizing the identity layer of the respective head networks into the fourth fully connected layer by defining a weight matrix and a bias vector for the fourth fully connected layer, the weight matrix including an identity matrix, the bias vector including a zero vector.
Example 21 includes the method of any of examples 15, 16, 17, or 18, further including determining whether the AI model has been trained for a threshold number of epochs.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.