Patent Application
20150093914
The present disclosure generally relates to methods for fabricating integrated circuits. More particularly, the presented disclosure relates to methods for depositing aluminum oxide layers over germanium substrates in the fabrication of integrated circuits.
The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode formed over a semiconductive substrate, and spaced apart source and drain electrodes within the substrate between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductive substrate between the source and drain electrodes.
The gain of an MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility of the majority carrier in the transistor channel. The current carrying capability and hence the performance of an MOS transistor is proportional to the mobility of the majority carrier in the channel. With the continued scaling of modern MOSFETs, transistors fabricated using conventional bulk silicon substrates are approaching their fundamental limits with regard to carrier mobility. Thus, various other substrate materials have been investigated. One such material, germanium (Ge), exhibits carrier mobilities that are approximately two to four times higher than that of silicon.
In Ge-based MOSFETs, the “quality” of the MOS interface (i.e., the interface between the Ge substrate and the gate electrode) is one of several factors that allow for the realization of the above-noted improved carrier mobility in the channel. As conventionally used in the art, the “quality” of the MOS interface refers to the diffusional stability of the interface, as well as the adhesion of the interfacial layers. In order to promote interfacial stability and adhesion, an interfacial layer (IL) is conventionally provided between the Ge substrate and the first layer of the gate electrode, for example a high-k layer (i.e., having a dielectric constant greater than the dielectric constant of silicon dioxide). While various interfacial layers have been investigated, germanium oxide (GeOx) is the most widely used material due to its ease of growth on Ge (thermal oxidation in an oxidizing environment, for example) as well as its ability to adhere to both Ge and various high-k materials, which themselves are often metal oxides (for example, Al2O3 or HfO2). In order to increase the carrier mobility performance of the transistor, it is desirable to provide an IL that is as thin as possible—that is, while the presence of the IL aides in stability and adhesion at the MOS interface, the IL detrimentally contributes to an increase in gate capacitance, which may harm transistor performance.
Atomic layer deposition (ALD) is commonly used to deposit the high-k dielectric layer over the thin GeOx interfacial layer. ALD requires several oxidation steps (“cycles”), where the deposited metal is oxidized to form the desired metal oxide, such as Al2O3. These oxidation steps, however, may undesirably result in the re-growth of additional GeOx, which as noted above may harm transistor performance. Attempts have been made in the prior art to reduce the level of oxidation during these cycles, or to reduce the total number of cycles (thereby creating a thinner dielectric layer), in an effort to prevent GeOx re-growth. Reduced levels of oxidation, however, detrimentally affect the nucleation (i.e., ordered bonding) of the deposited metal, which in turn may result in incomplete chemical bonding between the GeOx layer and the high-k layer. Incomplete chemical bonding between the layers may result in the formation of electron “traps.” As known in the art, these “traps” are localized areas within a semiconductor material that can attract or “trap” free electrical carriers. Traps may be caused by un-terminated or dangling electrochemical bonds at the interface of dissimilar materials such as GeOx and Al2O3. These unwanted energy traps may impair the electrical properties of material near the GeOx/Al2O3 interface and may reduce the performance of the transistor by increasing the density of energy states at the interface (Dit). Furthermore, reducing the number of oxidation cycles, thereby creating a thinner dielectric layer, may result in gate current “leakage” (Ig), which reduces the stability of the transistor.
Accordingly, it is desirable to provide improved methods for fabricating integrated circuits using Ge-based semiconductor substrates. Additionally, it is desirable to provide such methods that include steps for the deposition of an aluminum oxide dielectric layer that do not substantially contribute to the re-growth of the germanium oxide interfacial layer, that do not substantially contribute to an increase in interface state density (Dit), and that do not substantially contribute to increased gate current leakage (Ig). Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
Various exemplary methods for fabricating integrated circuits are provided herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a first oxygen-containing precursor. The second ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a second oxygen-containing precursor.
In another exemplary embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising an oxygen-containing precursor at a first level. The second ALD process is performed subsequent to the first ALD process and includes exposing the semiconductor substrate to the first gaseous precursor comprising aluminum and exposing the semiconductor substrate to the second gaseous precursor comprising the oxygen-containing precursor at a second level that is less than the first level.
The various embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
Embodiments of the present disclosure are directed to methods for depositing an aluminum oxide layer, which functions as a gate insulation layer for a gate electrode structure of an MOSFET, over germanium substrates using ALD in the fabrication of integrated circuits. In some embodiments of the present disclosure, GeOx re-growth is limited during ALD of the Al2O3 layer by using two (or more) different oxygen precursors in sequence during the various “cycles” of the ALD process. For example, during the first several deposition cycles a first oxygen precursor is employed, and during subsequent deposition cycles a second oxygen precursor is employed. The selection of various first and second oxygen precursors may be used in order to “tune” the qualities of the deposited aluminum oxide layer (for example, lower GeOx re-growth versus lower Dit) to a specific application, as will be described in greater detail below. In other embodiments of the present disclosure, GeOx re-growth is limited during ALD of the Al2O3 layer by continuously decreasing the level of oxidation in the ALD process in each successive cycle. As such, the level of oxidation becomes a function of film thickness growth. For example, the initial deposition cycles are performed with a relatively high oxidation level in order to promote proper nucleation at the interface so that the bonding between the dissimilar interface materials (GeOx/Al2O3) is as strong as possible. Thereafter, subsequent cycles are performed with reduced oxidation levels as the Al2O3 layer builds on itself in order to minimize any GeOx re-growth. Methods in accordance with the present disclosure are easily integrated into existing integrated circuit fabrication process flows, and are suitable for use in both gate-first and gate-last process flows.
For the sake of brevity, conventional techniques related to semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor based transistors are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
The techniques and technologies described herein may be utilized to fabricate MOS transistor devices, including NMOS transistor devices, PMOS transistor devices, and CMOS transistor devices. In particular, the process steps described here may be utilized in conjunction with any semiconductor device fabrication process that forms gate structures for transistors. Although the term “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout this disclosure to refer to any semiconductor device that includes a conductive gate electrode that is positioned over a high-k gate dielectric or other dielectric material, which in turn is positioned over a germanium-based semiconductor substrate.
As noted above, while the presence of a GeOx interfacial layer is desirable to achieve a high quality MOS interface, if too thick the GeOx material undesirably increases the gate capacitance of a transistor formed thereof. An increased gate capacitance degrades the mobility of the carriers in the substrate 104. As such, it is desirable to minimize the thickness of the oxide layer 107 to a thickness 122 of about 5 nm or less, such as about 1 nm or less, for example about 5 angstroms (Å) or less. As such, prior to the deposition of the high-k dielectric layer, the substrate 104 is subjected to an etching or “cleaning” process in order to reduce the thickness of layer 107 to a desirable thickness 122 as noted above. This etching or cleaning process may be performed using any wet or dry etching chemistry known in the art that is selective to the GeOx material.
Subsequent to the initial substrate etch, a high-k dielectric material layer is formed over the interfacial GeOx layer 107 as a preliminary step in forming an MOSFET on the substrate 104. In one embodiment, the high-k dielectric material is aluminum oxide (Al2O3), which may be deposited using ALD. Referring now to
The growth of material layers by ALD includes repeating the following characteristic four steps: (1) Exposure of the first precursor in an energized state, typically an organometallic compound, such as aluminum. (2) Purge or evacuation of the reaction chamber to remove the non-reacted precursors and the gaseous reaction by-products. (3) Exposure of the second precursor in an energized state to activate the surface again for the reaction thereof with the first precursor. (4) Purge or evacuation of the reaction chamber. Each reaction cycle adds a given amount of material to the surface, referred to as the growth per cycle. To grow a material layer, reaction cycles are repeated as many times as required for the desired film thickness. One cycle may take about from about 0.5 seconds to a few seconds to complete, and may deposit between about 0.1 angstroms (Å) and about 3 Å of film thickness.
Referring now particularly to the ALD of Al2O3 as illustrated in
While each of the various second precursors noted above are suitable for use in forming an Al2O3 layer, the use of each of the second precursors has a different effect on the qualities of the dielectric layer formed and on the amount of GeOx re-growth that occurs underneath the dielectric layer. For example, performing ALD of Al2O3 using ozone as the second precursor provides good nucleation of the deposited aluminum oxide, thereby beneficially reducing the Dit. However, using ozone as the second precursor also undesirably results in significant GeOx re-growth. In contrast, performing ALD of Al2O3 using water as the second precursor minimizes GeOx re-growth. However, using water as the second precursor undesirably increases the Dit as it provides relatively weak nucleation of the deposited aluminum oxide.
Thus, in order to minimize Dit while simultaneously minimizing GeOx re-growth, some embodiments of the present disclosure using two (or more) different oxygen pre-cursors in sequence during the various “cycles” of the ALD process. For example, during the first several deposition cycles a first oxygen precursor is employed, and during subsequent deposition cycles a second oxygen precursor is employed. The selection of various first and second oxygen precursors may be used in order to “tune” the qualities of the deposited aluminum oxide layer (for example, lower GeOx re-growth versus lower Dit) to a specific application.
In one particular embodiment, the ALD of Al2O3 is performed wherein the initial few layers (for example, the first two or three layers) of Al2O3 are deposited using ozone as the second precursor, and the subsequent layers (until the desired layer thickness is formed) of Al2O3 are deposited using water as the second precursor. In this embodiment, using ozone for the first few layers provides good nucleation at the interface, where it is most effective at reducing Dit due to the chemical bonding between the different interface materials. Thereafter, using water for the subsequent layers minimizes the re-growth of GeOx that occurs underneath the Al2O3, thereby allowing the Al2O3 to be formed to a sufficient thickness so as to minimize the Ig, such as from about 1 nm to about 8 nm, for example from about 1 nm to about 3 nm. In one embodiment, ALD is performed at a temperature of about 250° to about 350° C., such as about 300° C. Where ozone is the precursor, the layers are deposited by exposing the substrate to the ozone precursor for about 0.2 to about 2 seconds, for example about 1 second, and to the TMA precursor for about 1.5 to about 2.5 seconds, for example about 2 seconds. Where water is the precursor, the layers are deposited by exposing the substrate to the water precursor for about 4 to about 6 second, for example about 5 second, and to the TMA precursor for about 2 second to about 3 seconds, for example about 2.5 seconds.
In another particular embodiment, the ADL of Al2O3 is performed wherein the initial few layers (for example, the first two or three layers) of Al2O3 are deposited using water as the second precursor, and the subsequent layers (until the desired layer thickness is formed) of Al2O3 are deposited using ozone as the second precursor. In this embodiment, using water for the first few layers prevents significant re-growth of GeOx, as the first few layers are where the oxygen-containing second precursor comes in closest contact with the underlying GeOx layer. Thereafter, using ozone for the subsequent layers improves the bond ordering of the Al2O3 to prevent trapping and reduce Dit. The process conditions for this embodiment are substantially as identified in the previous embodiment.
In some further embodiments of the present disclosure, GeOx re-growth is limited during ALD of the Al2O3 layer by continuously decreasing the level of oxidation in the ALD process in each successive cycle. In this manner, the level of oxidation becomes a function of film thickness growth. For example, the initial deposition cycles are performed with a relatively high oxidation level in order to promote proper nucleation at the interface so that the bonding between the dissimilar interface materials (GeOx/Al2O3) is as strong as possible. Thereafter, subsequent cycles are performed with reduced oxidation levels as the Al2O3 layer builds on itself in order to minimize any GeOx re-growth. Any of the above-mentioned second precursors are suitable for use in such methods.
In one particular embodiment, ozone is selected as the second precursor. For the first cycle, the exposure of the substrate 104 to the ozone (see step 128 of
Reference is now made to
As illustrated, one or more isolation regions 101 may be formed that extend into semiconductor material 104 to electrically isolate a plurality of transistors from one another. The isolation regions 101 are preferably formed by well-known shallow trench isolation (STI) techniques in which trenches are etched into semiconductor material 104, the trenches are filled with a dielectric material such as deposited silicon dioxide, and the excess silicon dioxide is removed by chemical mechanical planarization (CMP). STI regions 101 provide electrical isolation, as needed, between various devices of the integrated circuit that are to be formed. STI regions 101 are filled with a dielectric material such as an insulating oxide material.
In some embodiments, the gate stack structure 102 includes, without limitation: the gate insulation layer 106 overlying the IL (although the elements of the figures are not drawn in proportion relative to each other, because of the thinness of IL 107, IL 107 appears as a line in the figure), both of which are formed as described above; a metal gate electrode element 108 overlying the gate insulation layer 106; and one or more spacer structures 112 adjacent to vertical sidewalls of the gate electrode element 108. The gate stack structure 102 may also include a capping layer 110 (which may be formed from a nitride, a silicide, or other material) formed over the gate electrode element 108. Further, the gate stack structure 102 may optionally include a work function modifying material 109, such as lanthanum (La) or aluminum (Al), which may be disposed in between the gate insulation layer 106 and the metal gate electrode element 108.
As initially noted above, the metal gate stack structure 102 may be formed using either “gate first” or “gate last” process flows, as are well-known in the art. In one embodiment, the metal gate stack structure 102 is formed using a “gate first” metal gate process flow as will be described in greater detail below with continuing reference to
Continuing with the description of the exemplary gate first process flow, the work function modifying material 109 is optionally deposited subsequent to the formation of layer 106 and, as noted above, may include one or more of La and Al, for example, or other materials as are known in the art. Material 109 may be deposited using a suitable deposition technique such as atomic layer deposition (ALD), CVD, LPCVD, semi-atmospheric chemical vapor deposition (SACVD), or PECVD. The work function modifying material 109 may be deposited to a thickness sufficient to achieve the desired work function modification effect, such as from about 2 Å to about 2 nm.
Thereafter, the gate electrode element 108 may be formed by electroplating, CVD, ALD, or PVD. In some embodiments, the gate electrode element 108 is conformally deposited using CVD or ALD. The gate electrode element 108 may be formed to a thickness from about 5 nm to about 50 nm. The gate electrode element 108 may be a metal such titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi), tungsten (W), and the like. In one embodiment, the gate electrode element 108 includes TiN. The capping layer 110 may thereafter be deposited using a material such as a polysilicon, a silicon nitride, or a silicide.
With reference now to
Turning to
The spacer structures 112 may be provided to protect the underlying semiconductor material 104 during ion implantation processes (illustrated by arrows 150 in
In an alternative embodiment, the metal gate stack 102 is fabricated using gate last or replacement metal gate (RMG) techniques that are well known in the art. For example, with reference to
With reference now to
Although not illustrated, with regard to any of the embodiments described above, the partially-formed integrated circuit is completed in a conventional manner by, for example, providing electrical contacts to the source and drain regions 117 and to the gate electrodes 108, depositing interlayer dielectrics, etching contact vias, filling the contact vias with conductive plugs, and the like as are well known to those of skill in the art of fabricating integrated circuits. Additional post-processing may include the formation of one or more metal layers (M1, M2, etc.) and interlayer dielectric layers therebetween to complete the various electrical connections in the integrated circuit. The present disclosure is not intended to exclude such further processing steps as are necessary to complete the fabrication of a functional integrated circuit, as are known in the art.
Thus, embodiments of the present disclosure provide methods for depositing an aluminum oxide layer over germanium substrates using ALD in the fabrication of integrated circuits. Beneficially, the described methods do not substantially contribute to the re-growth of the germanium oxide interfacial layer, do not substantially contribute to an increase in interface state density (Dit), and do not substantially contribute to increased gate current leakage (Ig). Additionally, the described methods are suitable for integration into existing integrated circuit fabrication process flows, including both gate-first and gate-last process flows.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the disclosure, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the disclosure. It being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.
