Claims
- 1. A method for determining instance switching in simulating integrated circuit design, comprising the steps of:
generating instances and respective instance switching charge information; and determining instance switching as a function of said instance switching charge information.
- 2. A method as recited in claim 1 wherein said determining step further comprising the sub-steps of:
selecting certain instances as a function of said instance switching charge information; determining the switching probability of said selected instances; and determining the switching probability of non-selected instances.
- 3. A method as recited in claim 2 wherein said determining the switching probability of said selected instances step is determined as a function of a first user-provided probability value.
- 4. A method as recited in claim 2 wherein said determining the switching probability of non-selected instances step is determined as a function of a second user-provided probability value.
- 5. A method as recited in claim 3 wherein said determining the switching probability of non-selected instances step is determined as a function of a second user-provided probability value.
- 6. A method as recited in claim 2 wherein said determining the switching probability of said selected instances step is determined as a function of one or more random numbers.
- 7. A method as recited in claim 2 wherein said determining the switching probability of non-selected instances step is determined as a function of one or more random numbers.
- 8. A method as recited in claim 3 wherein said determining the switching probability of non-selected instances step is determined as a function of one or more random numbers.
- 9. A method as recited in claim 3 wherein said determining the switching probability of said selected instances step is determined as a function of one or more random numbers.
- 10. A method as recited in claim 9 wherein said determining the switching probability of non-selected instances step is determined as a function of one or more random numbers.
- 11. A method as recited in claim 4 wherein said determining the switching probability of said selected instances step is determined as a function of one or more random numbers.
- 12. A method as recited in claim 11 wherein said determining the switching probability of non-selected instances step is determined as a function of one or more random numbers.
- 13. A method as recited in claim 5 wherein said determining the switching probability of said selected instances step is determined as a function of one or more random numbers.
- 14. A method as recited in claim 13 wherein said determining the switching probability of non-selected instances step is determined as a function of one or more random numbers.
- 15. A method as recited in claim 1 wherein said determining instance switching step uses one or more random numbers.
- 16. A method for simulating integrated circuit design, comprising the steps of:
generating instances and respective instance switching charge information; determining instance switching as a function of said instance switching charge information; determining timing information for selected ones of said instances; calculating load information; extracting RLC parasitic networks; and conducting transient simulation.
- 17. A method as recited in claim 16 further including an additional step, after said calculating step and before said extracting step, of determining intrinsic decaps of said selected instances.
- 18. A method as recited in claim 16 further including an additional step, after said conducting step, of reporting transient simulation results.
- 19. A method as recited in claim 16 wherein said calculating load information step is performed by determining the load current waveform for each instance.
- 20. A method as recited in claim 16 wherein said calculating load information step is performed by determining time-varying resistor in series with loading capacitor connecting between each Vdd-Gnd pin pair for each instance.
- 21. A method as recited in claim 17 further including an additional step, after said conducting step, of reporting transient simulation results.
- 22. A method as recited in claim 17 wherein said calculating load information step is performed by determining the load current waveform for each instance.
- 23. A method as recited in claim 17 wherein said calculating load information step is performed by determining time-varying resistor in series with loading capacitor connecting between each Vdd-Gnd pin pair for each instance.
- 24. A method as recited in claim 18 wherein said calculating load information step is performed by determining the load current waveform for each instance.
- 25. A method as recited in claim 18 wherein said calculating load information step is performed by determining time-varying resistor in series with loading capacitor connecting between each Vdd-Gnd pin pair for each instance.
- 26. A method for selecting and determining switching instances and switching probabilities in simulating integrated circuit design, said design comprising of a plurality of blocks, comprising the steps of:
determining switching probability based on empirical information; determining average power of said blocks as a function of toggling rate; determining peak instantaneous power as a function of a user-provided percentage; searching for instances having said peak instantaneous power dividing said averaging power equaling to a given multiplier; determining instance switching as a function of instance charge information; and determining timing information for selected ones of said instances.
- 27. A method for determining decoupling capacitor insertion in an integrated circuit design, comprising the steps of:
sorting generated instances based on respective instance switching charge of said instances; determining switching scenario for said instances; performing transient simulation based on said switching scenario to generate worst Vdd-Gnd voltage for said instances; identifying cells needing decap insertion as a function of a threshold voltage, Vr, and said respective worst Vdd-Gnd voltage of said instances; and determining decap insertion for said cells needing decap insertion.
- 28. A method for determining decoupling capacitor insertion in an integrated circuit design, comprising the steps of:
sorting generated instances based on the respective instance switching charge of said instances; performing switching scenario for said instances; performing transient simulation based on said switching scenario to generate dv/dt of Vdd-Gnd voltage for said instances; identify cells needing decap insertion as a function of a threshold voltage, Vr, and said respective dv/dt of Vdd-Gnd voltage of said instances; and determining decap insertion for said cells needing decap insertion.
CROSS REFERENCE
[0001] This application claims priority to a provisional application entitled “Method for Full-Chip Vectorless Dynamic IR-drop Analysis in IC Designs” filed on May 13, 2002, having an application Ser. No. 60/380,360. This application further claims priority to a non-provisional application entitled “Method for Full-Chip Vectorless Dynamic IR and Timing Impact Analysis in IC Designs” filed on Mar. 28, 2003, having an Application No. yet to be assigned.
Provisional Applications (1)
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Number |
Date |
Country |
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60380360 |
May 2002 |
US |