The foregoing and other objects, aspects and advantages of the invention will be better understood from the following detailed description of the preferred embodiments of this invention when taken in conjunction with the accompanying drawings in which:
The following is further explanation of the present invention based on the figures and the embodiments of this invention.
One of the technology problems that this invention aims at solving is to provide a method that has simplified circuitry, low energy consumption, low cost, and easy to realize segment driver circuit in a LCD driver system.
The methods include the following operational steps:
Its characteristics are: The said step B comprises the following steps:
B1. first perform inverse operation (from 1 to 0, or from 0 to 1) on the array signal
B2. data signal and the array signal that has been processed through the inversion operation then undergo a matrix operation;
B3. The signal that has gone through the matrix operation is then sent to the BBM circuit in step C.
Step B has the following steps:
B1. Signal processor first performs inverse operation (from 1 to 0, or from 0 to 1) on the array signal;
B2. data signal and the array signal that has processed through the inversion operation are simultaneously sent to the decoder for the matrix operation;
B3. Based on the output from the decoder, the level control selector selects a corresponding level control signal which is then output to the BBM circuit in step C.
The second technology problem this invention aims to solve is to provide an application specific SEG decoder in the methods for said segment driver circuit.
Said SEG decoder comprises of a signal processor that can perform an inverse operation (from 1 to 0, or from 0 to 1) on the array signal and a decoder circuit that can perform a matrix operation; the displayed data from the register is output to the SEG decoder; the resulting control signal is further processed by the BBM circuit, its characteristics are: the signal processor first performs an inverse operation (from 1 to 0, or from 0 to 1) on the array signal; decoder circuit performs the matrix operation on the array signal that has been inversed (from 1 to 0, or from 0 to 1) before sending it to the BBM circuit.
The decoder circuit includes a combinational logic decoder, a level control selector, a signal processor that performs the inverse operation (from 1 to 0, or from 0 to 1) on the array signal. The data signal and the array signal that has been processed through the inversion circuit are simultaneously sent to the decoder for matrix operation; based on the decoder output, the level control selector selects a corresponding level control signal which is then output to the BBM circuit.
The methods of this invention first perform field processing and inverse operation (from 1 to 0, or from 0 to 1) on the array signal followed by the matrix operation rather than conducting the matrix operation first before sending the signal based on the field signal. Therefore, the methods enhance the SEG decoder by providing simplified circuitry, lower energy consumption, lower cost, and ease of realization. Moreover, further improvement can be realized in the array algorithm circuit. The multiplication and addition circuits and dynamic circuit can be replaced by the combinational logic decoder to achieve the same functions resulting in simplified circuitry, reduced surface area, and simpler logic control.
The following is a detailed explanation of the preferred embodiment of this invention referencing the figures below. Moreover, the following explanation of the embodiments is not to improperly limit in the scope of the patent claims of this invention. Thus, all of the components mentioned in following description are not the essential constitution of this invention.
For the ease of comprehension, a simple introduction of the principles of MLA is provided before describing the embodiments.
MLA LCD driver method is a technology that addresses multiple lines at one time. It utilizes orthogonal functions based on orthogonal principles in its signal processing.
Based on the display of the liquid crystal and driver principle, it can be known that, through the COM and SEG electrodes, the LCD driver chip provides an address and data to the LCD panel. With the SLA driver method, the segment driver circuit outputs data at each timing cycle. While with the MLA driver method, the segment driver circuit outputs multiple lines of data message at each timing cycle. After several cycles, the output are layered and added, and the display panel obtains the data to display.
With the MLA driver method, if the orthogonal matrix used in processing the data is O−1((N−1)*N), it results in that the scan electrode (or common driver) signal being divided into N field cycles to output O arrays. The signal electrode (or segment driver) signal is obtained by processing the data from the register using orthogonal matrix O−1 ((N−1)*N).
From the theoretical mathematic analysis, if the row addressing signal is addressed according to the orthogonal matrix O, and the displayed data read from the register is D, then: signal electrode (or segment driver) output is
S=O−1D
In each pixel, the row and column compilation can be represented by the following mathematical relationship.
D=OO−1D=ED
Through the row and column orthogonal operation, the monitor receives the data for the display.
As shown in
The embodiment methods include the following steps:
The described step A includes the following few steps:
A1. data is sent periodically from the memory cell.
A2. The output data is synchronized through the timer and stored in the register or latch;
A3. The data and the array signal are input simultaneously into the SEG decoder.
The described step B includes the following few steps:
B1. Signal processor first performs an inverse operation (from 1 to 0, or from 0 to 1) on the array signal. The array signal is based on the signal sent from field information;
B2. data signal and the array signal that has been processed through the inversion operation are simultaneously sent to the decoder;
B3. Based on the output of the decoder, the level control selector selects a corresponding level control signal. The signal is then output to the BBM circuit in step C.
The field signal mentioned in step B is needed because, in driving MLA, the same frame contains many fields; and also because the liquid crystal needs the AC load signal, thus the inverse operation (from 1 to 0, or from 0 to 1) is required.
The described step C performs the BBM process on the signal produced from step B.
In step D, the voltage level shifter 012 changes the low voltage level to a high voltage level;
The embodiment of this invention utilizes the modulation matrix as shown in
The displayed data is as shown in
In
Per the modulation matrix used by the embodiment of this invention, the SEG decoder of the embodiment of this invention is shown in
The control node of the 2-to-1 multiplexer is an inverse signal T. The input signals resulting from the converted phase of M<0>, M<0>, the converted phase of M<1>, M<1>, and the converted phase of M<2>, M<2>are sequentially sent to the 2-to-1 multiplexers I64, I65, and I66. The 2-to-1 multiplexers I64, I65, and I66 outputs are sequentially sent to the XOR gates I67, I68, and I69. XOR gates I67 has another input signal which is data input D<0>; I68 has another input signal which is data input D<1> and I69 has another input signal which is data input D<2>. The I67 output is an input to NAND gate I612 and another input to I612 is the output of I610. The XOR gates I68 and XOR gates I69 outputs are the two input nodes of XOR gates I610. NAND gate I611 has two input nodes that are the outputs of XOR gates I68 and XOR gates I69. The I613 input is the outputs of I612 and I611. The I613 input is V_CTRL output node as well as phase inverter I614 input node. The I614 output node is VN_CTRL output node.
M<0:2> is done according to the array signal sent from field information. According to the array, the first field M<0:2> is listed as low level (−1), high level (1), and high level (1); the second field M<0:2> is listed as high level (1), low level (−1), and high level (1), etc. Because the LCD requires electric field exchange, therefore the voltage must be constantly flip-flopped. T is the inverse control signal and if T is at low level, M<0> is low and the 2-to-1 multiplexer 164 output is also at low level. If T is at high level, the 2-to-1 multiplexer I64 output is also at high level. The opposite is also opposite and the M<1>, M<2> follow the same concept. D<2:0> is the synchronized data from the data register.
While M<0:2> is sent to the decoding circuit 62 after it is processed through the signal processor 61, D<2:0> is simultaneously output from the register reaching 62 at the same time as the 61 output. The voltage level control selector 63 selects a voltage control signal of the corresponding level V_CTRL or VN_CTRL based on the decoding circuit output.
Without specific constraints,
Without specific constraints,
The level shifter has an N trench MOSFET Q3 and Q4 installed in the circuit on electric potential side and a P trench MOSFET Q1 and Q2 and phase inverter circuit INV installed on the high level side. The P trench MOSFET Q1 and Q2 are in stable condition allowing its gate and drain to cross connect. The drain of the N trench MOSFET Q3 and Q4 are connected to the drain of the P trench MOSFET Q1 and Q2 respectively. The input signal is sent to MOSFET Q4 gate. The input signal that has been negative phased through the phase converter circuit INV is sent to MOSFET Q3 gate. The output is from to the common connection between MOSFET Q1 drain and Q3 drain.
When the input signal is at a low level, the N trench MOSFET Q4 is at the cutoff region (turned off) and the output from the inverter circuit is high; therefore, the N trench MOSFET Q3 is turned on. The turned on condition of MOSFET Q3 causes P trench MOSFET Q2 to also be turned on. The cutoff region (turned off) of MOSFET Q4 causes P trench of MOSFET Q1 gate to be VH, causing Q1 to be at the cutoffregion (turned off). The output signal is at a low level.
When the input signal is changed from low to high, the N trench MOSFET Q4 is turned on, causing N trench of MOSFET Q3 to be in the cutoff region (turned off). The turned on of N trench Q2 causes the gate node Vg (the voltage at the gate) of P trench Q3 to swing to the low level side, resulting in Q1 being turned on. Q1 being turned on causes the Q2 Vg (the voltage at the gate) to recharge VH, causing Q2 to cutoff. The output signal is at the high level corresponding to the VH of the P trench MOSFET Q1 being turned on.
The input signals INA and INB are non-overlapping signals. When the input signal INA is low, INB is also low, P trench of MOSFET Q5 is conducting, and N trench of MOSFET Q6 is cut off, resulting in a high level output voltage V. When the input signal INA is high, INB is also high, P trench of MOSFET Q5 is at cutoff region (turned oft) and N trench of MOSFET Q6 is turned on, resulting in a low level voltage VN. When the input signal INA is high and INB is low, both MOSFET Q5, Q6 are in the cutoff region (turned off), causing high output resistance. This circuit precludes input signals INA to be low and INB to be high at the input terminals.
While the present invention has been described with reference to certain preferred embodiments, it is to be understood that the present invention is not limited to such specific embodiments. Rather, it is the inventor's contention that the invention be understood and construed in its broadest meaning as reflected by the following claims. Thus, these claims are to be understood as incorporating not only the preferred embodiments described herein but also all those other and further alterations and modifications as would be apparent to those of ordinary skilled in the art.
Number | Date | Country | Kind |
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200610062707.0 | Sep 2006 | CN | national |