Patent Application
20110003466
This disclosure relates in general to p-n junctions and in particular to methods of forming a multi-doped junction with porous silicon.
A solar cell converts solar energy directly to DC electric energy. Generally configured as a photodiode, a solar cell permits light to penetrate into the vicinity of metal contacts such that a generated charge carrier (electrons or holes (a lack of electrons)) may be extracted as current. And like most other diodes, photodiodes are formed by combining p-type and n-type semiconductors to form a junction.
Electrons on the p-type side of the junction within the electric field (or built-in potential) may then be attracted to the n-type region (usually doped with phosphorous) and repelled from the p-type region (usually doped with boron), whereas holes within the electric field on the n-type side of the junction may then be attracted to the p-type region and repelled from the n-type region. Generally, the n-type region and/or the p-type region can each respectively be comprised of varying levels of relative dopant concentration, often shown as n−, n+, n++, p−, p+, p++, etc. The built-in potential and thus magnitude of electric field generally depend on the level of doping between two adjacent layers.
Substantially affecting solar cell performance, carrier lifetime (recombination lifetime) is defined as the average time it takes an excess minority carrier (non-dominant current carrier in a semiconductor region) to recombine and thus become unavailable to conduct an electrical current. Likewise, diffusion length is the average distance that a charge carrier travels before it recombines. In general, although increasing dopant concentration improves conductivity, it also tends to increase recombination. Consequently, the shorter the recombination lifetime or recombination length, the closer the metal region must be to where the charge carrier was generated.
Most solar cells are generally manufactured on a silicon substrate doped with a first dopant (commonly boron) forming an absorber region, upon which a second counter dopant (commonly phosphorous), is diffused forming the emitter region, in order to complete the p-n junction. After the addition of passivation and antireflection coatings, metal contacts (fingers and busbar on the emitter and pads on the back of the absorber) may be added in order to extract generated charge. Emitter dopant concentration, in particular, must be optimized for both carrier collection and for contact with the metal electrodes.
Referring now to
Prior to the deposition of silicon nitride (SiNx) layer 104 on the front of the substrate, residual surface glass (PSG) formed on the substrate surface during the POCl3 deposition process may be removed by exposing the doped silicon substrate to an etchant, such as hydrofluoric acid (HF). The set of metal contacts, comprising front-metal contact 102 and back surface field (BSF)/back metal contact 116, are then sequentially formed on and subsequently fired into doped silicon substrate 110.
The front metal contact 102 is commonly formed by depositing an Ag (silver) paste, comprising Ag powder (about 70 to about 80 wt % (weight percent)), lead borosilicate glass (frit) PbO—B2O3—SiO2 (about 1 to about 10 wt %), and organic components (about 15 to about 30 wt %). After deposition the paste is dried at a low temperature to remove organic solvents and fired at high temperatures to form the conductive metal layer and to enable the silicon-metal contact.
BSF/back metal contact 116 is generally formed from aluminum (in the case of a p-type substrate) and is configured to create an electrical field that repels and thus minimizes the impact of minority carrier rear surface recombination. In addition, Ag pads [not shown] are generally applied onto BSF/back metal contract 116 in order to facilitate soldering for interconnection into modules.
However, a low concentration of (substitutional) dopant atoms within an emitter region generally results in both low recombination (thus higher solar cell efficiencies) and poor electrical contact to metal electrodes. Conversely, a high concentration of (substitutional) dopant atoms results in both high recombination (thus reducing solar cell efficiency) and low resistance ohmic contacts to metal electrodes. In order to reduce manufacturing costs, single dopant diffusion is often used to form an emitter, with a doping concentration selected as a compromise between low recombination and low resistance ohmic contact. Consequently, potential solar cell efficiency (the percentage of sunlight that is converted to electricity) is limited.
In view of the foregoing, there is a desire to provide methods of optimizing the dopant concentration in a solar cell.
The invention relates, in one embodiment, to a method of forming a multi-doped junction on a substrate. The method includes providing the substrate doped with boron atoms, the substrate comprising a front crystalline substrate surface; and forming a mask on the front crystalline substrate surface, the mask comprising exposed mask areas and non-exposed mask areas. The method also includes exposing the mask to an etchant, wherein porous silicon is formed on the front crystalline substrate surface defined by the exposed mask areas; and removing the mask. The method further includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl3 gas, at a first temperature and for a first time period, wherein a PSG layer is formed on the front substrate surface; and heating the substrate in a drive-in ambient to a second temperature and for a second time period. Wherein a first diffused region with a first sheet resistance is formed under the porous silicon and a second diffused region with a second sheet resistance is formed under the front crystalline substrate surface without the porous silicon, and wherein the first sheet resistance is substantially smaller than the second sheet resistance.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
As previously described, the single dopant diffusion generally used to form an emitter is a compromise between low recombination and a low resistance ohmic contact. Consequently, potential solar cell efficiency (the percentage of sunlight that is converted to electricity) is limited.
While not wishing to be bound by theory, the inventors believe that porous silicon may be used to form a selective emitter. In general, porous silicon is a form of silicon with nano-scale voids, rendering a large silicon surface to volume ratio (in the order of 500 m2/cm3). Porosity is generally defined as the fraction of void within the porous silicon
In one configuration, in order to diffuse phosphorous into a boron doped silicon substrate in a quartz tube furnace, POCl3 (phosphorus oxychloride) is used. The reaction is typically:
4POCl3(2)+3O2(2)→2P2O5(2)+6Cl2(2) [Equation 1A]
2P2O5(2)5Si(2)→5SiO2(2)4P(2) [Equation 1B]
Si+O2→SiO2 [Equation 2]
The typical gases involved in a POCl3 diffusion process include: an ambient nitrogen gas (main N2 gas), a carrier nitrogen gas (carrier N2 gas) which is flowed through a bubbler filled with liquid POCl3, a reactive oxygen gas (reactive O2 gas) configured to react with the vaporized POCl3 to form the deposition (processing) gas, and optionally a main oxygen gas (main O2 gas) configured to later form an oxide layer.
In general, a silicon substrate is first placed in a heated tube furnace with a nitrogen gas ambient (main N2 gas). The deposition gas (POCl3 vapor) is then flowed into the tube furnace, heated to a deposition temperature, and exposed to reactive O2 (oxygen) gas to form P2O5 (phosphorus pentoxide) on the silicon substrate, as well as Cl2 (chlorine) gas that interacts with and removes metal impurities in the silicon substrate. P2O5 in turn reacts with the silicon substrate to form SiO2, and free P atoms. The simultaneous oxidation of the silicon wafer during the deposition results in the formation of a SiO2.P2O5 layer (PSG or phosphosilicate glass).
An additional drive-in step (free of any POCl3 flow) is typically employed using the deposition temperature or a higher temperature in order to enable the free phosphorous atoms to diffuse further into the silicon substrate and substitutionally replace silicon atoms in the lattice in order to be available for charge carrier generation. During this step, ambient gas which may comprise of main N2 gas and/or main O2 gas is flowed into the tube furnace. The use of oxygen would result in the formation of an oxide layer at the silicon wafer surface. Such an oxide layer attenuates the diffusion of P atoms from the PSG layer into the silicon substrate allowing for more control over the resultant diffusion profiles. In general, for a given temperature phosphorous diffuses slower in SiO2 than in silicon.
Another approach to phosphorus doping of silicon wafers is a spray-on technique whereby a phosphoric acid (H3PO4) mixture (usually mixed with water or an alcohol like ethanol or methanol) is sprayed onto the wafer and then subjected to a thermal treatment. The diffusion of phosphorus into a silicon wafer using phosphoric acid as a dopant source occurs via the following reaction:
2H3PO4→P2O5+3H2O[Equation 3A]
2P2O5+3Si→3SiO2+4P [Equation 3B]
The first step involves the dehydration of phosphoric acid which produces phosphorus pentoxide (P2O5) on the silicon surface which in turn acts as the phosphorus source. P2O5 in turn reacts with the silicon substrate to form SiO2, and free P atoms. An example of this process is further disclosed in U.S. patent application Ser. No. 12/692,878, filed Jan. 25, 2010, the entire disclosure of which is incorporated by reference.
Likewise, boron may be deposited on a phosphorus doped silicon substrate using BBr3 (boron tri-bromide). The reaction is typically:
4BBr3(2)+3O2(2)→2B2O3(2)+6Br3(2) [Equation 4A]
2B2O3(2)+3Si2→4B(2)+3SiO2(2) [Equation 4B]
Si+O2=SiO2 [Equation 2]
In general, a silicon substrate is first placed in a heated tube furnace which has a nitrogen gas (main N2 gas), a carrier nitrogen gas (carrier N2) which is flowed through a bubbler filled with liquid BBr3, a reactive oxygen gas (reactive O2 gas) configured to react with the vaporized BBr3 to form B2O3 (boric oxide) on the silicon substrate, and optionally a main oxygen gas (main O2 gas) configured to later form an oxide layer.
B2O3 in turn reacts with the silicon substrate to form SiO2, and free B atoms. The simultaneous oxidation of the silicon wafer during the deposition results in the formation of a SiO2.B2O3 layer (BSG or boro-silicate glass)
An additional drive-in step (free of any BBr3 flow) is typically employed using the deposition temperature or a higher temperature in order to enable the free boron atoms to diffuse further into the silicon substrate and substitutionally replace silicon atoms in the lattice in order to be available for charge carrier generation. During this step, ambient gas which may comprise of nitrogen (main N2) and/or oxygen (main O2) is flowed into the tube furnace. The use of oxygen would result in the formation of an oxide layer at the silicon wafer surface. Such an oxide layer attenuates the diffusion of boron atoms from the B2O3 layer into the silicon substrate allowing for more control over the resultant diffusion profiles. In general, for a given temperature boron diffuses slower in SiO2 than in silicon. In some cases a pre-deposition oxide layer may be grown onto the silicon wafer to allow for better diffusion uniformity.
In the case of a selective emitter, a lightly doped region with sheet resistance of between about 70 Ohm/sq to about 140 Ohm/sq is optimal, while a heavily doped region (of the same dopant type) with a sheet resistance of between about 20 Ohm/sq to about 70 Ohm/sq is optimal.
In an advantageous manner, a substrate with porous silicon regions exposed to a deposition ambient (such as POCl3, H3PO4, or BBr3) may allow a larger volume of surface PSG (or BSG in the case of BBr3) to be locally deposited, which in turn, allows for a larger amount of the dopant to be locally driven into the underlying wafer. Consequently, a set of heavily doped regions (under areas with porous silicon) and a set of lightly doped regions (under areas without porous silicon) may both be formed in the dopant diffusion ambient.
For example, in one configuration, a patterned positive mask is first deposited on the substrate, with exposed areas of the mask corresponding to subsequent metal contact regions. The substrate is subjected to a set of etchants (i.e., HF and HNO3 mixture, etc.), subsequently etching into the uncovered areas of the substrate to create porous silicon regions. After removing the mask, the p-type silicon substrate is placed in a heated tube furnace and exposed to the deposition gas (POCl3 vapor) and O2 (oxygen) gas to form P2O5 (phosphorus pentoxide) on the substrate surface and on the porous silicon regions following the reactions of Equation 1A-1B.
In another configuration, the substrate is exposed to a set of etchants (i.e. HF and HNO3 mixture, etc.), subsequently etching into the substrate to create porous silicon regions. A patterned negative mask is subsequently deposited on the substrate, with covered areas of the mask corresponding to subsequent metal contact regions. The substrate is subjected to a set of etchants (KOH, HF and HNO3 mixture, etc.) etching back the porous silicon regions in the exposed areas of the mask. After removing the mask, the p-type silicon substrate is placed in a heated tube furnace and exposed to the deposition gas (POCl3 vapor) and O2 (oxygen) gas to form P2O5 (phosphorus pentoxide) on the substrate surface and on the porous silicon regions following the reactions of Equations 1A-B.
Referring now to
Referring now to
The substrates were first cleaned with a mixture of hydrofluoric acid (HF) and hydrochloric acid (HCl), followed by a DI water rinsing step. All substrates were then dried using N2. Porous silicon was formed on substrate subsets 308 and 310 by immersion in an HF and HNO3 mixture, although other etchants and etchant techniques may also be used.
All substrates were then exposed to a dopant source in a diffusion furnace with an atmosphere of POCl3, N2, and O2. All the substrates subsets had an initial deposition temperature of about 800° C. for 20 minutes. The inventors believe the initial deposition temperature may preferably be between about 725° C. and about 850° C., more preferably between about 750° C. and about 825° C., and most preferably about 800° C. The initial deposition time period may preferably be between about 10 minutes and about 35 minutes, more preferably between about 15 minutes and about 30 minutes, and most preferably about 20 minutes. Furthermore, a 1:1 ratio of nitrogen (carrier N2 gas) to oxygen (reactive O2 gas) during deposition was employed. The inventors believe that carrier N2 gas to reactive O2 ratios of between 1:1 and 1.5:1 during the deposition step to be preferable.
The initial deposition was followed by a drive-in step with drive-in temperature of about 900° C. for about 25 minutes in an N2 ambient. The residual PSG glass layers on the substrate surface and the porous silicon were subsequently removed by a buffered oxide etch (BOE) cleaning step for about 5 minutes.
Consequently, the longer etch period of substrate subset 310 (corresponding to a greater amount of silicon surface area when compared to the un-etched silicon substrate surface) creates a substantially lower sheet resistance and thus a higher diffused phosphorous concentration.
The inventors believe the drive-in temperature may be preferably between about 850° C. and about 1050° C., more preferably between about 860° C. and about 950° C., and most preferably about 875° C. The drive-in time period may be preferably between about 10 minutes and about 60 minutes, more preferably between about 15 minutes and about 30 minutes, and most preferably about 25 minutes.
Referring now to
In general, FTIR (Fourier transform spectroscopy) is a measurement technique whereby spectra are collected based on measurements of the temporal coherence of a radiative source, using time-domain measurements of the electromagnetic radiation or other type of radiation 422 (shown as wave number on the horizontal axis). At certain resonant frequencies characteristic of the chemical bonding within a specific sample, the radiation 422 will be absorbed (shown as absorbance A.U. on the vertical axis 424) resulting in a series of peaks in the spectrum, which can then be used to identify the chemical bonding within samples. The radiation absorption is proportional to the number of bonds absorbing at a given frequency.
Here, for the porous silicon substrate, one side of the substrate was covered with a masking wax prior to being immersed in a HF and HNO3 mixture for 20 minutes in order to create a porous silicon layer on a single substrate surface. The masking wax layer was subsequently removed with acetone followed by a water rinse. The porous silicon and non-porous silicon samples were cleaned using a mixture of hydrofluoric acid (HF) and hydrochloric acid (HCl). The substrates were loaded into a standard tube furnace and subjected to a POCl3 deposition step at about 800° C. for about 20 minutes, using a nitrogen (carrier N2) to oxygen (reactive O2) gas ratio of about 1:1 during deposition. No subsequent drive-in step was performed. The process was thus terminated after PSG deposition onto both substrates.
First spectrum 408 (corresponding to a silicon substrate without porous silicon) and second spectrum 410 (corresponding to a silicon substrate with porous silicon created using a 20 minute etch) show peaks in the range of 1330 cm−1 that is characteristic of P═O (phosphorous oxygen double bonding) and around 450 cm−1, 800 cm−1, and 1100 cm−1 that are characteristic of Si—O (silicon oxygen single bonding), all typical of deposited PSG films. The absorbance of the second spectrum 410 is substantially greater than the absorbance of the first spectrum 408, indicating that there is significantly more PSG embedded in the porous silicon layer compared to a bare silicon substrate.
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The inventions illustratively described herein may suitably be practiced in the absence of any element or elements, limitation or limitations, not specifically disclosed herein. Thus, for example, the terms “comprising,” “including,” “containing,” etc. shall be read expansively and without limitation. Additionally, the terms and expressions employed herein have been used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention claimed.
Thus, it should be understood that although the present invention has been specifically disclosed by preferred embodiments and optional features, modification, improvement and variation of the inventions herein disclosed may be resorted to by those skilled in the art, and that such modifications, improvements and variations are considered to be within the scope of this invention. The materials, methods, and examples provided here are representative of preferred embodiments, are exemplary, and are not intended as limitations on the scope of the invention.
As will be understood by one skilled in the art, for any and all purposes, particularly in terms of providing a written description, all ranges disclosed herein also encompass any and all possible subranges and combinations of subranges thereof. Any listed range can be easily recognized as sufficiently describing and enabling the same range being broken down into at least equal halves, thirds, quarters, fifths, tenths, etc. As a non-limiting example, each range discussed herein can be readily broken down into a lower third, middle third and upper third, etc. As will also be understood by one skilled in the art all language such as “up to,” “at least,” “greater than,” “less than,” and the like include the number recited and refer to ranges which can be subsequently broken down into subranges as discussed above. In addition, the terms “dopant or doped” and “counter-dopant or counter-doped” refer to a set of dopants of opposite types. That is, if the dopant is p-type, then the counter-dopant is n-type. Furthermore, unless otherwise dopant-types may be switched. In addition, the silicon substrate may be either mono-crystalline or multi-crystalline.
All publications, patent applications, issued patents, and other documents referred to in this specification are herein incorporated by reference as if each individual publication, patent application, issued patent, or other document were specifically and individually indicated to be incorporated by reference in its entirety. Definitions that are contained in text incorporated by reference are excluded to the extent that they contradict definitions in this disclosure.
For the purposes of this disclosure and unless otherwise specified, “a” or “an” means “one or more.” All patents, applications, references and publications cited herein are incorporated by reference in their entirety to the same extent as if they were individually incorporated by reference. In addition, the word set refers to a collection of one or more items or objects.
Advantages of the invention include the production of low cost and efficient junctions for electrical devices, such as solar cells.
Having disclosed exemplary embodiments and the best mode, modifications and variations may be made to the disclosed embodiments while remaining within the subject and spirit of the invention as defined by the following claims.
This application claims the benefit of U.S. Pat. App. No. 61/222,628 filed Jul. 2, 2009, entitled Methods of Using A Silicon Particle Fluid To Control In Situ A Set Of Dopant Diffusion Profiles, U.S. patent application Ser. No. 12/692,878, filed Jan. 25, 2010, entitled Methods Of Forming A Dual-Doped Emitter On A Substrate With An Inline Diffusion Apparatus, and, U.S. patent application Ser. No. 12/656,710, filed Feb. 12, 2010, entitled Methods of Forming a Multi-Doped Junction with Silicon-Containing Particles, the entire disclosures of which is incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61222628 | Jul 2009 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12692878 | Jan 2010 | US |
| Child | 12794188 | US | |
| Parent | 12656710 | Feb 2010 | US |
| Child | 12692878 | US |
