This application claims priority to Korean Patent Application No. 2004-60809, filed on Aug. 2, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The present invention relates to methods of forming a semiconductor device and, more particularly, methods of forming a semiconductor device having a P-channel metal oxide semiconductor (PMOS).
Semiconductor devices having a PMOS region/device are used, for example, for complementary metal oxide semiconductor (CMOS) devices. A CMOS semiconductor device generally includes a P-channel MOS transistor and an N-channel MOS transistor that are constructed on a semiconductor device to perform a complementary operation. With CMOS technology, the efficiency and operating speed of the semiconductor device may be increased relative to a PMOS device and a CMOS transistor device may have characteristics similar to a bipolar transistor. CMOS semiconductor devices are typically used for semiconductor devices requiring high speed and performance. With the recent trend of increasing density for finer semiconductor devices, dual polysilicon gate type CMOS devices have been widely used to increase integration density and to improve a threshold voltage characteristic and an operating speed for the devices. In the dual polysilicon gate CMOS type device, polysilicon defining a gate formed in respective channels is typically doped with impurities having the same conduction type as the channel. Advantageously, the dual polysilicon gate typically makes it possible to enhance a function of a channel surface layer and to perform a symmetrical low-voltage operation.
In various methods of forming a dual polysilicon gate, a polysilicon layer for a PMOS polysilicon gate is doped with P-type impurities and a polysilicon layer for an NMOS polysilicon gate is doped with N-type impurities. Each of the doped polysilicon layers is annealed to activate the impurities.
The P-type impurities may be, for example, boron (B) or boron fluoride (BF2). As boron is typically readily diffused, doped boron may be diffused during an annealing process to reach a gate oxide layer or to be diffused to an underlying semiconductor substrate through the gate oxide layer. This may lead to generation of leakage current, which may be overcome using boron fluoride (BF2) because BF2 generally has a lower diffusivity than boron (B). However, if a polysilicon layer is doped with BF2 and annealed, small voids typically are formed at an upper portion of the polysilicon layer. Referring to
Embodiments of the present invention provide methods of forming a semiconductor device including forming a polysilicon layer on a semiconductor substrate and doping the polysilicon layer with P-type impurities. The semiconductor substrate including the polysilicon layer is annealed and then an upper portion having a first thickness of the annealed polysilicon layer doped with the P-type impurities is removed. The first thickness is selected to remove defects formed in the polysilicon layer during doping and/or annealing thereof.
In some embodiments of the present invention, the P-type impurities are boron fluoride (BF2). The polysilicon layer may be a conductive layer and there may be defects in the upper portion thereof. Forming the polysilicon layer may include forming the polysilicon layer to a thickness corresponding to the first thickness plus a desired thickness of a remaining polysilicon layer and removing an upper portion may include removing the upper portion to provide a remaining polysilicon layer having the desired thickness.
In other embodiments of the present invention, removing the upper portion of the polysilicon layer doped with the P-type impurities is followed by patterning the polysilicon layer to form a P-type gate electrode. Patterning the polysilicon layer may be preceded by stacking a metal containing layer on a surface of the semiconductor substrate including the polysilicon layer and patterning the polysilicon layer may include concurrently patterning the metal containing layer and the polysilicon layer. The metal containing layer may include tungsten, aluminum, copper, titanium, tantalum, iridium, cobalt, rhodium, platinum, palladium, and/or molybdenum and/or nitrides or suicides thereof.
In further embodiments of the present invention, removing the upper portion of the polysilicon layer doped with the P-type impurities includes planarizing the polysilicon layer. Planarizing the upper portion may include chemical mechanical polishing (CMP) the polysilicon layer.
In other embodiments of the present invention, forming a polysilicon layer is preceded by forming a gate oxide layer on the semiconductor substrate and removing the upper portion of the polysilicon layer is followed by patterning the polysilicon layer doped with the P-type impurities to form a P-type gate electrode and forming P-type impurity source/drain regions proximate to and on opposite sides of the P-type gate electrode. Forming the polysilicon layer may include forming the polysilicon layer to a thickness corresponding to the first thickness plus a desired thickness of a remaining polysilicon layer and removing an upper portion may include removing the upper portion to provide a remaining polysilicon layer having the desired thickness.
In yet further embodiments of the present invention, the semiconductor substrate includes a NMOS region and a PMOS region. Forming the polysilicon layer includes forming the polysilicon layer in the NMOS and the PMOS regions and doping the polysilicon layer in the NMOS and the PMOS regions with N-type impurities. Doping the polysilicon layer includes doping the polysilicon layer with the P-type impurities in the PMOS region and not in the NMOS region. In some embodiments, the semiconductor substrate includes an NMOS region and a PMOS region and doping the polysilicon layer includes doping the polysilicon layer with the P-type impurities in the PMOS region and not in the NMOS region and annealing the semiconductor substrate is preceded by doping the polysilicon layer in the NMOS region with N-type impurities.
In other embodiments of the present invention, the methods further include patterning the polysilicon layer in the NMOS region to form an N-type gate electrode in the NMOS region and forming N-type impurity source/drain regions in the semiconductor substrate proximate to and on opposite sides of the N-type gate electrode. Patterning the polysilicon layer may be preceded by stacking a metal containing layer on a surface of the semiconductor substrate including the polysilicon layer and patterning the polysilicon layer may include concurrently patterning the metal containing layer and the polysilicon layer. The metal containing layer may be at least one material selected from the group consisting of tungsten, aluminum, copper, titanium, tantalum, iridium, cobalt, rhodium, platinum, palladium, and molybdenum.
In yet further embodiments of the present invention, methods of forming a semiconductor device include forming a gate oxide layer and a polysilicon layer doped with N-type impurities on a semiconductor substrate having an NMOS region and a PMOS region. Using a mask layer covering the polysilicon layer in the NMOS region the polysilicon layer in the PMOS region is doped with P-type impurities. The semiconductor device including the polysilicon layer is annealed. An upper portion having a first thickness of the polysilicon layer doped with the P-type impurities is removed. The first thickness is selected to remove defects formed in the polysilicon layer during doping and/or annealing thereof. The polysilicon layer is patterned to form a P-type gate electrode in the PMOS region and to form an N-type gate electrode in the NMOS region. P-type impurity regions are formed in the semiconductor substrate proximate to and on opposite sides of the P-type gate electrode. N-type impurity regions are formed in the semiconductor substrate proximate to and on opposite sides of the N-type gate electrode. Patterning the polysilicon layer may be preceded by stacking a metal containing layer on a surface of the semiconductor substrate including the polysilicon layer and patterning the polysilicon layer may include concurrently patterning the metal containing layer and the polysilicon layer.
In other embodiments of the present invention, methods of forming a semiconductor device include forming a gate oxide layer on a semiconductor substrate having an NMOS region and a PMOS region. An undoped polysilicon layer is formed on an entire surface of a semiconductor substrate where the gate oxide layer is formed. Using a mask covering the polysilicon layer in the PMOS region, the polysilicon layer in the NMOS region is doped with N-type impurities. The semiconductor substrate including the polysilicon layer is annealed. An upper portion of the polysilicon layer doped with the P-type impurities is removed as much as a first thickness. The polysilicon layer is patterned to form a P-type gate electrode in the PMOS region and to form an N-type gate electrode in the NMOS region. A P-type impurity region is formed in the semiconductor substrate disposed on opposite sides of and adjacent to the P-type gate electrode. An N-type impurity region is formed in the semiconductor substrate disposed on opposite sides of and adjacent to the N-type gate electrode.
In some embodiments of the present invention, when the polysilicon layer is formed, the entire polysilicon layer is doped with N-type impurities. When the polysilicon layer is doped with the P-type impurities, a mask layer may be used to cover a polysilicon layer in the NMOS region.
In other embodiments of the present invention, only a polysilicon layer in the PMOS region is doped with the P-type impurities. Before an annealing process is performed, a polysilicon layer in the NMOS region may be doped with N-type impurities. An upper portion of the polysilicon layer doped with the P-type impurities may be removed as much as a first thickness. The polysilicon layer may be patterned to form an N-type gate electrode in the NMOS region and to form a P-type gate electrode in the PMOS region. Before the polysilicon layer is patterned, a metal containing layer may be stacked on an entire surface of the semiconductor substrate. When the polysilicon layer is patterned, the metal containing layer may also be patterned.
The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Some embodiments of the present invention will now be described with reference to
Referring to
A gate oxide layer 14 is formed on the active region. The formation of the gate oxide layer 14 may be done using a thermal oxidation process and/or a chemical vapor deposition (CVD) process. A polysilicon layer 18b doped with N-type impurities is formed on the gate oxide layer 14. The formation of the polysilicon layer 18b may be done using a CVD process. When a polysilicon layer is deposited, it may be doped with N-type impurities supplied simultaneously. The polysilicon layer 18b may have a thickness of, for example, 400-1000 angstroms (Å). A thickness of the polysilicon layer 18b is equal to the sum of a thickness of a finally remaining polysilicon layer and a thickness of a to-be-removed polysilicon layer. For example, if the thickness of the finally remaining polysilicon layer is 300 angstroms and the thickness of the to-be-removed polysilicon layer is 200 angstroms, an initial thickness of the polysilicon layer 18b is 500 angstroms. A concentration of the N-type impurities is, for example, 1×1015˜1×1020 ions/cm2.
Referring to
Referring to
Referring to
As illustrated in
Referring to
Referring to
As previously stated, an upper portion of the polysilicon layer 18a with defects “D” is removed. Thus, although metal containing layers 24 and 26 are stacked and patterned to form a gate electrode in a subsequent process, there may be no resulting problems, such as an increase in resistance or a malfunction of a device. As a planarization process for removing the defects “D” may be performed to lower an overall height of the gate pattern, a gap-fill property may become superior and an etch process for forming a gate pattern or a contact hole may be readily performed. Further, a gate polysilicon electrode in a PMOS region may be doped with P-type impurities, for example, BF2, to limit or even prevent leakage current generated when it is doped with boron.
Further embodiments of the present invention will now be described with reference to
Referring to
A gate oxide layer 14 is formed on the active region. The formation of the gate oxide layer 14 may be done using a thermal oxidation process and/or a chemical vapor deposition (CVD) process. An undoped polysilicon layer 18 is formed on the gate oxide layer 14. The formation of the polysilicon layer 18 may be done using a CVD process. The polysilicon layer 18 may have a thickness of, for example, 400-1000 angstroms. A thickness of the polysilicon layer 18 is equal to the sum of a thickness of a finally remaining polysilicon layer and a thickness of a to-be-removed polysilicon layer. For example, if the thickness of the finally remaining polysilicon layer is 300 angstroms and the thickness of the to-be-removed polysilicon layer is 200 angstroms, an initial thickness of the polysilicon layer 18 is 500 angstroms.
Referring to
Referring to
After the ion implanting process is completed, the mask layer 21a covering the PMOS region is removed. The mask layers 21a and 21b may be made of photoresist pattern or silicon nitride.
Doping the undoped polysilicon layer 18 with the P-type impurities and doping the undoped polysilicon layer 18 with the N-type impurities are interchangeable with each other. That is, after doping the polysilicon layer 18 in the NMOS region with the N-type impurities using a mask layer covering the PMOS region, the polysilicon layer 18 in the PMOS region may be doped with the P-type impurities using a mask layer covering the NMOS region.
A CMOS semiconductor device having the same dual gate as described with reference to
Although the present invention has been described with reference to the exemplary embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.
Number | Date | Country | Kind |
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2004-60809 | Aug 2004 | KR | national |