Patent Grant
9684580
The subject matter described herein relates to scrambling data signals. More particularly, the subject matter described herein relates to methods, systems, and computer readable media for efficient scrambling of data for line rate transmission in high speed communications networks.
In today's high speed networks, such as 100 Gigabit (100 G) and 400 Gigabit (400 G) Ethernet networks, data is scrambled with a scramble key before being transmitted on the wire to reduce undesirable frequency characteristics and to facilitate descrambling at the receiver. For example, transmitting a long sequence of ones or zeros results in spikes at specific frequencies and inefficiently utilizes the frequency bandwidth allocated for the transmitted signal. In addition, a long sequence of ones or zeros makes synchronization at the receiver difficult due to the lack of transitions in the transmitted signal. Transmitters use a scramble key and a corresponding scrambling algorithm to reduce the likelihood of long sequences of ones and zeros and thereby spread the frequency spectrum of the transmitted signal over a wider frequency bandwidth.
Scrambling data at line rates in high speed networks can be difficult. In 100 G Ethernet, 400 G Ethernet, and beyond, data bus widths can be on the order of hundreds of bits in order to transmit data at line rates. Scrambling data at line rate on such wide busses requires that an entire bus width of data be scrambled during each clock cycle. Scrambling an entire bus width of data when the bus is on the order of hundreds of bits wide requires that the scrambler logically implement the shift and XOR operations for each bit on the data bus being scrambled. While such logic implementations are possible, physical real estate on a chip for implementing a scrambler may be limited.
Accordingly, there exists a long felt need for methods, systems, and computer readable media for efficiently implementing a scrambler for scrambling data in high speed communications networks.
The subject matter described herein includes methods, systems, and computer readable media for efficiently scrambling data in high speed communications networks. One exemplary method includes, in a network equipment test device, providing a scrambler for scrambling data to be output to a device under test. Scrambling the data includes separating a scrambling algorithm into a scramble key portion and a data portion. Scrambling the data further includes precomputing and storing the scramble key portion. Scrambling the data further includes precomputing and storing the data portion. Scrambling the data further includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width scrambled output data. The method further includes transmitting the scrambled output data over a network to the device under test.
By “precomputing”, it is meant that the scramble key portion and the data portion are computed in advance of being logically combined with each other.
In addition, the subject matter described herein is described as being implemented by “blocks”. It is understood that such blocks refer to processing hardware and/or firmware for performing the indicated functions.
The subject matter described herein can be implemented in software in combination with hardware and/or firmware. For example, the subject matter described herein can be implemented in software executed by a processor. In one exemplary implementation, the subject matter described herein can be implemented using a non-transitory computer readable medium having stored thereon computer executable instructions that when executed by the processor of a computer control the computer to perform steps. Exemplary computer readable media suitable for implementing the subject matter described herein include non-transitory computer-readable media, such as disk memory devices, chip memory devices, programmable logic devices, and application specific integrated circuits. In addition, a computer readable medium that implements the subject matter described herein may be located on a single device or computing platform or may be distributed across multiple devices or computing platforms.
The subject matter described herein will now be explained with reference to the accompanying drawings of which:
The subject matter described herein includes methods, systems, and computer readable media for efficient scrambling of data for line rate transmission in a high speed communications network.
SOn=Dn⊕S57⊕S38, (1)
where SOn is the scrambler output for data bit Dn and S57 and S18 are the fifty-seventh and eighteenth bit of the scramble key, respectively. Thus, the scrambler output for data bit zero would be:
SO0=D0⊕S57⊕S18. (2)
Because the scrambler must scramble all of the bits on the data bus in a single clock cycle and the scramble key must be loaded with the data output and shifted for each bit, using a 256 bit bus as an example, the scrambler outputs for iteration 0 through 255 of the shift operations illustrated in
SO0=D0⊕S57⊕S38 (3)
SO1=D1⊕S56⊕S37 (4)
SO2=D2⊕S55⊕S36 (5)
The equation for scrambler output becomes increasingly more complex as the data bus width increases because the output depends on the scramble key, which depends on the scrambler output for previous input data bits. For example, for the 38th bit on the data bus, the equation for the scrambler output may be:
SO38=D38⊕S3819⊕S380, (6)
where S3819 is the value of the 19th position in the scramble key after the 38th iteration of the scrambling algorithm (beginning with iteration zero) and S380 is the value in the 0th position of the scramble key after the 38th iteration of the scrambling algorithm. The term S3819 stores the value SO18, which is the scrambler output after the 18th iteration of the scrambling algorithm, which can be expanded as follows:
S3819=SO18=D18⊕S39⊕S20,
where S39 and S20 are the values stored in the 39th and 20th positions of the original scramble key. The remaining term from Equation 6, S380, which stores the scrambler output after the 37th iteration of the scrambling algorithm can be expanded as follows:
Fully expanded, Equation 6, which is the equation for the 38th bit on the data bus becomes:
SO38=D38⊕D18⊕S39⊕S20⊕D37⊕D20⊕S37⊕S18⊕D1⊕S56⊕S37 (7)
Each term in Equation 7 represents a logic element needed to store the associated value. Exclusive OR gates are also required to implement the computations. Thus, Equation 7 requires 11 logic elements to store the equation terms plus a ten-input exclusive OR gate to combine the values and an additional logic element to store the output, for a total of 13 logic elements. Equation 7 is only the equation for scrambling the 38th bit on the data bus. Similar equations must be implemented for the remaining bits on the data bus. The logic elements required to implement such equations increases in number as data bus widths increase. While such logic could be implemented, scrambler chip real estate is a finite resource, and implementing the logic to calculate the scrambler output for each bit on a wide data bus is impractical.
Accordingly, to avoid this difficulty, a network equipment test device that tests gigabit Ethernet or other high speed equipment has knowledge of the data that will be transmitted during a given iteration of the test. With such knowledge, the scrambler output for a full data bus width of data at a given clock cycle can be viewed as:
Scrambler output=f(scramble key)⊕f(data) (8)
The term f(scramble key) represents the effect of the scramble key on the scrambler output and the term f(data) represents the effect of the data on the scrambler output. f(data) can be precomputed by setting the entire scramble key to all zeros and computing f(data) for an entire data bus width of data. fn(data) for each bit of an n bit data bus can be computed as follows:
fn(data)=Dn⊕S57⊕S38 (9)
Thus, f0(data) is:
f0(data)=D0⊕0⊕0=D0 (10)
Similarly, Equations 3-5 simplify to:
f1(data)=D1⊕0=D1 (11)
f2(data)=D2⊕0=D2 (12)
f3(data)=D3⊕0=D3 (13)
Equation 7 becomes:
Similar calculations can be performed for each bit on the data bus at a given time.
Once f(data) has been computed by using all zeros for the scramble key, the next step is to precompute f(scramble key) assuming all zeros for the input data. f(scramble key) can be computed as follows:
fn(scramble key)=0⊕S57⊕S38 (15)
Thus,
Even though Equations 15-25 for computing f(scramble key) for each data bit on the data bus during a given clock cycle show an increasing number of terms with the number of iterations for the data bus width, because all of the data bits are zeros, the function f(scramble key) depends only on the original scramble key bits themselves. As a result, values for each iteration of f(scramble key) can be precomputed and stored.
Once f(scramble key) and f(data) have been precomputed for each bit currently on the data bus, the scrambler output can be computed using Equation 8 and a single 2 input exclusive OR gate using the two values stored for each bit on the data bus. Exemplary computations that may be performed are as follows:
Scrambler outputn=fn(scramble key)⊕fn(data) (26)
Scrambler output0=f0(scramble key)⊕f0(data) (27)
Scrambler output1=f1(scramble key)⊕f1(data) (28)
Because the values for fn(scramble key) and fn(data) are precomputed and stored, the scrambler output can be computed at line rate for 100 G Ethernet, 400 G Ethernet, or higher data rates.
In order to scramble packets at line rate, network equipment test device 200 includes an f(data) precomputation block 206 for computing the effect of the data on the scrambler output and an f(scramble key) precomputation block 208 for computing the effect of the scramble key on the output. F(data) precomputation block 206 may compute fn(data) as described above with regard to Equations 9-13. f(scramble key) calculation block may compute fn(scramble key) using Equations 15-25 described above. The output of f(data) precomputation block 206 and f(scramble key) precomputation block 208 may be stored in memory 210. A scrambler output data generator 212 may compute the scrambler output using the stored values for f(scramble key) and f(data) using Equations 26-28 as described above.
Accordingly, by precomputing fn(scramble key) and fn(data), the subject matter described herein enables line rate scrambling of data at 100 G, 400 G, and higher data rates without requiring complex logic to implement.
In step 304, the method includes precomputing and storing the scramble key portion. For example, fn(scramble key) may be precomputed using Equations 15-25, as described above. Like the computations for f((data), the computations for fn(scramble key) may be performed in advance of a given clock cycle and then logically combined with fn(data) during a given clock cycle for generating the scrambler output. Thus, step 304 may include computing fn(scramble key) for multiple upcoming clock cycles and storming the precomputed values.
In step 306, the method includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width of scrambled output data. For example, the scrambler output may be computed for each bit on the data bus during a clock cycle using Equations 26-28 as described above. In step 308, the method includes transmitting the scrambled output data. For example, a bus width of scrambled output data may be transmitted by a network equipment test device 200 to device under test 202. In step 310, the next clock cycle occurs and control returns to step 306 where the process is repeated for the precomputed values for fn(data) for the data bits on the data bus for the next clock cycle and the precomputed values for fn(scramble key).
As illustrated in
The scrambler architecture described herein can be pipelined and parallelized to scramble a data bus of a desired bit width and achieve a desired output line rate.
The links associated with each 256 bit portion of data are labeled in
In
Logical combination blocks 416 logically combine the precomputed f(data) and f(scramble key) portions, e.g., using an XOR operation as described above. The labels on each input link to logical combination blocks 416 indicate the corresponding f(data) and f(scramble key) portions being logically combined by the respective block. For example, the topmost logical combination block combines the yellow precomputed f(data) value with the yellow precomputed f(scramble key) value. The remaining logical combination blocks 416 perform logical combinations of their respective f(data) and f(scramble key) portions. Thus, each set of precomputation blocks 206 and 208 and their respective logical combination and output blocks 416 and 418 for a particular color label can be considered a separate scrambler capable of scrambling m bits per clock cycle. In general, n scramblers, each capable of scrambling m bits per clock cycle can be connected in the pipelined, parallel architecture illustrated in
In
It will be understood that various details of the presently disclosed subject matter may be changed without departing from the scope of the presently disclosed subject matter. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation.
This application claims the priority benefit of U.S. Provisional Patent Application Ser. No. 61/900,367 filed Nov. 5, 2013, the disclosure of which is incorporated herein by reference in its entirety.
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| Number | Date | Country | |
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| 20150135014 A1 | May 2015 | US |
| Number | Date | Country | |
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| 61900367 | Nov 2013 | US |
