Patent Application
20170201401
The present disclosure relates generally to demodulation. More particularly, the present disclosure relates to digital demodulation of a communication signal.
Smart field devices that output 4 to 20 mA current signals often use Highway Addressable Remote Transducer (HART) communication signals (superimposed upon the process signal) to communicate with host equipment. According to the HART standard, process signals are modulated with binary data using frequency shift Keying (FSK) modulation with 1200 Hz and 2200 Hz tones, having a bit period of 1/1200 second.
To extract the modulated binary data, the modulated signal needs to be demodulated and converted into digital form. Conventional hardware for extracting the process signal and the modulated binary data requires dual paths: one path for the process signal and one path for the modulated signal. In the past, each path required its own analog-to-digital converter (ADC) or an ADC for the process signal path plus a modem. Part of the reason for this is that the ADC is typically time multiplexed across several channels of a modulated signal to amortize cost and space. As an ADC is shared across several channels of a modulated signal, a separate ADC is needed for conversion of the process signal.
In at least one embodiment, the present disclosure provides a method for digitally demodulating an input signal including a process signal modulated with a sinusoidal signal. The method includes receiving the input signal, converted from analog form to digital form. The method also includes filtering the converted input signal through a first programmable digital filter to extract the process signal and filtering the converted input signal through a second programmable digital filter to extract the sinusoidal signal. The method further includes creating a binary data signal based on the extracted sinusoidal signal.
In at least another embodiment, the present disclosure provides a system for Digitally demodulating an input signal including a process signal modulated with a sinusoidal signal. The system includes a first programmable digital filter configured to filter the input signal, converted from analog form to digital form, to extract the process signal. The system also includes a second programmable digital filter configured to filter the input signal, converted from analog form to digital form, to extract the sinusoidal signal, and a programmable detector configured to create a binary data signal based on the extracted sinusoidal signal.
In at least another embodiment, the present disclosure describes a computer readable storage device having stored thereon instructions which, when executed by a processor, cause the processor to perform operations for demodulating an input signal including a process signal modulated with a sinusoidal signal. The operations include receiving the input signal, converted from analog form to digital form, digitally filtering the converted input signal to extract the process signal, and digitally filtering the converted input signal to extract the sinusoidal signal. The operations further include creating a binary data signal based on the extracted sinusoidal signal.
Further features and advantages, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings. It is noted that the disclosure is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.
Illustrative embodiments may take form in various components and arrangements of components. Illustrative embodiments are shown in the accompanying drawings, throughout which like reference numerals may indicate corresponding or similar parts in the various figures. The drawings are only for purposes of illustrating preferred embodiments and are not to be construed as limiting the disclosure. Given the following enabling description of the drawings, the novel aspects of the present disclosure should become evident to a person of ordinary skill in the art.
While illustrative embodiments are described herein for particular applications, it should be understood that the disclosure is not limited thereto. Those skilled in the art with access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the multi-reflector design described herein would be of significant utility.
Alternative embodiments, examples, and modifications which would still be encompassed by the disclosure may be made by those skilled in the art, particularly in light of the foregoing teachings. Further, it should be understood that the terminology used to describe the disclosure is intended to be in the nature of words of description rather than of limitation.
The modulated current signal is conducted over the field wiring 150 and detected by an operational amplifier 160B in the host device 100B as a voltage across a resistor R1 included in the host device 100B. The detected voltage signal is converted into a digital signal by an ADC (not shown in this figure for simplicity of illustration). The process signal representing the sensor measurement is then extracted by a digital filter 165B, and the modulated signal is extracted and demodulated by a digital HART demodulator 170B to produce the encoded binary data.
Similarly, binary data on the host side 100B is converted to a sinusoidal signal by a modulator 110B, filtered by a filter 115B and coupled to the field wiring 150 by a voltage modulator (VM). The modulated signal is detected as a voltage signal by the operational amplifier 160A. Although not shown in the interest of simplicity, the detected signal is converted to a digital signal by an ADC. The converted signal is filtered by a filter 165A to attenuate unwanted signals that may interfere with HART demodulation, e.g., signals in the process signal band from DC to 30 Hz, and extract HART frequency signals in the Extended Frequency Band (500 Hz-10 KHz). The filtered signal is demodulated by a digital HART demodulator 170A to produce the encoded binary data.
The digital HART demodulators 170A and 170B are illustrated in
The values produced by the QRs 320A and 320B are digital representations of the continuous (analog) value of the energy. Technically, the values are estimates of the energy. At any moment in time, the estimates may be compared, and the larger value indicates the frequency which is most likely present at that moment in time. A digital routine may be used to make this comparison as often as needed, which may be several times per FSK bit period (1/1200, in units of seconds).
According to an illustrative embodiment, this comparison may be made by a difference operator 330. If the resulting value is positive, then the energy estimate at 1200 Hz is larger than the energy estimate of 2200 Hz, thus indicating the likely presence of a tone at 1200 Hz. If the result is negative, then the energy estimate at 1200 Hz is smaller than the energy estimate at 2200 Hz, thus indicating the likely presence of a tone at 2200 Hz. As the digital routine makes successive differences, several times per bit period, the sign of the result will transition a few sample times after the frequency shifts. During the transition, there may be uncertainty in the estimates, and a rapid alternation may result at the output of the difference operator 330. A few sample times after the transition, however, the alternations cease and the output of the difference operator 330 stays solidly in one state or the other.
Referring to
In the arrangement shown in
Referring again to
Outputs of the QRs 420 and 430 are compared by a difference operator 450 to produce an output indicating whether a 1200 Hz frequency signal or a 2200 Hz frequency signal is present. The output of the difference operator 450, which is considered “analog” or “continuous” yet represented in the digital domain, is low pass filtered by the low pass filter 460 to remove most of the indecision during the transitions between 1200 Hz and 2200 Hz.
The transitions require some downstream processing logic to produce a glitch-free binary value. For this purpose, a detector 470 may be used.
The detector 470 performs two basic functions. It determines whether the signal is large enough to be considered a tone with a Carrier Detect (CD), and it converts the analog and somewhat noisy value into a binary value using Clock and Data Recovery (CDR).
The CD determines whether the carrier is present with enough signal to noise ratio (SNR) to be reliable. In particular, the FSK modulated signal may cease or disappear in a noisy environment, making reliable communications impossible. In this type of environment, the CD function suppresses the output to prevent noisy binary data.
The CDR determines the ideal sampling time to determine the binary output. The device that transmitted the modulated FSK signal has a different time reference that is asynchronous to the device including the demodulator 400. Additionally, the filtered output of the difference operator 450 has jitter in the edge transitions. The CDR rejects the jitter by locating the edge transitions in the binary stream and then using the “center” or “eye” of the bit period to determine whether there is “1” or “0”.
The conversion from the “analog” value from the low pass filter 460 into a binary value is performed by the CDR based on the sign of the analog value. If the sign is positive, the binary value is a ‘1’, and if the sign is negative, the binary value is a ‘0’.
The bit period is 1/1200 second. However, since the transmitting device is asynchronous, the CDR is used to adjust for the fact that the bit period is not exactly 1/1200.
According to an illustrative embodiment, the digital HART demodulator may be applied per channel, with one ADC dedicated to a particular digital channel. As an alternative, a high sample rate ADC may be used to support multiple demodulators in another implementation. As yet another alternative, there may be one ADC for multiple input analog channels.
According to an illustrative embodiment, the ADC 180 may be implemented with a sigma delta ADC. Sigma deltas ADCs are smaller and cheaper than traditionally used successive approximation (SAR) or Flash based ADCs. Also, a sigma delta ADC may be applied per channel.
According to an illustrative embodiment, the digitization of an input analog signal occurs as close as possible to the signal source, e.g., close to the terminals of the field wiring 150. Processing of the input signal to extract the process signal and the sinusoidal modulated signal and to demodulate the modulated signal then occurs downstream in the digital domain where complexity costs less and requires less board space.
According to illustrative embodiments, a continuous sampling ADC is combined with digital filtering and a digital HART demodulator to demodulate HART signals and acquire the low frequency process signal. Here, the system is not only a HART communications modem, but it also includes the process signal acquisition hardware which is often implemented separately. The HART signal and the process signal are both acquired by the same hardware.
According to illustrative embodiments, use of the digital demodulator, in conjunction with a single ADC for a process signal path and a sinusoidal signal path results in a simpler, cheaper circuit with fewer electronics in the acquisition hardware, minimal analog filters (e.g., for anti-aliasing), and better response times in comparison with traditional HART demodulators.
Traditionally, one HART modem including a HART demodulator was shared by more than one channel for cost, space, and thermal reasons. The digital HART demodulator described herein may easily be implemented for each channel with no multiplexing required. However, it should be appreciated that, although not shown, there may be one instance of the digital HART demodulator for multiple channels using time multiplexing to multiple (N) interfaces.
Further, it should be appreciated that, although not shown, there may be multiple instances of the digital HART demodulators, such that multiple digital HART demodulators may be applied in parallel, one associated with each of N interfaces.
It should be understood that
The term “application”, or variants thereof, is used expansively herein to include routines, program modules, program, components, data structures, algorithms, and the like. Applications can be implemented on various system configurations, including single-processor or multiprocessor systems, minicomputers, mainframe computers, personal computers, handheld-computing devices, microprocessor-based, programmable consumer electronics, combinations thereof, and the like. The terminology “computer-readable media” and variants thereof, as used in the specification and claims can include volatile and/or non-volatile, removable and/or non-removable media, such as, for example, RAM, ROM, EEPROM, flash memory or other memory technology, CDROM, DVD, or other optical disk storage, magnetic tape, magnetic disk storage, or other magnetic storage devices or any other medium that can be used to store information that can be accessed by the components shown in
According to an illustrative embodiment, the computing device 500 may be implemented in any suitable computing device having a connection to the field wiring 150.
Referring to
The computing device 500 also includes a physical hard drive 580. The processor 510 communicates with the memory 530 and the hard drive 580 via, e.g., an address/data bus (not shown). The processor 510 can be any commercially available or custom microprocessor. The memory 530 is representative of the overall hierarchy of memory devices containing the software and data used to implement the functionality of the device 500. The memory 530 can include, but is not limited to the types of memory devices described above. As shown in
The I/O device drivers 570 may include various routines accessed through at least one of the OS 560 by the applications 540 to communicate with devices and certain memory components.
The applications 540 can be stored in the memory 530 and/or in a firmware as executable instructions, and can be executed by the processor 510. The applications 540 include various programs that implement the various features of the device 500. The applications 540 include, for example, applications for digitally filtering the input signal to extract the process signal, digitally filtering the input signal to extract the sinusoidal signal, and creating a binary data signal based on the extracted sinusoidal signal. These applications 540 are executed by the processor 510.
The database 550 represents the static and dynamic data used by the applications 540, the OS 560, the I/O device drivers 570 and other software programs that may reside in the memory. The database may 550 may be used to store, e.g., trigonometric tables used in digital filtering, etc.
While the memory 530 is illustrated as residing proximate the processor 510, it should be understood that at least a portion of the memory 530 can be a remotely accessed storage system, for example, a remote hard disk drive, a removable storage medium, combinations thereof, and the like. Thus, any of the data, applications, and/or software described above can be stored within the memory 530 and/or accessed via network connections to other data processing systems (not shown) that may include a local area network (LAN), a metropolitan area network (MAN), or a wide area network (WAN), for example.
The processor 510 can be any commercially available or custom microprocessor. Additionally, although illustrated and described as one processor, the processor 510 could be implemented with multiple processors, which could include distributed processors or parallel processors in a single machine or multiple machines. Further, it should be appreciated that the processor can be used in supporting a virtual processing environment. Also, the processor could include a state machine, an application specific integrated circuit (ASIC), programmable gate array (PGA) including a Field PGA, a programmable logic device (PLD) or a state machine.
The method begins at step 610 at which an analog input signal, e.g., from a current output device 100A, including a process signal modulated with a sinusoidal signal, is converted into digital form by an ADC, such as the ADC 180B. It should be appreciated that this conversion, though shown as part of the demodulation process, may be performed separately from processing by the digital demodulator 400.
At step 620, the converted input signal is digitally faltered, e.g., by the filter 165B, to extract the process signal. This step, like step 610, may be performed separately from processing by the digital demodulator 400.
At step 630, the converted input signal is digitally filtered, e.g., by filters 420A and 430B, to extract the sinusoidal signal. At step 640, a binary signal is created based on the extracted sinusoidal signal, e.g., by the difference operator 450, the low pass filter 460, and the detector 470.
It should be appreciated that, although the method is described in relation to demodulation performed by the host device, similar steps may be performed for demodulation by the field device
Those skilled in the art will also appreciate that various adaptations and modifications of the preferred and alternative embodiments described above can be configured without departing from the scope and spirit of the disclosure. Therefore, it is to be understood that, within the scope of the appended claims, the disclosure may be practiced other than as specifically described herein.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2014/045950 | 7/9/2014 | WO | 00 |
