This application relates to concurrently filed, co-pending U.S. Pat. application Ser. No. 09/232,021, “METHODS TO SECURELY CONFIGURE AN FPGA TO ACCEPT SELECTED MACROS”, by Burnham et al., owned by the assignee of this application and incorporated herein by reference. This application relates to concurrently filed, co-pending U.S. Pat. application Ser. No. 09/231,528, “METHOD TO SECURELY CONFIGURE AN FPGA USING ENCRYPTED MACRO”, by Burnham, owned by the assignee of this application and incorporated herein by reference. This application relates to concurrently filed, co-pending U.S. Pat. application Ser. No. 09/231,912, “METHODS TO SECURELY CONFIGURE AN FPGA USING MACRO MARKERS”, by Burnham et al., owned by the assignee of this application and incorporated herein by reference. This application relates to U.S. Pat. application Ser. No. 09/000,519, entitled “DECODER STRUCTURE AND METHOD FOR FPGA CONFIGURATION” by Gary R. Lawman, which is also incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
3849760 | Endou et al. | Nov 1974 | A |
5084636 | Yoneda | Jan 1992 | A |
RE34363 | Freeman et al. | Aug 1993 | E |
5237218 | Josephson et al. | Aug 1993 | A |
5237219 | Cliff | Aug 1993 | A |
5343406 | Freeman, et al. | Aug 1994 | A |
5394031 | Britton et al. | Feb 1995 | A |
5457408 | Leung | Oct 1995 | A |
5499192 | Knapp et al. | Mar 1996 | A |
5705938 | Kean | Jan 1998 | A |
5946478 | Lawman | Aug 1999 | A |
6216259 | Guccione et al. | Apr 2001 | B1 |
Number | Date | Country |
---|---|---|
0253530 | Jun 1987 | EP |
WO9220157 | Nov 1992 | WO |
WO9410754 | Nov 1993 | WO |
WO9401867 | Jan 1994 | WO |
Entry |
---|
“The Programmable Logic Data Book”, Published 1998, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 4-46 to 4-59. |
D. D. Gajski, et al., “Computer Architecture” IEEE Tutorial Manual, IEEE Computer Society, 1987, pp. v-i. |
“New IEEE Standard Dictionary of Electrical and Electronics Terms”, Fifth Edition, 1993, page 1011. |
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std. 1149.1, published Oct. 21, 1993. |
David A. Patterson and John L. Hennessy, “Computer Architecture: A Quantitive Approch”, pp. 200-201, 1990. |
Betty Prince, “Semiconductor Memories”, copyright 1983, 1991, John Wiley & Sons, pp. 149-174. |
Hodges, et al., “Analog MOS Integrated Circuits” IEEE Press, 1980, pp. 2-11. |
“The Programmable Logic Data Book”, published Sep., 1996, in its entirety and also specifically pp. 4-54 to 4-79 and 4-253 to 4-286, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124. |
“Core Solutions Data Book”, published May, 1997, pp. 2-5 to 2-13 available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124. |
“The Programmable Logic Data Book”, published 1994, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 2-105 to 2-132 and 2-231 to 2-238. |