Claims
- 1. A method of fabrication of a Fabry-Perot tunable vertical cavity device comprising first and second distributed Bragg reflector (DBR) stacks with a tunable air-gap cavity therebetween, the method comprising the steps of:
(a) forming a spacer above the first DBR stack, wherein said spacer has a structured surface formed by a recess presenting a location for the tunable air-gap cavity; (b) providing a second DBR structure and coupling it to the structured surface of the spacer so as to completely cover said recess by said second DBR structure, thus forming the air-gap cavity between the first DBR stack and the second DBR structure, and; (c) selectively applying material removal to the second DBR structure to form a mesa, presenting the second DBR stack, above a region of said recess, and to form a membrane above said recess outside said second DBR stack.
- 2. The method according to claim 1, comprising forming electrical contacts of the device on regions of the upper surface of the first DBR stack and on regions of the upper surface of the second DBR structure outside said mesa, thereby enabling deflection of said membrane by application of a tuning voltage to the electrical contacts of the device.
- 3. The method according to claim 1, wherein the second DBR structure is coupled to the structured surface of the spacer by bonding.
- 4. The method according to claim 1, wherein said second DBR structure comprises a supporting structure carrying a layer structure of the second DBR stack.
- 5. The method according to claim 4, wherein said material removal comprises etching the layers of the second DBR structure until the supporting structure is reached.
- 6. The method according to claim 4, wherein said second DBR structure comprises an intermediate layer presenting an interface between the supporting structure and the layer structure of the second DBR stack.
- 7. The method according to claim 6, wherein said material removal comprises etching the layers of the second DBR structure until said intermediate layer is reached, such layer serving as an etch stop layer.
- 8. The method according to claim 1, wherein said mesa is centered about a vertical axis passing through the center of said recess.
- 9. The method according to claim 1, wherein the recess is formed by etching all the layers of the spacer.
- 10. The method according to claim 1, wherein the depth of the recess defining the thickness of the air-gap cavity is in the range of 0.5-1.5 μm.
- 11. The method according to claim 4, wherein the lateral continuation of the supporting structure within a region thereof outside the region below the mesa forms the membrane completely covering the recess.
- 12. The method according to claim 11, wherein the thickness of the membrane is about 0.5-1.5 micron.
- 13. The method according to claim 4, wherein the second DBR stack is coupled to the structure surface of the spacer by applying a wafer fusion between the surface of the supporting structure of the second DBR structure and the structured surface of the spacer.
- 14. The method according to claim 1, comprising formation of a mesa on the bottom of said recess.
- 15. The method according to claim 14, wherein said mesa on the bottom of the recess is centered about the central vertical axis passing through the center of the recess.
- 16. The method according to claim 14, wherein said mesa on the bottom of the recess has a lateral size and a height of less than 10 and less than {fraction (1/30)}, respectively, of a certain wavelength selected as an operational wavelength of the device.
- 17. The method according to claim 1, comprising formation of an active cavity material between the first DBR stack and the spacer.
- 18. The method according to claim 17, wherein the formation of the active cavity material comprises the steps of growing a multiquantum well layer stack sandwiched between two cladding layers.
- 19. The method according to claim 17, wherein said active cavity material is fused to the surface of the first DBR stack.
- 20. The method according to claim 1, wherein the spacer is a stack formed by layers having the same thickness and composition values as in the first DBR stack.
- 21. The method according to claim 20, wherein the layers in the spacer have alternating n-type and p-type doping.
- 22. The method according to claim 1, wherein the second DBR stack comprises pairs of AlxGa1−xAs layers with different values of x.
- 23. The method according to claim 4, wherein the supporting structure comprises pairs of AlxGa1−xAs layers with different values of x.
- 24. The method according to claim 23, wherein the supporting structure comprises the same pairs of AlxGa1−xAs layers as the second DBR stack.
- 25. The method according to claim 1, wherein each of the first and second DBR stacks comprises pairs of AlxGa1−xAs layers with different values of x.
- 26. The method according to claim 23, wherein the second DBR structure comprises an etch stop layer presenting an interface between the second DBR stack and the supporting structure.
- 27. The method according to claim 23, wherein said etch stop layer is an InGaP layer.
- 28. The method according to claim 1, wherein the first DBR stack comprises 30 pairs of AlGaAs/GaAs n-type layers grown on an n-type GaAs substrate.
- 29. The method according to claim 28, wherein said spacer is a stack having six pairs of AlGaAs/GaAs layers with alternating n-type and p-type doping.
- 30. The method according to claim 29, wherein said recess is formed in the spacer by reactive plasma dry etching in Cl2—CH4—Ar and selective chemical etching in a HF—H2O solution.
- 31. The method according to claim 30, wherein the etching is stopped, when reaching the top GaAs layer of the first AlGaAs/GaAs DBR stack.
- 32. The method according to claim 1, wherein the second DBR structure contains a GaAs substrate carrying a layer structure of the second DBR stack, and a supporting structure on top of said layer structure.
- 33. The method according to claim 32, wherein the second DBR stack is coupled to the structured surface of the spacer by applying a wafer fusion between the surface of the supporting structure of the second DBR structure and the structured surface of the spacer.
- 34. The method according to claim 33, wherein the fusion is performed at 650° C. by applying a pressure of 2 bar to the fused interface.
- 35. The method according to claim 34, wherein said selective material removal comprises selectively etching the GaAs-substrate in a H2O2—NH3OH solution till reaching the first AlGaAs layer of the second DBR layer structure, said first layer acting as an etch-stop layer.
- 36. The method according to claim 35, comprising selectively etching said etch-stop layer in a HF—H2O solution.
- 37. The method according to claim 32, wherein said selective material removal comprising etching the mesa in the second DBR structure by dry etching in Cl2—CH4—Ar and selective chemical etching in a HF—H2O solution.
- 38. The method according to claim 37, wherein said etching of mesa continues until an etch stop-layer in the second DBR structure is reached, thus presenting an interface between a support structure for supporting the DBR stack in the second DBR structure.
- 39. The method according to claim 14, comprising formation of an active cavity material between the first DBR stack and the spacer.
- 40. The method according to claim 39, wherein the formation of the active cavity material comprises the steps of growing a multiquantum well layer stack sandwiched between two cladding layers.
- 41. The method according to claim 39, wherein said active cavity material is fused to the surface of the first DBR stack.
- 42. The method according to claim 39, wherein said first DBR stack is AlGaAs/GaAs, and said active cavity material comprises a multiquantum well InGaAsP/InGaAs layer stack sandwiched between two InP cladding layers.
- 43. The method according to claim 42, wherein said spacer comprises a InP layer with alternating p-n-p-n doping sandwiched between 2 InGaAsP etch-stop layers.
- 44. The method according to claim 39, wherein said mesa on the bottom of the recess is centered about the central vertical axis passing through the center of the recess.
- 45. The method according to claim 44, wherein said mesa on the bottom of the recess has a lateral size and a height of less than 10 and less than {fraction (1/30)}, respectively, of a certain wavelength selected as an operational wavelength of the device.
- 46. A tunable Fabry-Perot vertical cavity device fabricated by the method of claim 1.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of PCT/IB02/00682, filed on Mar. 8, 2002 and U.S. Ser. No 09/809,236, filed on Mar. 15, 2001, all of the same title, the applications having common inventors, and the contents of which being incorporated herein by reference thereto. Priority under 35 U.S.C. §119 is claimed to these prior applications.
Divisions (2)
|
Number |
Date |
Country |
Parent |
09809236 |
Mar 2001 |
US |
Child |
10382374 |
Mar 2003 |
US |
Parent |
PCT/IB02/00682 |
Mar 2002 |
US |
Child |
10382374 |
Mar 2003 |
US |