Patent Application
20250228057
Embodiments described herein relate to light emitting structures. More specifically, embodiments relate to micro light emitting diode (LED) based display panels.
State of the art displays for portable electronics, computers, and televisions commonly utilize glass substrates with thin film transistors (TFTs). More recently, it has been proposed to replace the TFT substrate for emissive displays such as those based on organic light emitting diodes (OLEDs) or inorganic semiconductor-based micro LEDs with a substrate including a matrix of pixel driver chips either embedded within or mounted onto the substrate, where each pixel driver chip is to switch and drive one or more LEDs.
In some aspects, the techniques described herein relate to display structures and methods of manufacture that employ an “LED first” integration sequence. In an embodiment, a display structure includes an array of pixel driver chips embedded in an insulation layer, a redistribution layer (RDL) over and in electrical contact with the array of pixel driver chips, and an array of light emitting diodes (LEDs) over and in electrical contact with the RDL. The array of LEDs may include a first group of first LEDs designed for a first wavelength emission spectrum, with each first LED including a first top surface, and a second group of second LEDs designed for a second wavelength emission spectrum different from the first wavelength emission spectrum, with each second LEDs including a second top surface. In accordance with embodiments each first top surface is coplanar with each second top surface.
In some embodiments transparent placement structures may be included, for example, to aid in throughput or light extraction. In an embodiment, the display structure includes an array of transparent placement structures onto which top surfaces of the array of LEDs are placed, with each transparent placement structure being characterized as a bank structure including a bank bottom surface, bank sidewalls, and a bank top surface. In some embodiments the bank top surface is characterized by a greater surface roughness than the bank bottom surface for each transparent placement structure. For example, the array of transparent placement structures may be formed on a passivation layer, where the bank top surface for each transparent placement structure is conformal to a roughened bottom surface of the passivation layer.
The manufacture sequences in accordance with embodiments are compatible with both vertical LEDs and horizontal LEDs. The different groups of LEDs can also have different thicknesses, while maintaining coplanarity of their top surfaces. In an exemplary vertical LED display structure, a transparent electrode layer may span over the array of transparent placement structures, where the top surfaces of the array of LEDs are in electrical contact with the transparent electrode layer. For example, the transparent electrode layer may span over the bank bottom surface and the bank sidewalls of each transparent placement structure. Furthermore, the bank bottom surface of each transparent placement structure may be coplanar. In an exemplary horizontal LED display structure, the RDL may include an array of contact via line pairs in electrical contact with the bottom surfaces of the array of LEDs such that each contact via line pair is in electrical contact with a corresponding LED.
The pixel driver chips in accordance with embodiments may also be embedded face up or face down within the display structure. In an embodiment, each pixel driver chip is bonded to the RDL with a plurality of solder bumps. For example, this may be a face down configuration with the contact pads of the pixel driver chips facing the RDL. In an embodiment, each pixel driver chip includes a front side with a plurality of contact pads facing away from the RDL. This may be a face up configuration. In either configuration a plurality of vertical interconnects can extend through an insulation layer within which the pixel driver chips are embedded. For example, these may be used to electrically connect the array of pixel driver chips with the RDL, as well as to electrically connect to other system components.
The RDL in accordance may be fabricated using suitable techniques, including thin film techniques. In an embodiment, the RDL includes a plurality of wiring layers forming a plurality of redistribution lines and a plurality of contact via lines, and a plurality of interlayer dielectric (ILD) layers separating levels of redistribution lines of the plurality of redistribution lines. The plurality of contact line vias may extend through one or more ILD layers of the plurality of ILD layers. For example, a first group of contact via lines may extend through a thickness of at least two ILD layers, through a thickness of at least three ILD layers, or more. In some embodiments thin film fabrication sequences may be utilized so that the contact via lines extend through via openings through the one or more ILD layers and form an outline conforming to the via openings.
The display structures and fabrication sequences are also compatible with hybrid structures in which the RDL additionally includes a thin film transistor (TFT) layer including an array of TFTs coupled with the array of LEDs and the array of pixel driver chips. The TFTs can be suitable transistors and can include a combination of transistors including both low temperature polycrystalline silicon (LTPS) TFTs and oxide TFTs.
Embodiments describe display structures and methods of manufacture that employ an “LED first” integration sequence in which an array of LEDs (including multiple different groups of LEDs designed for different wavelength emission spectra) is first integrated followed by subsequent completion of a redistribution layer (RDL) for electrical routing, and the integration of an array of pixel driver chips. In accordance with embodiments the display structure fabricated using such techniques can align the top surfaces of each LED so that they are coplanar. In some embodiments selective placement structures including an existing planar surface are first fabricated, followed by mass transfer of the LEDs from one or more donor substrates to the selective placement structures. For example, this can be accomplished with a pick and place tool with an array of transfer heads.
In one aspect, embodiments described herein may facilitate emissive light extraction. For example, the planar top surfaces of the LEDs can benefit display Mura effect. Furthermore, a uniform flat and roughened surface can be provided over the planar top surfaces of the LEDs to increase light extraction. Additional structures can also be integrated to enhance light extraction and viewing angle such as distributed Bragg reflector (DBR), or metal routing within the RDL.
In one aspect, the receiving structures (e.g., selective placement structures) and LED transfer sequences can improve total thickness variation (TTV) of the display structures, and thereby overall assembly yield. The scalable architecture is also compatible with both vertical and horizonal LEDs, and topography provided by the selective placement structures can facilitate multi place transfer sequences from a single transfer head array.
In another aspect, the processing sequences described herein facilitate panel level passivation techniques, where key encapsulation structures are formed earlier in the process flow, easing integration challenges such as TTV and topography of the stack-up.
In another aspect, the processing sequences described herein facilitate RDL formation in which contact via lines extend through the thickness of multiple interlayer dielectric (ILD) layers, which can mitigate routing complexity and provide space savings.
In yet another aspect, the processing sequences described herein can avoid thermal budgets by placing the pixel driver chips last in the stack-up. Furthermore, the integration techniques and RDL formation are also compatible with TFT integration for a hybrid TFT and pixel driver chip architecture where the TFT layers can be fabricated prior to pixel driver chip integration, removing a thermal budget constraint for TFT fabrication. In such a configuration the pixel driver chips may provide digital functionality with the TFT layer including local subpixel circuitry to provide analog functionality. Additional sensing dies and chipsets can also be integrated using the processing sequences described herein, including laser, photodiode, readout integrated circuits, and image sensors with wafer level micro-optics.
In yet another aspect, the processing sequences described herein allow for peripheral electronic components such as a display timing controller (TCON), which is typically located off panel, can be attached without using conventional chip on film (COF) techniques, therefore eliminating conventional bend tail further leading to potential border reduction.
In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
The terms “over”, “to”, “between”, “spanning” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over”, “spanning” or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The terms “micro” device or “micro” LED as used herein may refer to the descriptive size of certain devices or structures in accordance with embodiments. As used herein, the term “micro” is meant to refer to the scale of 1 to 300 μm. For example, each micro LED may have a maximum length or width of 1 to 300 μm, 1 to 100 μm, or less. In some embodiments, the micro LEDs may have a maximum length and width of 20 μm, 10 μm, or 5 μm. However, it is to be appreciated that embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger, and possibly smaller size scales.
Referring now to
In accordance with all embodiments described herein the pixel driver chips 150 may be located within the display panel 103 and may be positioned face up (e.g. with terminals facing up towards the LEDs 104), positioned face down (e.g. with terminals facing away from the LEDs), or both (with terminals on both top and bottom sides).
In particular, the arrangement of pixel driver chips 150 in accordance with embodiments can remove the requirement for driver ledges on the edges of a display panel 103. As a result, the display panel 103 may have reduced borders, or zero borders outside of the display area. An external control circuit 105 may be attached with the display panel 103 to supply various control signals, video signals, and power supply voltage to the display panel 103. The control circuit 105 may include a timing controller (TCON). Additional system components can also be connected to the display panel along with the control circuit, such as a host system on chip (SOC), power management integrated circuit (PMIC), level shifters, touch screen controller, additional passives, etc. Generally, the control circuit 105 may be coupled to an edge of the display panel 103, though may also be coupled to a back side of the display panel 103 in accordance with embodiments. Bus columns of global routing lines 102 may extend from the control circuit 105 to supply global signals to the display panel 103. For example, the global routing lines 102 may include at least data clock lines, emission clock lines, and vertical selection token (VST) lines. The global routing lines are coupled to a plurality of “hybrid” pixel driver chips, and together form a backbone of the display. The corresponding backbone hybrid pixel driver chips receive the global signals and then transmit manipulated signals to their corresponding rows of row lines 106 connected to the other pixel driver chips 150 within the same row. For example, the global data clock and emission clock signals may be converted to manipulated signals and transmitted to the row of pixel driver chips 150 along manipulated data clock lines and manipulated emission clock lines. For example, the manipulated signals may include only the necessary information for the particular row.
The system also includes a power module 780 (e.g., flexible batteries, wired or wireless charging circuits, etc.), a peripheral interface 708, and one or more external ports 790 (e.g., Universal Serial Bus (USB), HDMI, Display Port, and/or others). In one embodiment, the portable electronic device 700 includes a communication module 712 configured to interface with the one or more external ports 790. For example, the communication module 712 can include one or more transceivers functioning in accordance with IEEE standards, 3GPP standards, or other communication standards, 4G, 5G, etc. and configured to receive and transmit data via the one or more external ports 790. The communication module 712 can additionally include one or more
WWAN transceivers configured to communicate with a wide area network including one or more cellular towers, or base stations to communicatively connect the portable electronic device 700 to additional devices or components. Further, the communication module 712 can include one or more WLAN and/or WPAN transceivers configured to connect the portable electronic device 700 to local area networks and/or personal area networks, such as a Bluetooth network.
The portable electronic device 700 can further include a sensor controller 770 to manage input from one or more sensors such as, for example, proximity sensors, ambient light sensors, or infrared transceivers. In one embodiment the system includes an audio module 731 including one or more speakers 734 for audio output and one or more microphones 732 for receiving audio. In embodiments, the speaker 734 and the microphone 732 can be piezoelectric components. The portable electronic device 700 further includes an input/output (I/O) controller 722, a display structure 110, and additional I/O components 718 (e.g., keys, buttons, lights, LEDs, cursor control devices, haptic devices, and others). The display structure 110 and the additional I/O components 718 may be considered to form portions of a user interface (e.g., portions of the portable electronic device 700 associated with presenting information to the user and/or receiving inputs from the user).
While not required to achieve the coplanar surfaces, in some embodiments the top surfaces of the array of LEDs 104 are placed onto a corresponding array of transparent placement structures 122. Each transparent placement structure 122 can be a bank structure for example, including a bank bottom surface 124 onto which the LEDs 104 are placed, bank sidewalls 126, and a bank top surface 128. The bank sidewalls 126 may be straight sidewalls (e.g. vertical) or angled sidewalls as shown, which may aid in deposition of subsequent conformal layers. The bank top surface 128 may optionally be characterized by a greater surface roughness, such as average surface roughness (Ra), than the bank bottom surface 124 for the transparent placement structure 122. For example, this can be accomplished when forming the array of transparent placement structures 122 on an optional passivation layer 130, with the bank top surface 128 being conformal to a roughened bottom surface 132 of the passivation layer 130.
Generally, the LEDs in accordance with embodiments may be vertical micro LEDs including a p-n diode, a top surface 116 (top electrode side), a bottom contact 134 (bottom electrode side) and sidewall of the p-n diode. For example, the p-n diodes may be formed of inorganic semiconductor materials, such as III-V or II-VI materials. Exemplary materials include nitride-based semiconductors (e.g. GaN) and phosphorous-based semiconductors (e.g. AlInGaP, InGaP). Alternatively, the LEDs may be horizontal micro LEDs.
In the particular embodiment illustrated in
The RDL 120 in accordance with embodiments may include a plurality of redistribution lines 138, contact via lines 140, and a plurality of interlayer dielectric (ILD) layers 142 separating the various metal layer levels of the redistribution lines 138. The RDL 120 may additionally include a dielectric layer 144, or passivation layer, that is formed around the array LEDs and the selective placement structures 122 to secure the LEDs in place. The dielectric layer 144 may be formed of a suitable insulating material, and may be formed using a suitable technique, such as slot coating, spin coating, vapor deposition, etc. in order to cover the array of LEDs and substantially fill the gaps therebetween. The ILD layers 142 may be formed of suitable materials including oxides (e.g. SiOx), nitrides, polymers, etc. The redistribution lines 138 and contact via lines 140 may be metallization layers such as copper, aluminum, etc. In accordance with embodiments, RDL 120 includes one or more of the plurality global signal lines and power lines. In the illustrated embodiments, the redistribution lines 138 and contact via lines 140 are formed using thin film techniques, and the contact via lines 140 may extend into via openings in the ILD layers 142 and dielectric layer 144. When utilizing thin film techniques, the contact via lines 140 may form an outline conforming to the via openings. Alternatively, other plating techniques can be utilized so that metal vias completely fill the via openings, though this may be accompanied by additional process operations, including metal planarization. In an embodiment, the plurality of contact via lines 140 extend through one or more ILD layers as shown in area B where a contact via line extends through at least two ILD layers 142, and as shown in area C where a contact via line extends through at least three ILD layers 142. The contact via lines 140 may also be used to make electrical contact with the transparent electrode layer 135 to make electrical contact with the top surfaces 116 of one or more LEDs 104.
Additional structures may be included such as, but not limited to, a distributed Bragg reflector (DBR) layer 160 over the optional passivation layer 130, lower passivation layer 166, and cover plate 168. For example, the DBR layer 160 may include alternating layers 162, 164 such as SiNx, SiOx, SiNx, SiOx. The layers of DBR layer 160 may also function as a passivation layer. Lower passivation layer 166 can additionally be formed of a transparent material. In some embodiments lower passivation layer 166 is formed of a transparent polymer material or glass that can be embossed to form a roughened bottom surface 132 for light extraction. Other materials, and roughening techniques may also be utilized. Cover plate 168 can also be formed of a transparent material such as glass.
In the particular embodiment illustrated the pixel driver chips 150 are flip chip bonded with contact pads 152 facing the RDL 120. For example, the contact pads 152 may be bonded to the redistribution lines 138 (or landing pads formed therewith) using solder bumps 154. Alternatively, referring briefly to
Referring now to
It is to be appreciated that while the example illustrated in
Referring now to
The selective placement structures 122 in accordance with embodiments can enable a single-pick-multi-place transfer process. Referring now to
Referring now to
Still referring to
While the selective placement structures 122 in accordance with embodiments can be utilized to enhance placement throughput they are not required for the “LED first” integration sequence. In the variation illustrated in
Referring now to
The RDL 120 can then be completed as shown in
Referring now to
The back side routing 170 and vertical interconnects 115 illustrated in
Following encapsulation of the pixel driver chips 150 and optional back side routing 170 a back side carrier substrate 180 can be formed. For example, a polymer or glass substrate can be attached with an adhesive to provide some structural integrity and protection from ambient.
Up until this point the fabrication sequences and variations described and illustrated have presumed the bottom side (front side) cover plate 168 and optics such as lower passivation layer 166 and DBR layer 160 are formed at the initial fabrication stages. In the variation illustrated in
In yet another process variation, as shown in
The “LED first” fabrication sequences described herein can facilitate the fabrication of display structures with maximum display areas, and also allow for peripheral electronic components such as a display timing controller (TCON), which is typically located off panel, to be attached without using conventional chip on film (COF) techniques, therefore eliminating conventional bend tail further leading to potential border reduction. More specifically the peripheral electronic components can be integrated close in time with the pixel driver chips 150. Referring to
Referring now to
Any of the plurality of global signal lines and power lines may also, or alternatively, be formed in the TFT layer 190. In an embodiment, the TFT layer 190 is used primarily for local routing. The TFT layer 190 may include an array of TFTs, capacitors, and electrical routing. For example, the TFTs may be silicon or oxide transistors. For example, the array of TFTs may include both low temperature polycrystalline silicon (LTPS) TFTs and oxide TFTs. Similar to RDL 120, the TFT layer 190 may additionally include a plurality of metal routing lines 192 and dielectric layers 194. Routing lines 192 (or vias 196 thereof) may contact the source/drains of the TFTs.
In operation, the pixel driver chips may update with multiplexing and row sharing, while a mostly passive TFT layer 190 is set to the LED driving current value and is always on until it is reprogrammed. This may enable digital driving at higher multiplexing ratios than possible with local passive matrix addressing, and with reduced power consumption and complexity of active matrix addressing.
In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming a bottom emission display structure with an “LED first” fabrication sequence. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.
This application claims the benefit of priority of U.S. Provisional Application No. 63/618,813, filed Jan. 8, 2024, which is herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63618813 | Jan 2024 | US |
