Patent Application
20230246129
The present disclosure generally relates to light emitting diode, and more particularly, to a micro light emitting diode (LED), a micro-LED array panel, and a manufacturing method thereof.
Inorganic micro pixel light emitting diodes, also referred to as micro light emitting diodes, micro-LEDs or μ-LEDs, are of increasing importance because of their use in various applications including self-emissive micro-displays, visible light communications, and optogenetics. The micro-LEDs exhibit higher output performance than conventional LEDs due to better strain relaxation, improved light extraction efficiency, and uniform current spreading. The micro-LEDs also exhibit improved thermal effects, fast response rate, larger work temperature range, higher resolution, color gamut and contrast, and lower power consumption, and can be operated at higher current density compared with conventional LEDs.
The inorganic micro-LEDs are conventionally III-V group epitaxial layers formed as multiple mesas. A space is formed between the adjacent micro-LEDs in the conventional micro-LEDs structures to avoid carriers in the epitaxial layer spreading from one mesa to an adjacent mesa. However, the space which is formed between the adjacent micro-LEDs can reduce an active light emitting area and decrease light extraction efficiency. If there is no space between the adjacent micro-LEDs, the active light emitting area would be increased and the carriers in the epitaxial layer would spread laterally to the adjacent mesa, which reduces the light emitting efficiency of the micro-LED. Furthermore, if there is no space formed between the adjacent mesas, cross talk will be produced between the adjacent micro-LEDs, which would interfere with micro-LEDs operation.
However, smaller micro-LEDs with higher current densities will experience red-shift, lower maximum efficiency, and inhomogeneous emission at high current density, which has been attributed to fabrication process damage that results in degraded electrical injection. In addition, the peak external quantum efficiencies (EQEs) and internal quantum efficiency (IQE) are largely decreased with decreasing chip size. The decreased EQE appears due to nonradiative recombination caused by etching damage and the decreased IQE is attributed to poor current injection and electron leakage current of micro-LEDs.
The above discussion is only provided to assist in understanding the technical problem overcome by the present disclosure, and does not constitute an admission that the above is prior art.
Embodiments of the present disclosure provide a micro-LED. The micro-LED includes a first type semiconductor layer; and a light emitting layer formed on the first type semiconductor layer; wherein the first type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending up through the first type semiconductor layer and extending up into at least part of the light emitting layer; and the ion implantation fence is formed around the trench and the trench is formed around the mesa structure; wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.
Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method includes providing an epitaxial structure, wherein the epitaxial structure includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer sequentially from top to bottom; patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a bottom contact on the mesa structure; and performing an ion implantation process into the fence to form a first ion implantation fence.
Embodiments of the present disclosure provide micro-LED array panel. The micro-LED array panel includes a plurality of the above-described micro-LEDs.
Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying figures. Various features shown in the figures are not drawn to scale.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the invention. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the invention as recited in the appended claims. Particular aspects of the present disclosure are described in greater detail below. The terms and definitions provided herein control, if in conflict with terms and/or definitions incorporated by reference.
The present disclosure provides a micro-LED which can avoid nonradiative recombination at sidewalls of a mesa according to a structure of a semiconductor layer and continuously formed light emitting layer. Furthermore, compared with conventional micro-LEDs, a space between adjacent mesas can be decreased largely due to an ion implantation fence. Therefore, the integration level of the micro-LEDs in a chip is increased and the active light emitting efficiency is improved. Furthermore, the micro-LED provided by the present disclosure can also increase the active light emitting area and improve the image quality.
Referring to
A conductive type of the first type semiconductor layer 110 is different from a conductive type of the second type semiconductor layer 120. In some embodiments, the conductive type of the first type semiconductor layer 110 is P type, and the conductive type of the second type semiconductor layer 120 is N type. In some embodiments, the conductive type of the second type semiconductor layer 120 is P type, and the conductive type of the first type semiconductor layer 110 is N type. For example, a material of the first type semiconductor layer 110 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
The first type semiconductor layer 110 includes a mesa structure 111, a trench 112 and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are annular around the mesa structure 111.
The ion implantation fence 113 includes a light absorption material for absorbing light from the mesa structure 111. A conductive type of the light absorption material is the same as the conductive type of the first type semiconductor layer 110. Preferably, the light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. Additionally, the ion implantation fence 113 is formed at least by implanting ions into the first type semiconductor layer 110. Preferably, ions implanted into the first type semiconductor layer 110 to form the ion implantation fence 113 are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
Furthermore, the width of the ion implantation fence 113 is not greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is not greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is not greater than 200 nm, the diameter of the mesa structure 111 is not greater than 2500 nm, and the thickness of the first type semiconductor layer 110 is not greater than 300 nm.
In some embodiments, the width of the trench 112 is not greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is not greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the trench 112 is not greater than 200 nm.
As shown in
There is no limitation for a depth of the trench 112. The trench 112 can extend up through the first type semiconductor layer 110, the emitting layer 130, even into the second type semiconductor layer 120. In the variant shown in
In the first exemplary micro-LED, the top surface of the ion implantation fence 113 is lower than the top surface of the first type semiconductor layer 110. Thus, the ion implantation fence 113 cannot reach the light emitting layer 130. The top surface of the ion implantation fence 113 can be formed at any position within the first type semiconductor layer 110. Preferably, as shown in
Additionally, the bottom surface of the ion implantation fence 113 can be formed at any position, higher or lower than the bottom surface of the first type semiconductor layer 110. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first type semiconductor layer 110. As shown in
In some embodiments, as shown in
In this embodiment, an integrated circuit (IC) backplane 190 is formed under the first type semiconductor layer 110 and is electrically connected with the first type semiconductor layer 110 via a connection structure 150. As shown in
The micro-LED further includes a bottom contact 160. The bottom contact 160 is formed at the bottom of the first type semiconductor layer 110. An upper surface of the connection structure 150 is connected with the bottom contact 160 and the bottom surface of the connection structure 150 is connected with the IC backplane 190. As shown in
In some embodiments, the micro-LED further includes a top contact 180 and a top conductive layer 170. The top contact 180 is formed on the top of the second type semiconductor layer 120. The top conductive layer 170 is formed on the top of the second type semiconductor layer 120 and the top contact 180. The conductive type of the top contact 180 is the same as the conductive type of the second type semiconductor layer 120 For example, in some embodiments, the conductive type of the second type semiconductor layer 120 is N type and the conductive type of the top contact 180 is N type. In some embodiments, the conductive type of the second type semiconductor layer 120 is P type and the conductive type of the top contact 180 is P type. The top contact 180 is made of metal or metal alloy, such as, AuGe, AuGeNi, etc. The top contact 180 is used for forming an ohmic contact between the top conductive layer 170 and the second type semiconductor layer 120, to optimize the electrical properties of the micro-LED. The diameter of the top contact 180 is about 20˜50 nm and the thickness of the top contact 180 is about 10˜20 nm.
Referring to
In step 502: referring to
As shown in
In some embodiments, the first type semiconductor layer 610 is etched and the etching is stopped on the light emitting layer 630, to avoid the light emitting layer 630 being etched in the patterning process. Referring back to
In some embodiment, the step 502 further includes: etching the first type semiconductor layer and the light emitting layer in sequence, and stopping the etching in the light emitting layer. Referring back to
In some embodiments, the step 502 further includes: etching the first type semiconductor layer 610, the light emitting layer 630, and the second type semiconductor layer 620 in sequence, and stopping the etching in the second type semiconductor layer 620. Referring back to
The first type semiconductor layer 610, the light emitting layer 630, and the second type semiconductor layer 620 are etched by a conventional dry etching process, such as, a plasma etching process, which can be understood be those skilled in the field.
In step 503: referring to
Before the bottom contact 660 is deposited, a first protective mask (not shown) is used to protect an area where the bottom contact 660 will not be formed. Then, the material of the bottom contact 660 is deposited on the first protective mask and on the first type semiconductor layer 610 by a conventional vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. After the deposition process, the first protective mask is removed from the first type semiconductor layer 610 and the material on the first protective mask is also removed with the first protective mask to form the bottom contact 660 on the mesa structure 611.
In step 504: referring to
In combination with
In step 505: referring to
The bottom isolation layer 640 is formed on sidewalls and a bottom surface of the trench 612. As shown in
In step 506: referring to
In step 507: referring to
In step 508: referring to
In step 509: referring to
In step 510: referring to
A micro-LED array panel is further provided by some embodiments of the present disclosure. The micro-LED array panel includes a plurality of micro-LEDs as described above and shown in
A conductive type of the first type semiconductor layer 710 is different from a conductive type of the second type semiconductor layer 720. For example, in some embodiments, the conductive type of the first type semiconductor layer 710 is P type, and the conductive type of the second type semiconductor layer 720 is N type. In some embodiments, the conductive type of the second type semiconductor layer 720 is P type, and the conductive type of the first type semiconductor layer 710 is N type. The thickness of the first type semiconductor layer 710 is greater than the thickness of the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
The first type semiconductor layer 710 includes multiple mesa structures 711, multiple trenches 712, and multiple ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fence 713 is lower than the top surface of the first type semiconductor layer 710. Thus, the top surface of the trench 712 does not contact to the light emitting layer 730. The relationship of the top surface of the ion implantation fence 713, the top surface of the first type semiconductor layer 710, the top surface of the trench 712 can be seen in the micro-LED shown in
In some embodiments, the space between the adjacent sidewalls of the adjacent ones of the mesa structure 711 can be adjusted. For example, in some embodiments, the space between the adjacent sidewalls of the mesa structures 711 is not greater than 50% of the diameter of the mesa structure 711. In some embodiments, the space between the adjacent sidewalls of the mesa structures 711 is not greater than 30% of the diameter of the mesa structure 711. Preferably, the space between the adjacent sidewalls of the mesa structure 711 is not greater than 600 nm. Additionally, in some embodiments, the width of the ion implantation fence 713 can be adjusted. For example, the width of the ion implantation fence 713 can be not greater than 50% of the diameter of the mesa structure 711. In some embodiments, the width of the ion implantation fence 713 can be not greater than 10% of the diameter of the mesa structure 711. Preferably, in the micro-LED array panel, the width of the ion implantation fence 713 is not greater than 200 nm.
In this embodiment, the micro-LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on the top of a second type semiconductor layer 920. The top conductive layer 970 is formed on the top of the second type semiconductor layer 920 and the top contact 980. A conductive type of the top contact 980 is the same as a conductive type of the second type semiconductor layer 920. For example, in some embodiments, the conductive type of the second type semiconductor layer 920 is N type and the conductive type of the top contact 980 is N type. In some embodiments, the conductive type of the second type semiconductor layer 920 is P type and the conductive type of the top contact 980 is P type. The top contact 980 is made of metal or metal alloy, such as, AuGe, AuGeNi, etc. The top contact 980 is used for forming ohmic contact between the top conductive layer 970 and the second type semiconductor layer 920, to optimize the electrical properties of the micro-LEDs. The diameter of the top contact 980 is about 20˜50 nm and the thickness of the top contact 980 is about 10˜20 nm.
The micro-LED array panel can be manufactured by the method 500 as shown in
The second type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is higher than the bottom surface of the second type semiconductor layer 1020. Furthermore, the ion implantation fence 1023 is formed around the trench 1022 and the trench 1022 is formed around the mesa structure 1021. The electrical resistance of the ion implantation fence 1023 is higher than the electrical resistance of the mesa structure 1021.
The ion implantation fence 1023 includes a light absorption material for absorbing light from the mesa structure 1021. A conductive type of the light absorption material is the same as the conductive type of the second type semiconductor layer 1020. Preferably, the light absorption material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or p-AlGaN. Additionally, the ion implantation fence 1023 is formed at least by implanting ions into the second type semiconductor layer 1020. Preferably, the ion type implanted into the second type semiconductor layer 1020 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
Furthermore, the width of the ion implantation fence 1023 is not greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is not greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is not greater than 200 nm. The diameter of the mesa structure 1021 is not greater than 2500 nm. The thickness of the second type semiconductor layer 1020 is not greater than 100 nm.
In some embodiments, the width of the trench 1022 is not greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the trench 1022 is not greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the second trench 1022 is not greater than 200 nm.
There is no limitation on the depth of the trench 1022. In some embodiments, the trench 1022 can extend down through the bottom surface of the second type semiconductor layer 1020 but cannot reach the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and can reach the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and extend into the interior of the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the light emitting layer 1030. Furthermore, the trench 1022 can extend down through the second type semiconductor layer 1020 and the light emitting layer 1030, and extend down into the interior of the first type semiconductor layer 1010.
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, the bottom surface of the ion implantation fence 1023 is higher than the bottom surface of the trench 1022. The bottom surface of the ion implantation fence 1023 can be formed at any position within the first type semiconductor layer 1010.
Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any position. Preferably, the top surface of the ion implantation fence 1023 is aligned with the top surface of the second type semiconductor layer 1020. In some embodiments, as shown in
In some embodiments, as show in
In this embodiment, an integrated circuit (IC) backplane 1090 is formed under the first type semiconductor layer 1010 and is electrically connected with the first type semiconductor layer 1010 via a connection structure 1050. As shown in
Additionally, in some embodiments, the micro-LED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on the top of the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020 and the top surface of the top contact 1080, and covers sidewalls and the bottom of the trench 1022. Preferably, a dielectric layer 1071 is formed on the sidewalls and bottom surface of the trench 1022. A conductive type of the top contact 1080 is the same as a conductive type of the second type semiconductor layer 1020. For example, the conductive type of the second type semiconductor layer 1020 is N type and the conductive type of the top contact 1080 is N type. The top contact 1080 is made of metal or metal alloy, such as, AuGe, AuGeNi, etc. The top contact 1080 is used for forming an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020, to optimize the electrical properties of the micro-LED. The diameter of the top contact 1080 is about 20˜50 nm and the thickness of the top contact 1080 is about 10˜20 nm.
Referring to
Referring to
Preferably, before turning upside down the epitaxial structure, a bottom contact layer 1560 used as the bottom contact is deposited on the top surface of the first type semiconductor layer 1510. Then, a metal bonding layer which is used as a connection structure 1550 is deposited on the top surface of the bottom contact layer 1560.
In step 1402: referring to
In step 1403: referring to
In some embodiments, the second type semiconductor layer 1520 is etched down to the surface of the light emitting layer 1530, to avoid the light emitting layer 1530 being etched in the patterning process. For example, referring back to
In some embodiments, step 1403 further includes: etching the second type semiconductor layer 1520 and the light emitting layer 1530 in sequence, and stopping the etching process in the light emitting layer 1530. For example, referring back to
In some embodiments, step 1403 further includes: etching the second type semiconductor layer, the light emitting layer, and the first type semiconductor layer 1510 in sequence, and stopping the etching process in the first type semiconductor layer. Referring back to
The second type semiconductor layer 1520 is etched by a conventional dry etching process, such as, a plasma etching process, which can be understood be those skilled in the field.
In step 1404: referring to
In step 1405: referring to
In some embodiments, the top contact 1580 can be formed after the ion implantation process.
In step 1406: referring to
Alternatively, a dielectric layer can be formed on the sidewalls and the bottom of the trench 1522 before depositing the top conductive layer 1570. More particularly, before forming the top conductive layer 1570, a dielectric layer 1571 is formed on the sidewall and the bottom of the trench 1522. Furthermore, the dielectric layer 1571 is formed on the sidewalls of the first type semiconductor layer 1510, the light emitting layer 1530 and the mesa structure 1521 in the trench 1522. The top conductive layer 1570 is formed on the surface of the dielectric layer 1571 extending into the trench 1522, on the top of the mesa structure 1521, and the top of the ion implantation fence 1523. Referring back to
Referring back to
When the connection structure 1550 is a connection pillar, step 1402 can be replaced with the following step 1402′: depositing a bottom contact on the first type semiconductor layer; depositing a bottom isolation layer on the whole substrate; patterning the bottom isolation layer to expose the bottom contact; depositing metal material on the whole substrate; grinding the top of the metal material to the top of the bottom isolation layer, to form a connection pillar; and bonding the connection pillar with an IC backplane. The epitaxial structure is turned upside down, and the connection pillar is bonded with a contact pad of the IC backplane by a metal bonding process. Step 1402′ can further understood by also referring to the description of
A micro-LED array panel is further provided according to some embodiments of the present disclosure. The micro-LED array panel includes a plurality of micro-LEDs as described above with reference to
The second type semiconductor layer 1620 includes multiple mesa structures 1621, multiple trenches 1622, and multiple ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. The bottom surface of the ion implantation fence 1623 is higher than the bottom surface of the second type semiconductor layer 1620.
Furthermore, in some embodiments, as shown in
In some embodiments, the space between the adjacent sidewalls of adjacent ones of the mesa structures 1621 can be adjusted. For example, in some embodiments, the space between the adjacent sidewalls of the mesa structures 1621 is not greater than 50% of the diameter of the mesa structure 1621. In some embodiments, the space between the adjacent sidewalls of the mesa structures 1621 is not greater than 30% of the diameter of the mesa structure 1621. Preferably, the space between the adjacent sidewalls of the mesa structures 1621 is not greater than 600 nm. Additionally, in some embodiments, the width of the ion implantation fence 1623 can be adjusted. For example, in some embodiments, the width of the ion implantation fence 1623 is not greater than 50% of the diameter of the mesa structure 1621. In some embodiments, the width of the ion implantation fence 1623 is not greater than 10% of the diameter of the mesa structure 1621. Preferably, in the micro-LED array panel, the width of the ion implantation fence 1623 is not greater than 200 nm.
Furthermore, referring back to
Additionally, further details regarding the features of the micro-LED and the ion implantation fence in the micro-LED array panel can be understood by also referring to the micro-LEDs as shown in
The micro-LED array panel shown in
The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912 and a first ion implantation fence 1913. The first trench 1912 extends up through the top surface of the first type semiconductor layer 1910. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922 and a second ion implantation fence 1923 separated from the second mesa structure 1921.
In some embodiments, referring back to
Furthermore, in some embodiments, the second trench 1922 extends down through the bottom of the second type semiconductor layer 1920 and the bottom of the second trench 1922 is lower than the bottom of the second type semiconductor layer 1920. Thus, the bottom of the second trench 1922 contacts to the light emitting layer 1930. Referring back to
Referring to
In some embodiments, the center of the first mesa structure 1911 is aligned with the center of the second mesa structure 1921. The center of the first trench 1912 is aligned with the center of the second trench 1922, and the center of the first ion implantation fence 1913 is aligned with the center of the second ion implantation fence 1923.
A bottom view of the first type semiconductor layer 1910 is similar to the bottom view shown in
The relationship of the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912 and the top surface of the first type semiconductor layer 1910 is the same as that of the variants of the micro-LED in Embodiment 1 shown in
The relationship of the bottom of the second ion implantation fence 1923, the bottom of the second trench 1922 and the bottom of the second type semiconductor layer 1920 is the same as that of the variants of the micro-LED in embodiment 2 shown in
The micro-LED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on the top of a second type semiconductor layer 2020 and the top conductive layer 2070 is formed on the top of the second type semiconductor layer 2020. The top conductive layer 2070 covers the top contact 2080 and covers the sidewalls of the second trench 2022. Further detail regarding the top contact 2080 and the top conductive layer 2070 can be found by referring to the description of Embodiment 2, which will not be further described here.
Additionally, further details regarding the micro-LED, the first ion implantation fence 2013, and the second ion implantation fence 2023 can be found by referring to description of Embodiment 1 and Embodiment 2, which will not be further described here.
In Process I: the first type semiconductor layer is patterned, and then ions are implanted into the first type semiconductor layer, to form a first ion implantation fence.
In Process II: the second type semiconductor layer is patterned, and then ions are implanted into the second type semiconductor layer, to form a second ion implantation fence.
Referring to
For Process I, the steps 2101-2109 are similar to the steps 501-509 of method 500, respectively, as shown in
In step 2102: referring to
In step 2103: referring to
In step 2104: referring to
In step 2105: referring to
In some embodiments, referring to
In step 2106: referring to
In step 2107: referring to
In step 2108: referring to
In step 2109: referring to
In step 2111: referring to
In step 2112: referring to
In step 2113: referring to
In some embodiments, as shown to
The bottom isolation layer 2340 is formed on the sidewalls and the top of the first trench 2312, and the dielectric layer 2371 is formed on the sidewalls and the bottom of the second trench 2322. The thickness of the bottom isolation layer extending into the first trench 2312 depends on a position of the bottom of the second trench 2322 and a position of the top of the first trench 2312. The thickness of the dielectric layer 2371 extending into the second trench 2322 depends on a position of the bottom of the second trench 2322 and a position of the top of the first trench 2312.
The top contact and the bottom contact can be formed in the micro-LED according to some embodiments of the present disclosure, which will not be further described here.
Further details of the Process I can be found by reference to the description of steps 501-509 for the Embodiment 1. Further details of the Process II can be found by reference to the description of steps 1403-1406 for the Embodiment 2, which will not be further described here.
A micro-LED array panel is further provided according to some embodiments of the present disclosure. The micro-LED array panel includes a plurality of micro-LEDs as described above and shown in
The first type semiconductor layer 2410 includes multiple first mesa structures 2311, multiple first trenches 2412 and multiple first ion implantation fences 2413 separated from the first mesa structures via the first trenches 2412. The top surface of the first ion implantation fence 2413 is lower than the top surface of the first type semiconductor layer 2410. Referring back to
The second type semiconductor layer 2420 includes multiple second mesa structures 2421, multiple second trenches 2422 and multiple second ion implantation fences 2423 separated from the second mesa structures 2421 by the second trenches 2422. The bottom surface of the second ion implantation fence 2423 is higher than the bottom surface of the second type semiconductor layer 2420. A top view of the micro-LED array panel is similar to the top view shown in
In some embodiments, the space between the adjacent sidewalls of the first mesa structures 2411 can be adjusted. For example, in some embodiments, the space between the adjacent sidewalls of the first mesa structures 2411 is not greater than 50% of the diameter of the first mesa structure 2411. In some embodiments, the space between the adjacent sidewalls of the first mesa structures 2411 is not greater than 30% of the diameter of the first mesa structure 2411. Preferably, the space between the adjacent sidewalls of the first mesa structures 2411 is not greater than 600 nm. Additionally, in some embodiments, the width of the first ion implantation fence 2413 can be adjusted. For example, in some embodiments, the width of the first ion implantation fence 2413 is not greater than 50% of the diameter of the first mesa structure 2411. In some embodiments, the width of the first ion implantation fence 2413 is not greater than 10% of the diameter of the first mesa structure 2411. Preferably, in some embodiments, in the micro-LED array panel, the width of the first ion implantation fence 2413 is not greater than 200 nm. The space between the adjacent sidewalls of the second mesa structure 2421 is not greater than 50% of the diameter of the second mesa structure 2421. In some embodiments, the space between the adjacent sidewalls of the second mesa structure 2421 is not greater than 30% of the diameter of the second mesa structure 2421. Preferably, the space between the adjacent sidewalls of the second mesa structure 2421 is not greater than 600 nm. Additionally, the width of the second ion implantation fence 2423 is not greater than 50% of the diameter of the second mesa structure 2421. In some embodiments, the width of the second ion implantation fence 2423 is not greater than 10% of the diameter of the second mesa structure 2421. Preferably, in the micro-LED array panel, the width of the second ion implantation fence 2423 is not greater than 200 nm.
With respect to
Referring back to
Further detail characters of the micro-LED in the micro-LED array panel can be found by reference to the above-described micro-LEDs, which will not be further described here.
The method of manufacturing the micro-LED array panel at least includes manufacturing a micro-LED. Details of manufacturing the micro-LED can be found by reference to the description of steps 501-509 in the Embodiment 1 and the description of steps 1403-1406 in the Embodiment 2, which will not be further described here.
In Embodiments 1-3, a micro lens can be further formed on or above the top of the second type semiconductor layer, such as on the top surface of the top conductive layer, which can be understood by those skilled in the field.
The micro-LED herein has a very small volume. The micro-LED may be an organic LED or an inorganic LED. The micro-LED can be applied in a micro-LED array panel. The light emitting area of the micro-LED array panel is very small, such as 1 mm×1 mm, 3 mm×5 mm. In some embodiments, the light emitting area is the area of the micro-LED array in the micro-LED array panel. The micro-LED array panel includes one or more micro-LED arrays that form a pixel array in which the micro-LEDs are pixels, such as a 1600×1200, 680×480, or 1920×1080 pixel array. The diameter of the micro-LED is in the range of about 200 nm˜2 m. An IC backplane is formed at the back surface of the micro-LED array and is electrically connected with the micro-LED array. The IC backplane acquires signals such as image data from outside via signal lines to control corresponding micro-LEDs to emit light or not.
The embodiments may further be described using the following clauses:
1. A micro-LED, comprising:
a first type semiconductor layer; and
a light emitting layer formed on the first type semiconductor layer; wherein
the first type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending up through the first type semiconductor layer and extending up into at least part of the light emitting layer; and
the ion implantation fence is formed around the trench and the trench is formed around first mesa structure, wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.
2. The micro-LED according to clause 1, wherein a top surface of the ion implantation fence is lower than a top surface of the first type semiconductor layer.
3. The micro-LED according to clause 1, wherein a bottom surface of the ion implantation fence is aligned with or higher than or lower than a bottom surface of the first type semiconductor layer.
4. The micro-LED according to clause 1, wherein a top surface of the ion implantation fence is lower than a top surface of the trench.
5. The micro-LED according to clause 1, wherein the trench extends up through the light emitting layer.
6. The micro-LED according to clause 1, further comprising a second type semiconductor layer formed on the light emitting layer, wherein a conductive type of the second type semiconductor layer is different from the conductive type of the first type semiconductor layer.
7. The micro-LED according to clause 6, wherein the trench extends up through the light emitting layer and further extends up into an interior of the second type semiconductor layer.
8. The micro-LED according to clause 6, wherein the trench extends up through the light emitting layer and further extends up through the second type semiconductor layer.
9. The micro-LED according to clause 1, wherein the mesa structure comprises one or more stair structures.
10. The micro-LED according to clause 1, wherein a width of the trench is not greater than 50% of a diameter of the mesa structure.
11. The micro-LED according to clause 10, wherein the width of the trench is not greater than 200 nm.
12. The micro-LED according to clause 1, wherein the ion implantation fence comprises a light absorption material, and the light absorption material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.
13. The micro-LED according to clause 1, wherein a thickness of the first type semiconductor layer is greater than a thickness of the light emitting layer.
14. The micro-LED according to clause 1, further comprising a bottom isolation layer filled in the trench.
15. The micro-LED according to clause 14, wherein a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
16. The micro-LED according to clause 1, wherein the ion implantation fence is formed by at least implanting ions into the first type semiconductor layer.
17. The micro-LED according to clause 16, wherein the ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, 0, C, P, B, Si, S, Cl, or F.
18. The micro-LED according to clause 1, wherein a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
19. The micro-LED according to clause 18, wherein the width of the ion implantation fence is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 100 nm.
20. The micro-LED according to clause 6, wherein a material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and a material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.
21. The micro-LED according to clause 1, further comprising an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer via the connection structure.
22. The micro-LED according to clause 21, wherein the connection structure is a connection pillar or a metal bonding layer.
23. The micro-LED according to clause 21, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
24. A micro-LED array panel, comprising a plurality of micro-LEDs according to any one of clauses 1 to 23.
25. A method for manufacturing a micro-LED, comprising:
providing an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer sequentially from top to bottom;
patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence;
depositing a bottom contact on the mesa structure; and
performing an ion implantation process into the fence to form an ion implantation fence.
26. The method according to clause 25, wherein after patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, the method further comprises:
depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact;
patterning the bottom isolation layer to expose the bottom contact;
depositing metal material on the isolation layer and the bottom contact;
grinding the metal material to a top surface of the bottom isolation layer, to form a connection structure; and
turning the epitaxial structure upside down and bonding the connection structure with an integrated circuit (IC) backplane.
27. The method according to clause 26, wherein in depositing the bottom isolation layer on the isolation layer and the bottom contact, a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
28. The method according to clause 26, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.
29. The method according to clause 28, wherein turning the epitaxial structure upside down and bonding the connection structure with the IC backplane further comprises:
removing the substrate.
30. The method according to clause 28, wherein after turning the epitaxial structure upside down and bonding the connection structure with the IC backplane, the method further comprises:
forming a top contact and a top conductive layer on a top surface of the second type semiconductor layer.
31. The method according to clause 25, wherein patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the first type semiconductor layer to a surface of the light emitting layer.
32. The method according to clause 25, wherein patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the first type semiconductor layer and the light emitting layer in sequence, and
stopping the etching in the light emitting layer.
33. The method according to clause 25, wherein patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer in sequence, and
stopping the etching in the second type semiconductor layer.
34. The method according to clause 25, wherein depositing the bottom contact on the mesa structure further comprises:
forming a protective mask to protect an area where the bottom contact is not deposited; depositing material of a bottom contact on the protective mask and on the first type semiconductor layer; and
removing the protective mask from the first type semiconductor layer and removing the material on the protective mask, to form the bottom contact on the first mesa structure.
35. The method according to clause 25, wherein performing an ion implantation process into the fence to form an ion implantation fence further comprises:
forming a protective mask on an area not being ion implanted while leaving the fence exposed;
implanting ions into the fence; and
removing the protective mask.
36. The method according to clause 35, wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting with an energy of 0˜500 Kev.
37. The method according to clause 35, wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting a dose of 1E10˜9E17.
38. The method according to clause 35, wherein in performing the ion implantation process into the fence to form the ion implantation fence, ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
39. The method according to clause 35, wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
40. The method according to clause 35, wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 200 nm, a diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.
41. The method according to clause 25, wherein in patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is not greater than 50% of a diameter of the mesa structure.
42. The method according to clause 25, wherein a conductive type of the first type semiconductor layer is P type and a conductive type of the second type semiconductor layer is N type, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
43. The method according to clause 42, wherein the ion implantation fence comprises a light absorption material.
44. The method according to clause 43, wherein the light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.
45. A micro-LED, comprising:
a first type semiconductor layer;
a light emitting layer formed on the first type semiconductor layer;
a second type semiconductor layer formed on the light emitting layer; and
an integrated circuit (IC) backplane formed at a bottom surface of the first type semiconductor layer; wherein
the second type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending down through the second type semiconductor layer and extending down into at least part of the light emitting layer; and
the ion implantation fence is formed around the trench and the trench is formed around the mesa structure, wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure;
wherein a conductive type of the second type semiconductor layer is different from the conductive type of the first type semiconductor layer.
46. The micro-LED according to clause 45, wherein a bottom surface of the ion implantation fence is higher than a bottom surface of the second type semiconductor layer.
47. The micro-LED according to clause 45, wherein a top surface of the ion implantation fence is aligned with or higher than or lower than a top surface of the second type semiconductor layer.
48. The micro-LED according to clause 45, wherein a bottom surface of the ion implantation fence is higher than a bottom surface of the trench.
49. The micro-LED according to clause 45, wherein the trench extends down through the light emitting layer.
50. The micro-LED according to clause 45, wherein the trench extends down through the light emitting layer and further extends down into an interior of the first type semiconductor layer.
51. The micro-LED according to clause 45, wherein the trench extends down through the light emitting layer and further extends down through the first type semiconductor layer.
52. The micro-LED according to clause 45, wherein the mesa structure comprises one or more stair structures.
53. The micro-LED according to clause 45, wherein a width of the trench is not greater than 50% of a diameter of the mesa structure.
54. The micro-LED according to clause 53, wherein the width of the trench is not greater than 200 nm.
55. The micro-LED according to clause 45, wherein the ion implantation fence comprises a light absorption material, wherein the light absorption material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.
56. The micro-LED according to clause 45, wherein a thickness of the second type semiconductor layer is greater than a thickness of the light emitting layer.
57. The micro-LED according to clause 45, further comprising a bottom isolation layer formed on a bottom surface of the first type semiconductor layer and the top surface of the IC backplane.
58. The micro-LED according to clause 57, wherein a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
59. The micro-LED according to clause 45, wherein the ion implantation fence is formed by at least implanting ions into the second type semiconductor layer.
60. The micro-LED according to clause 59, wherein ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
61. The micro-LED according to clause 45, wherein a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
62. The micro-LED according to clause 61, wherein the width of the ion implantation fence is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.
63. The micro-LED according to clause 45, wherein a material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and a material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.
64. The micro-LED according to clause 45, further comprising a connection structure electrically connecting the IC backplane with the first type semiconductor layer via the connection structure.
65. The micro-LED according to clause 64, wherein the connection structure is a connection pillar or a metal bonding layer.
66. The micro-LED according to clause 64, further comprising: a bottom contact formed on a bottom surface of the first type semiconductor layer; and an upper surface of the connection structure is connected with the bottom contact and a bottom surface of the connection structure is connected with the IC backplane.
67. A micro-LED array panel, comprising a plurality of micro-LEDs according to any one of clauses 45 to 66.
68. A method for manufacturing a micro-LED, comprising:
providing an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer sequentially from top to bottom;
bonding the epitaxial structure with an integrated circuit (IC) backplane;
patterning the second type semiconductor layer to form a mesa structure, a trench, and a fence;
depositing a top contact on the mesa structure;
performing an ion implantation process into the fence; and
depositing a top conductive layer on a top surface of the second type semiconductor layer, on a top contact, and in the trench.
69. The method according to clause 68, wherein providing the epitaxial structure further comprises:
depositing a bottom contact layer on a top surface of the first type semiconductor layer; and
depositing a metal bonding layer on a top surface of the bottom contact layer.
70. The method according to clause 69, wherein bonding the epitaxial structure with the IC backplane further comprises:
turning the epitaxial structure upside down; and
bonding the metal bonding layer with a contact pad of the IC backplane.
71. The method according to clause 70, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.
72. The method according to clause 71, wherein bonding the epitaxial structure with the IC backplane further comprises:
removing the substrate.
73. The method according to clause 68, wherein patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the second type semiconductor layer to a surface of the light emitting layer.
74. The method according to clause 68, wherein patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the second type semiconductor layer and the light emitting layer in sequence; and
stopping the etching in the light emitting layer.
75. The method according to clause 68, wherein patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the second type semiconductor layer, the light emitting layer, and the first type semiconductor layer in sequence; and
stopping the etching in the first type semiconductor layer.
76. The method according to clause 68, wherein depositing the top contact on the mesa structure further comprises:
forming a protective mask;
depositing a material of the top contact on the protective mask; and
removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask, to form the top contact on the mesa structure.
77. The method according to clause 68, wherein performing the ion implantation process into the fence further comprises:
forming a protective mask on an area not being ion implanted while leaving the fence exposed;
implanting ions into the fence; and
removing the protective mask.
78. The method according to clause 77, wherein in performing the ion implantation process into the fence, implanting with an energy of 0˜500 Kev.
79. The method according to clause 77, wherein in performing the ion implantation process into the fence, implanting a dose of 1E10˜9E17.
80. The method according to clause 77, wherein in performing the ion implantation process into the fence, ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
81. The method according to clause 77, wherein in performing the ion implantation process into the fence, a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
82. The method according to clause 77, wherein in performing the ion implantation process into the fence, a width of the ion implantation fence is not greater than 200 nm, a diameter of the mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.
83. The method according to clause 68, wherein a conductive type of the first type semiconductor layer is P type and a conductive type of the second type semiconductor layer is N type; a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
84. The method according to clause 83, wherein the ion implantation fence comprises a light absorption material.
85. The method according to clause 84, wherein the light absorption material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.
86. A micro-LED, comprising:
a first type semiconductor layer;
a light emitting layer formed on the first type semiconductor layer; and
a second type semiconductor layer formed on the light emitting layer, wherein the first type semiconductor layer comprises a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the first trench extending up through the first type semiconductor layer and extending up into at least part of the light emitting layer;
the first ion implantation fence is formed around the first trench and the first trench is formed around the first mesa structure, an electrical resistance of the first ion implantation fence being higher than an electrical resistance of the first mesa structure; and
wherein the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure;
the second ion implantation fence is formed around the second trench and the second trench is formed around the second mesa structure, an electrical resistance of the second ion implantation fence being higher than an electrical resistance of the second mesa structure;
wherein a conductive type of the second type semiconductor layer is different from the conductive type of the first type semiconductor layer.
87. The micro-LED according to clause 86, wherein a top surface of the first trench does not contact a bottom surface of the second trench, and part of the light emitting layer is configured between the top surface of the first trench and the bottom surface of the second trench.
88. The micro-LED according to clause 87, wherein a top surface of the first ion implantation fence is lower than a top surface of the first type semiconductor layer, and a bottom surface of the second ion implantation fence is higher than a bottom surface of the second type semiconductor layer.
89. The micro-LED according to clause 86, wherein a bottom surface of the first ion implantation fence is aligned with or higher than or lower than a bottom surface of the first type semiconductor layer; and
a top surface of the second ion implantation fence is aligned with or higher than or lower than a top surface of the second type semiconductor layer.
90. The micro-LED according to clause 86, wherein a top surface of the first ion implantation fence is lower than a top surface of the first trench.
91. The micro-LED according to clause 86, wherein the second trench extends down into the second type semiconductor layer.
92. The micro-LED according to clause 91, wherein the second trench extends down through the second type semiconductor layer and extends down into at least part of the light emitting layer.
93. The micro-LED according to clause 92, wherein a bottom surface of the second ion implantation fence is higher than a bottom of the first trench.
94. The micro-LED according to clause 86, wherein the first trench and the second trench are connected directly, without the light emitting layer disposed between the first trench and the second trench.
95. The micro-LED according to clause 86, wherein the first mesa structure comprises one or more stair structures and the second mesa structure comprises one or more stair structures.
96. The micro-LED according to clause 86, wherein a width of the first trench is not greater than 50% of a diameter of the first mesa structure; and/or, a width of the second trench is not greater than 50% of a diameter of the second mesa structure.
97. The micro-LED according to clause 96, wherein the width of the first trench is not greater than 200 nm; and/or, the width of the second trench is not greater than 200 nm.
98. The micro-LED according to clause 86, wherein the first ion implantation fence comprises a first light absorption material, and the second ion implantation fence comprises a second light absorption material; wherein a conductive type of the first light absorption material is the same as a conductive of the first type semiconductor layer, a conductive type of the second light absorption material is the same as a conductive of the second type semiconductor layer.
99. The micro-LED according to clause 98, wherein the first light absorption material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN; and/or, the second light absorption material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.
100. The micro-LED according to clause 86, wherein a thickness of the first type semiconductor layer is greater than a thickness of the light emitting layer, a thickness of the second type semiconductor layer is greater than a thickness of the light emitting layer, and the thickness of the first type semiconductor layer is greater than the thickness of the second type semiconductor layer.
101. The micro-LED according to clause 86, further comprising a bottom isolation layer formed between a bottom surface of the first type semiconductor layer and a top surface of an integrated circuit (IC) backplane.
102. The micro-LED according to clause 101, wherein a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
103. The micro-LED according to clause 86, wherein the first ion implantation fence is formed by at least implanting first ions into the first type semiconductor layer and the second ion implantation fence is formed by at least implanting second ions into the second type semiconductor layer.
104. The micro-LED according to clause 103, wherein ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, 0, C, P, B, Si, S, Cl, or F; and ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
105. The micro-LED according to clause 86, wherein a width of the first ion implantation fence is not greater than 50% of a diameter of the first mesa structure; and a width of the second ion implantation fence is not greater than 50% of a diameter of the second mesa structure.
106. The micro-LED according to clause 105, wherein the width of the first ion implantation fence is not greater than 200 nm, the diameter of the first mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 100 nm; and
the width of the second ion implantation fence is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.
107. The micro-LED according to clause 86, wherein a material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and a material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.
108. The micro-LED according to clause 86, further comprising: an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer via the connection structure.
109. The micro-LED according to clause 108, wherein the connection structure is a connection pillar or a metal bonding layer.
110. The micro-LED according to clause 108, further comprising: a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
111. A micro-LED array panel, comprising a plurality of micro-LEDs according to any one of clauses 86 to 110.
112. A method for manufacturing a micro-LED, comprising:
a process I comprising patterning a first type semiconductor layer, and implanting first ions into the first type semiconductor layer; and
a process II comprising patterning a second type semiconductor layer, and implanting second ions into the second type semiconductor layer.
113. The method according to clause 112, wherein the process I further comprises:
providing an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer sequentially from top to bottom;
patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence;
depositing a bottom contact on the mesa structure;
performing an ion implantation process into the fence to form an ion implantation fence;
depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact;
patterning the bottom isolation layer to expose the bottom contact;
depositing metal material on the isolation layer and the bottom contact;
grinding the metal material to a top surface of the bottom isolation layer, to form a connection structure; and
turning the epitaxial structure upside down and bonding the connection structure with an Integrated Circuit (IC) backplane.
114. The method according to clause 113, wherein patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: etching the first type semiconductor layer to a surface of the light emitting layer.
115. The method according to clause 113, wherein patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the first type semiconductor layer and the light emitting layer in sequence; and stopping the etching in the light emitting layer.
116. The method according to clause 113, wherein patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer in sequence; and stopping the etching in the second type semiconductor layer.
117. The method according to clause 113, wherein depositing the bottom contact on the mesa structure further comprises:
forming a protective mask to protect an area where the bottom contact is not being deposited;
depositing a material of the bottom contact on the protective mask and on the first type semiconductor layer; and
removing the protective mask from the first type semiconductor layer and removing the material on the protective mask, to form the bottom contact on the mesa structure.
118. The method according to clause 113,
wherein performing the ion implantation process into the fence to form the ion implantation fence further comprises:
forming a protective mask on an area not being ion implanted while leaving the fence exposed;
implanting ions into the fence; and
removing the protective mask.
119. The method according to clause 118, wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting with an energy of 0˜500 Kev, and implanting a dose of 1E10˜9E17.
120. The method according to clause 118, wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting ions into the fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
121. The method according to clause 118, wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure, the width of the ion implantation fence is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.
122. The method according to clause 113, wherein in patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is not greater than 50% of a diameter of the mesa structure.
123. The method according to clause 112, wherein the mesa structure, the trench, and the fence are a first mesa structure, a first trench, and a first fence respectively; wherein the process II further comprises:
patterning the second type semiconductor layer to form a second mesa structure, a second trench, and a second fence;
depositing a top contact on the second mesa structure;
performing an ion implantation process into the second fence; and
depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the second trench.
124. The method according to clause 123, wherein patterning the second type semiconductor layer to form the second mesa structure, the second trench, and the second fence further comprises:
etching the second type semiconductor layer to a surface of the light emitting layer.
125. The method according to clause 123, wherein patterning the second type semiconductor layer to form the second mesa structure, the second trench, and the second fence further comprises:
etching the second type semiconductor layer and the light emitting layer in sequence, and stopping the etching in the light emitting layer.
126. The method according to clause 123, wherein patterning the second type semiconductor layer to form the second mesa structure, the second trench, and the second fence further comprises:
etching the second type semiconductor layer, the light emitting layer, and the first type semiconductor layer in sequence, and stopping the etching in the first type semiconductor layer.
127. The method according to clause 123, wherein depositing the top contact on the second mesa structure further comprises:
forming a protective mask;
depositing a material of the top contact on the protective mask;
removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask, to form the top contact on the second mesa structure.
128. The method according to clause 123, wherein performing the ion implantation process into the second fence further comprises:
forming a protective mask on an area not being implanted while leaving the second fence exposed;
implanting ions into the second fence; and
removing the protective mask.
129. The method according to clause 123, wherein in performing the ion implantation process into the second fence, implanting with an energy of 0˜500 KeV and implanting a dose of 1E10˜9E17.
130. The method according to clause 123, wherein in performing the ion implantation process into the second fence, implanting ions into the second fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
131. The method according to clause 123, wherein performing the ion implantation process into the second fence forms a second ion implantation fence, wherein a width of the second ion implantation fence is not greater than 50% of a diameter of the second mesa structure, the width of the second ion implantation fence is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.
132. The method according to clause 113, wherein
in providing the epitaxial structure, the epitaxial structure is grown on a substrate; and the turning the epitaxial structure upside down and bonding the connection structure with the IC backplane further comprises:
removing the substrate.
133. The method according to clause 113, wherein in depositing the bottom isolation layer on the first type semiconductor layer and the bottom contact, a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
134. The method according to clause 113, wherein the first ion implantation fence comprises a light absorption material.
135. The method according to clause 134, wherein the light absorption material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.
136. The method according to clause 113, wherein a conductive type of the first type semiconductive layer is P type and a conductive type of the second type semiconductive layer is N type; and a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN or p-AlGaN; and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
It should be noted that relational terms herein such as “first” and “second” are used only to differentiate an entity or operation from another entity or operation, and do not require or imply any actual relationship or sequence between these entities or operations. Moreover, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items.
As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.
In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain adaptations and modifications of the described embodiments can be made. Other embodiments can be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. It is also intended that the sequence of steps shown in figures are only for illustrative purposes and are not intended to be limited to any particular sequence of steps. As such, those skilled in the art can appreciate that these steps can be performed in a different order while implementing the same method.
In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.
| Number | Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/075283 | Jan 2022 | WO | international |
The disclosure claims the benefits of priority to PCT Application No. PCT/CN2022/075283, filed on Jan. 31, 2022, which is incorporated herein by reference in its entirety.
