The present disclosure generally relates to light emitting diode, and more particularly, to a micro light emitting diode (LED), a micro-LED array panel, and a manufacturing method thereof.
Inorganic micro pixel light emitting diodes, also referred to as micro light emitting diodes, micro-LEDs or μ-LEDs, are of increasing importance because of their use in various applications including self-emissive micro-displays, visible light communications, and optogenetics. The micro-LEDs exhibit higher output performance than conventional LEDs due to better strain relaxation, improved light extraction efficiency, and uniform current spreading. The micro-LEDs also exhibit improved thermal effects, fast response rate, larger work temperature range, higher resolution, color gamut and contrast, and lower power consumption, and can be operated at higher current density compared with conventional LEDs.
The inorganic micro-LEDs are conventionally III-V group epitaxial layers formed as multiple mesas. A space is formed between the adjacent micro-LEDs in the conventional micro-LEDs structures to avoid carriers in the epitaxial layer spreading from one mesa to an adjacent mesa. However, the space which is formed between the adjacent micro-LEDs can reduce an active light emitting area and decrease light extraction efficiency. If there is no space between the adjacent micro-LEDs, the active light emitting area would be increased and the carriers in the epitaxial layer would spread laterally to the adjacent mesa, which reduces the light emitting efficiency of the micro-LED. Furthermore, if there is no space formed between the adjacent mesas, cross talk will be produced between the adjacent micro-LEDs, which would interfere with LEDs operation.
However, smaller micro-LEDs with higher current densities will experience red-shift, lower maximum efficiency, and inhomogeneous emission at high current density, which has been attributed to fabrication process damage that results in degraded electrical injection. In addition, the peak external quantum efficiencies (EQEs) and internal quantum efficiency (IQE) are largely decreased with decreasing chip size. The decreased EQE appears due to nonradiative recombination caused by etching damage and the decreased IQE is attributed to poor current injection and electron leakage current of micro-LEDs.
The above discussion is only provided to assist in understanding the technical problem overcome by the present disclosure, and does not constitute an admission that the above is prior art.
Embodiments of the present disclosure provide a micro-LED. The micro-LED includes a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; and a light emitting layer formed on the first type cap layer; wherein the first type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure; wherein an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure.
Embodiments of the present disclosure provide micro-LED array panel. The micro-LED array panel includes a first type semiconductor layer formed in the micro-LED array panel; a first type cap layer formed on the first type semiconductor layer; a light emitting layer formed on the first type cap layer; a second type cap layer formed on the light emitting layer; and a second type semiconductor layer formed on the second type cap layer; wherein the first type is P type and the second type is N type; and the first type semiconductor layer includes multiple mesa structures, multiple trenches and multiple ion implantation fences separated from the mesa structures by the trenches; wherein a top surface of the ion implantation fence is lower than or aligned with a top surface of the first type semiconductor layer; and the ion implantation fences are formed around the trench and between adjacent type mesa structures; wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.
Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method includes providing an epitaxial structure, wherein the epitaxial structure includes a first type semiconductor layer, a first type cap layer, a light emitting layer, a second type cap layer, and a second type semiconductor layer sequentially from top to bottom; patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a bottom contact on the mesa structure; and performing an ion implantation process into the fence to form an ion implantation fence.
Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying figures. Various features shown in the figures are not drawn to scale.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the invention. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the invention as recited in the appended claims. Particular aspects of the present disclosure are described in greater detail below. The terms and definitions provided herein control, if in conflict with terms and/or definitions incorporated by reference.
The present disclosure provides a micro-LED which can avoid nonradiative recombination at sidewalls of a mesa according to a structure of a semiconductor layer and continuously formed light emitting layer. Furthermore, compared with conventional micro-LEDs, a space between adjacent mesas can be decreased largely due to an ion implantation fence. Therefore, the integration level of the micro-LEDs in a chip is increased and the active light emitting efficiency is improved. Furthermore, the micro-LED provided by the present disclosure can also increase the active light emitting area and improve the image quality.
Referring to
A conductive type of the first type semiconductor layer 110 is different from a conductive type of the second type semiconductor layer 120. In some embodiments, the conductive type of the first type semiconductor layer 110 is P type and the conductive type of the second type semiconductor layer 120 is N type. In some embodiments, the conductive type of the second type semiconductor layer 120 is P type and the conductive type of the first type semiconductor layer 110 is N type. For example, a material of the first type semiconductor layer 110 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
A conductive type of the first type cap layer 114 is the same as the conductive type of the first type semiconductor layer 110 and a conductive type of the second type cap layer 124 is the same as the second type semiconductor layer 120. The first type semiconductor layer 110 includes a mesa structure 111, a trench 112 and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are annular around the mesa structure 111.
The ion implantation fence 113 includes a light absorption material for absorbing light from the mesa structure 111. A conductive type of the light absorption material is the same as the conductive type of the first semiconductor layer 110. Preferably, the light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. Additionally, the ion implantation fence 113 is formed at least by implanting ions into the first type semiconductor layer 110. Preferably, the ion type implanted into the first type semiconductor layer 110 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
Furthermore, the width of the ion implantation fence 113 is not greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is not greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is not greater than 200 nm, the diameter of the mesa structure 111 is not greater than 2500 nm, and the thickness of the first type semiconductor layer 110 is not greater than 300 nm.
In some embodiments, the width of the trench 112 is not greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the trench 112 is not greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the first trench 112 is not greater than 200 nm.
In some embodiments, the top surface of the ion implantation fence 113 is not higher than the top surface of the first type semiconductor layer 110. Therefore, the ion implantation fence 113 can contact the first type cap layer 114 but cannot contact the light emitting layer 130. The top surface of the ion implantation fence 113 can be formed at any position within the first type semiconductor layer 110. As shown in
Referring to
Referring to
Additionally, the bottom surface of the ion implantation fence 113 can be formed at any position. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first type semiconductor layer 110. Referring to
In some embodiments, as shown in
In this embodiment, an integrated circuit (IC) backplane 190 is formed under the first type semiconductor layer 110 and is electrically connected with the first type semiconductor layer 110 via a connection structure 150. As shown in
The micro-LED further includes a bottom contact 160. The bottom contact 160 is formed at the bottom of the first type semiconductor layer 110. An upper surface of the connection structure 150 is connected with a bottom contact 160 and the bottom surface of the connection structure 150 is connected with the IC backplane 190.
Referring to
Referring to
In step 502: referring to
As shown in
In step 503: referring to
Before the bottom contact 660 deposited, a first protective mask (not shown) is used to protect an area where the bottom contact 660 will not be formed. Then, the material of the bottom contact 660 is deposited on the first protective mask and on the first type semiconductor layer 610 by a conventional vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. After the deposition process, the first protective mask is removed from the first type semiconductor layer 610 and the material on the first protective mask is also removed with the first protective mask to form the bottom contact 660 on the mesa structure 611.
In step 504: referring to
The ions are implanted into the fence 613′ (as shown in
In step 505: referring to
In step 506: referring to
In step 507: referring to
In step 508: referring to
In step 509: referring to
In step 510: referring to
A micro-LED array panel is further provided by some embodiments of the present disclosure. The micro-LED array panel includes a plurality of micro-LEDs as described above and shown in
A conductive type of the first type semiconductor layer 710 is different from a conductive type of the second type semiconductor layer 720. For example, in some embodiments, the conductive type of the first type semiconductor layer 710 is P type and the conductive type of the second type semiconductor layer 720 is N type. In some embodiments, the conductive type of the second type semiconductor layer 720 is P type and the conductive type of the first type semiconductor layer 710 is N type. The thickness of the first type semiconductor layer 710 is greater than the thickness of the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. A conductive type of the first type cap layer 714 is the same as the conductive type of the first type semiconductor layer 710 and a conductive type of the second type cap layer 724 is the same as the conductive type of the second type semiconductor layer 720.
The first type semiconductor layer 710 includes multiple mesa structures 711, multiple trenches 712, and multiple ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fence 713 is not higher than the top surface of the first type semiconductor layer 710. Thus, the ion implantation fence 713 cannot reach the light emitting layer 730. The top of the ion implantation fence 713 can be formed at any position. Additionally, the bottom surface of the ion implantation fence 713 can be formed at any position. The relationship of the top surface of the ion implantation fence 713, the top surface of the first type semiconductor layer 710, and the top surface of the trench 712 can be seen in the micro-LED shown in
In some embodiments, a space between the adjacent sidewalls of the adjacent ones of the mesa structure 711 can be adjusted. For example, in some embodiments, the space between the adjacent sidewalls of the mesa structures 711 is not greater than 50% of the diameter of the mesa structure 711. In some embodiments, the space between the adjacent sidewalls of the mesa structures 711 is not greater than 30% of the diameter of the mesa structure 711. Preferably, the space between the adjacent sidewalls of the mesa structure 711 is not greater than 600 nm. Additionally, in some embodiments, the width of the ion implantation fence 713 can be adjusted. For example, the width of the ion implantation fence 713 can be not greater than 50% of the diameter of the mesa structure 711. In some embodiments, the width of the ion implantation fence 713 can be not greater than 10% of the diameter of the mesa structure 711. Preferably, in the micro-LED array panel, the width of the ion implantation fence 713 is not greater than 200 nm.
In this embodiment, the micro-LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on the top of a second type semiconductor layer 920. The top conductive layer 970 is formed on the top of the second type semiconductor layer 920 and the top contact 980. A conductive type of the top contact 980 is the same as a conductive type of the second type semiconductor layer 920. For example, in some embodiments, the conductive type of the second type semiconductor layer 920 is N type and the conductive type of the top contact 980 is N type. In some embodiments, the conductive type of the second type semiconductor layer 920 is P type and the conductive type of the top contact 980 is P type. The top contact 980 is made of metal or metal alloy, such as, AuGe, AuGeNi, etc. The top contact 980 is used for forming ohmic contact between the top conductive layer 970 and the second type semiconductor layer 920, to optimize the electrical properties of the micro-LEDs. The diameter of the top contact 980 is about 20˜50 nm and the thickness of the top contact 980 is about 10˜20 nm.
In some embodiments, a dielectric layer is formed between the top conductive layer and the second type semiconductor layer (referring to
The micro-LED array panel can be manufactured by the method 500 as shown in
The second type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is not lower than the bottom surface of the second type semiconductor layer 1020. Thus, the ion implantation fence 1023 can reach the second type cap layer 1024 but cannot reach the light emitting layer 1030. The bottom surface of the ion implantation fence 1023 can be formed at any position. Furthermore, the ion implantation fence 1023 is formed around the trench 1022 and the trench 1022 is formed around the mesa structure 1021. The electrical resistance of the ion implantation fence 1023 is higher than the electrical resistance of the mesa structure 1021.
The ion implantation fence 1023 includes a light absorption material for absorbing light from the mesa structure 1021. A conductive type of the light absorption material is the same as the conductive type of the second semiconductor layer 1020. Preferably, the light absorption material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN. Additionally, the ion implantation fence 1023 is formed at least by implanting ions into the second type semiconductor layer 1020. Preferably, the ions implanted into the second type semiconductor layer 1020 to form the ion implantation fence 1013 are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
Furthermore, the width of the ion implantation fence 1023 can be adjusted. For example, in some embodiments, the width of the ion implantation fence 1023 is not greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is not greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is not greater than 200 nm. The diameter of the mesa structure 1021 is not greater than 2500 nm. The thickness of the second type semiconductor layer 1020 is not greater than 100 nm.
In some embodiments, the width of the trench 1022 is not greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the trench 1022 is not greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the trench 1022 is not greater than 200 nm.
There is no limitation on the depth of the trench 1022. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and enter into the interior of the second type cap layer 1024. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the second type cap layer 1024, and reach the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the second type cap layer 1024, and extend into the interior of the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, and the light emitting layer 1030. Furthermore, in some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024 and the light emitting layer 1030, and extend down into the interior of the first type cap layer 1014. Furthermore, in some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, the light emitting layer 1030 and the first type cap layer 1014, and extend down into the interior of the first type semiconductor layer 1010.
In some embodiments, as shown in
In some embodiments, as shown in
Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any position. Preferably, the top surface of the ion implantation fence 1023 is aligned with the top surface of the second type semiconductor layer 1020. In some embodiments, as shown in
In some embodiments, as show in
Additionally, in some embodiments, the micro-LED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on the top of the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020 and the top surface of the top contact 1080, and is filled in the second trench 1022. A conductive type of the top contact 1080 is the same as a conductive type of the second type semiconductor layer 1020. For example, the conductive type of the second type semiconductor layer 1020 is N type and the conductive type of the top contact 1080 is N type. The top contact 1080 is made of metal or metal alloy, such as, AuGe, AuGeNi, etc. The top contact 1080 is used for forming an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020, to optimize the electrical properties of the micro-LED. The diameter of the top contact 1080 is about 20˜50 nm and the thickness of the top contact 1080 is about 10˜20 nm.
Referring to
Referring to
Preferably, before turning upside down the epitaxial structure, a bottom contact layer 1560 used as the bottom contact is deposited on the top surface of the first type semiconductor layer 1510. Then, a metal bonding layer which is used as a connection structure 1550 is firstly deposited on the top surface of the bottom contact layer 1560.
In step 1402: referring to
In step 1403: referring to
In step 1404: referring to
In step 1405: referring to
In step 1406: referring to
Alternatively, referring back to
A micro-LED array panel is further provided according to some embodiments of the present disclosure. The micro-LED array panel includes a plurality of micro-LEDs as described above shown in
The second type semiconductor layer 1620 includes multiple mesa structures 1621, multiple trenches 1622, and multiple ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. The bottom surface of the ion implantation fence 1623 is not lower than the bottom surface of the second type semiconductor layer 1620.
Variations in the relationship of the bottom surface of the ion implantation fence 1623, and the bottom surface of the second type semiconductor layer 1620, and the bottom of the trench 1622 generally correspond to those shown for the micro-LED in
In some embodiments, a space between the adjacent sidewalls of adjacent ones of the mesa structures 1621 can be adjusted. For example, in some embodiments, the space between the adjacent sidewalls of the mesa structures 1621 is not greater than 50% of the diameter of the mesa structure 1621. In some embodiments, the space between the adjacent sidewalls of the mesa structures 1621 is not greater than 30% of the diameter of the mesa structure 1621. Preferably, the space between the adjacent sidewalls of the mesa structures 1621 is not greater than 600 nm. Additionally, in some embodiments, the width of the ion implantation fence 1623 can be adjusted. For example, in some embodiments, the width of the ion implantation fence 1623 can be not greater than 50% of the diameter of the mesa structure 1621. In some embodiments, the width of the ion implantation fence 1623 can be not greater than 10% of the diameter of the mesa structure 1621. Preferably, in the micro-LED array panel, the width of the ion implantation fence 1623 is not greater than 200 nm.
Furthermore, referring back to
As shown in
Additionally, further details regarding the features of the micro-LED and the ion implantation fence in the micro-LED array panel can be understood by also referring to the micro-LEDs as shown in
The micro-LED array panel shown in
A conductive type of the first type cap layer 1914 is the same as the conductive type of the first type semiconductor layer 1910 and a conductive type of the second type cap layer 1924 is the same as the second type semiconductor layer 1920.
The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912, and a first ion implantation fence 1913 separated from the first mesa structure 1911. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922, and a second ion implantation fence 1923 separated from the second mesa structure 1921.
In some embodiments, the center of the first mesa structure 1911 is aligned with the center of the second mesa structure 1921, the center of the first trench 1912 is aligned with the center of the second trench 1922, and the center of the first ion implantation fence 1913 is aligned with the center of the second ion implantation fence 1923.
The relationship of the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912 and the top surface of the first type semiconductor layer 1910 is the same as that of the variants of the micro-LED in Embodiment 1 shown in
The relationship of the bottom of the second ion implantation fence 1923, the bottom of the second trench 1922 and the bottom of the second type semiconductor layer 1920 is the same as that of the variants of the micro-LED in embodiment 2 shown in
The micro-LED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on the top of a second type semiconductor layer 2020. The top conductive layer 2070 is formed on the top of the second type semiconductor layer 2020 and the top contact 2080 and fills in the second trench 2022. Further details regarding the top contact 2080 and the top conductive layer 2070 can be found by referring to the description for Embodiment 2, which will not be further described here. In some embodiments, a dielectric layer 1071 as shown in
Additionally, further details regarding the micro-LED shown in
In Process I: the first type semiconductor layer is patterned, and then ions are implanted into the first type semiconductor layer, to form a first ion implantation fence.
In Process II: the second type semiconductor layer is patterned, and then ions are implanted into the second type semiconductor layer, to form a second ion implantation fence.
Referring to
For Process I, the steps 2101-2109 are similar to the steps 501-509 of method 500 as shown in
In step 2102: referring to
In step 2103: referring to
In step 2104: referring to
In step 2105: referring to
In step 2106: referring to
In step 2107: referring to
In step 2108: referring to
In step 2109: referring to
In step 2111: referring to
In step 2112: referring to
In step 2113: referring to
Further details of the Process I can be found by reference to the description of steps 501-509 for the Embodiment 1. Further details of the Process II can be found by reference to the description of steps 1403-1406 for the Embodiment 2, which will not be further described here.
A micro-LED array panel is further provided according to some embodiments of the present disclosure. The micro-LED array panel includes a plurality of micro-LEDs as described above and shown in
The first type semiconductor layer 2310 includes multiple first mesa structures 2311, multiple first trenches 2312, and multiple first ion implantation fences 2313 separated from the first mesa structures via the first trenches 2312. The top surface of the first ion implantation fence 2313 is lower than the top surface of the first type semiconductor layer 2310. Referring back to
The second type semiconductor layer 2320 includes multiple second mesa structures 2321, multiple second trenches 2322, and multiple second ion implantation fences 2323 separated from the second mesa structures 2321 via the second trenches 2322. The bottom surface of the second ion implantation fence 2323 is higher than the bottom surface of the second type semiconductor layer 2320. A top view of the micro-LED array panel is similar to the top view shown in
In some embodiments, a space between the adjacent sidewalls of the first mesa structures 2311 can be adjusted. For example, in some embodiments, the space between the adjacent sidewalls of the first mesa structures 2311 is not greater than 50% of the diameter of the first mesa structure 2311. In some embodiments, the space between the adjacent sidewalls of the first mesa structures 2311 is not greater than 30% of the diameter of the first mesa structure 2311. Preferably, the space between the adjacent sidewalls of the first mesa structures 2311 is not greater than 600 nm. Additionally, in some embodiments, the width of the first ion implantation fence 2313 can be adjusted. For example, in some embodiments, the width of the first ion implantation fence 2313 is not greater than 50% of the diameter of the first mesa structure 2311. In some embodiments, the width of the first ion implantation fence 2313 is not greater than 10% of the diameter of the first mesa structure 2311. Preferably, in some embodiments, in the micro-LED array panel, the width of the first ion implantation fence 2313 is not greater than 200 nm. The space between the adjacent sidewalls of the second mesa structure 2321 is not greater than 50% of the diameter of the second mesa structure 2321. In some embodiments, the space between the adjacent sidewalls of the second mesa structure 2321 is not greater than 30% of the diameter of the second mesa structure 2321. Preferably, the space between the adjacent sidewalls of the second mesa structure 2321 is not greater than 600 nm. Additionally, the width of the second ion implantation fence 2323 is not greater than 50% of the diameter of the second mesa structure 2321. In some embodiments, the width of the second ion implantation fence 2423 is not greater than 10% of the diameter of the second mesa structure 2421. Preferably, in the micro-LED array panel, the width of the second ion implantation fence 2323 is not greater than 200 nm.
Referring back to
Further detail characters of the micro-LED in the micro-LED array panel can be found by reference to the above described micro-LEDs, which will not be further described here.
The method of manufacturing the micro-LED array panel at least includes manufacturing a micro-LED. Details of manufacturing the micro-LED can be found by reference to the description of steps 501-509 in the Embodiment 1 and the description of steps 1403-1406 in the Embodiment 2, which will not be further described here.
In Embodiments 1-3, a micro lens can be further formed on or above the top of the second type semiconductor layer, such as on the top surface of the top conductive layer, which can be understood by those skilled in the field.
The micro-LED herein has a very small volume. The micro-LED may be an organic LED or an inorganic LED. The micro-LED can be applied in a micro-LED array panel. The light emitting area of the micro-LED array panel is very small, such as 1 mm×1 mm, 3 mm×5 mm. In some embodiments, the light emitting area is the area of the micro-LED array in the micro-LED array panel. The micro-LED array panel includes one or more micro-LED arrays that form a pixel array in which the micro-LEDs are pixels, such as a 1600×1200, 680×480, or 1920×1080 pixel array. The diameter of the micro-LED is in the range of about 200 nm˜2 μm. An IC backplane is formed at the back surface of the micro-LED array and is electrically connected with the micro-LED array. The IC backplane acquires signals such as image data from outside via signal lines to control corresponding micro-LEDs to emit light or not.
The embodiments may further be described using the following clauses:
1. A micro-LED, comprising:
a first type semiconductor layer;
a first type cap layer formed on the first type semiconductor layer; and
a light emitting layer formed on the first type cap layer; wherein
the first type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure; the ion implantation fence is formed around the trench and the trench is formed around the mesa structure, wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.
2. The micro-LED according to clause 1, wherein a top surface of the ion implantation fence is not higher than a top surface of the first type semiconductor layer.
3. The micro-LED according to clause 1, wherein a bottom surface of the ion implantation fence is aligned with or higher than a bottom surface of the first type semiconductor layer.
4. The micro-LED according to clause 1, wherein the trench extends up through a top surface of the first type semiconductor layer to a bottom surface of the first type cap layer.
5. The micro-LED according to clause 4, wherein a top surface of the ion implantation fence is not higher than a top surface of the trench.
6. The micro-LED according to clause 1, wherein the trench does not extend up through a top surface of the first type semiconductor layer.
7. The micro-LED according to clause 6, wherein a top surface of the ion implantation fence is not lower than a top surface of the trench.
8. The micro-LED according to clause 6, wherein a top surface of the ion implantation fence is lower than a top surface of the trench.
9. The micro-LED according to clause 1, further comprising:
a second type cap layer formed on the light emitting layer; and
a second type semiconductor layer formed on the second type cap layer;
wherein a conductive type of the second type semiconductor layer is different from the conductive type of the first type semiconductor layer.
10. The micro-LED according to clause 9, wherein the mesa structure, the trench, and the ion implantation fence are a first mesa structure, a first trench, and a first ion implantation fence, respectively; wherein the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; wherein a bottom surface of the second ion implantation fence is not lower than a bottom surface of the second type semiconductor layer; and
the second ion implantation fence is formed around the second trench and the second trench is formed around the second mesa structure; wherein an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.
11. The micro-LED according to clause 10, wherein the second trench extends down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.
12. The micro-LED according to clause 11, wherein the bottom surface of the second ion implantation fence is higher than or aligned with a bottom surface of the second trench.
13. The micro-LED according to clause 10, wherein the second trench does not extend down through the bottom surface of the second type semiconductor layer.
14. The micro-LED according to clause 13, wherein the bottom surface of the second ion implantation fence is lower than or aligned with a bottom surface of the second trench.
15. The micro-LED according to clause 13, wherein the bottom surface of the second ion implantation fence is higher than a bottom surface of the second trench.
16. The micro-LED according to clause 10, wherein a top surface of the second ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer; or the top surface of the second ion implantation fence is higher than the top surface of the second type semiconductor layer.
17. The micro-LED according to clause 10, wherein the first mesa structure comprises one or more stair structures; and the second mesa structure comprises one or more stair structures.
18. The micro-LED according to clause 10, wherein a width of the first trench is not greater than 50% of a diameter of the first mesa structure; and a width of the second trench is not greater than 50% of a diameter of the second mesa structure.
19. The micro-LED according to clause 18, wherein the width of the first trench is not greater than 200 nm; and the width of the second trench is not greater than 200 nm.
20. The micro-LED according to clause 10, wherein the first ion implantation fence comprises a first light absorption material, the second ion implantation fence comprises a second light absorption material; wherein a conductive type of the first light absorption material is the same as the conductive type of the first type semiconductor, a conductive type of the second light absorption material is the same as the conductive type of the second type semiconductor, and the first light absorption material and the second light absorption material are selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, AlGaN.
21. The micro-LED according to clause 9, wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.
22. The micro-LED according to clause 1, further comprising a bottom isolation layer filled in the trench.
23. The micro-LED according to clause 22, wherein a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
24. The micro-LED according to clause 9, further comprising a top contact and a top conductive layer, wherein the top contact and the top conductive layer are formed on a top surface of the second type semiconductor layer.
25. The micro-LED according to clause 10, further comprising a top conductive layer and a top contact; wherein the top contact is formed on a top surface of the second mesa structure; and the top conductive layer is formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implantation fence and fills in the second trench.
26. The micro-LED according to clause 10, wherein ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
27. The micro-LED according to clause 10, wherein the first ion implantation fence is formed by at least implanting ions into the first type semiconductor layer; and the second ion implantation fence is formed by at least implanting ions into the second type semiconductor layer.
28. The micro-LED according to clause 10, wherein a width of the first ion implantation fence is not greater than 50% of a diameter of the first mesa structure; and a width of the second ion implantation fence is not greater than 50% of a diameter of the second mesa structure.
29. The micro-LED according to clause 28, wherein the width of the first ion implantation fence is not greater than 200 nm, the diameter of the first mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 100 nm; and
the width of the second ion implantation fence is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.
30. The micro-LED according to clause 9, wherein a material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN and AlGaN; and a material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN and AlGaN.
31. The micro-LED according to clause 1, further comprising an integrated circuit (IC) backplane under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.
32. The micro-LED according to clause 31, wherein the connection structure is a connection pillar or a metal bonding layer.
33. The micro-LED according to clause 31, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
34. A micro-LED array panel, comprising a plurality of micro-LED according to any one of clauses 1 to 33.
35. A micro-LED array panel, comprising,
a first type semiconductor layer formed in the micro-LED array panel;
a first type cap layer formed on the first type semiconductor layer;
a light emitting layer formed on the first type cap layer;
a second type cap layer formed on the light emitting layer; and
a second type semiconductor layer formed on the second type cap layer;
wherein the first type is P type and the second type is N type; and
the first type semiconductor layer comprises multiple mesa structures, multiple trenches and multiple ion implantation fences separated from the mesa structures by the trenches; wherein a top surface of the ion implantation fence is lower than or aligned with a top surface of the first type semiconductor layer; and
the ion implantation fences are formed around the trenches and between adjacent type mesa structures; wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.
36. The micro-LED array panel according to clause 35, wherein the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure.
37. The micro-LED array panel according to clause 35, wherein a bottom surface of the ion implantation fence is aligned with or higher than a bottom surface of the first type semiconductor layer.
38. The micro-LED array panel according to clause 35, wherein a space between adjacent sidewalls of the mesa structures is not greater than 50% of a diameter of the mesa structure.
39. The micro-LED array panel according to clause 38, wherein the space between the adjacent sidewalls of the mesa structures is not greater than 600 nm.
40. The micro-LED array panel according to clause 35, wherein the ion implantation fence absorbs lights from the first mesa structure; and the ion implantation fence comprises a light absorption material, wherein the light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.
41. The micro-LED array panel according to clause 35, wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.
42. The micro-LED array panel according to clause 35, further comprising a bottom isolation layer filled in the trench.
43. The micro-LED array panel according to clause 42, wherein a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
44. The micro-LED array panel according to clause 35, wherein ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
45. The micro-LED array panel according to clause 35, wherein the ion implantation fence is formed at least by implanting ions into the first type semiconductor layer.
46. The micro-LED array panel according to clause 35, wherein a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
47. The micro-LED array panel according to clause 46, wherein the width of the ion implantation is not greater than 200 nm, a diameter of the first mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.
48. The micro-LED array panel according to clause 35, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
49. The micro-LED array panel according to clause 35, further comprising a top contact formed on a top surface of the second type semiconductor layer.
50. The micro-LED array panel according to clause 35, further comprising an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.
51. The micro-LED array panel according to clause 50, wherein the connection structure is a connection pillar or a metal bonding layer.
52. The micro-LED array panel according to clause 50, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
53. The micro-LED array panel according to clause 35, wherein the trench extends up through a top surface of the first type semiconductor layer to a bottom surface of the first type cap layer.
54. The micro-LED array panel according to clause 35, wherein a top surface of the ion implantation fence is lower than or aligned with a top surface of the trench.
55. The micro-LED array panel according to clause 35, wherein the trench does not extend up through a top surface of the first type semiconductor layer.
56. The micro-LED array panel according to clause 55, wherein the top of the ion implantation fence is higher than or aligned with a top surface of the trench.
57. The micro-LED array panel according to clause 55, wherein the top surface of the ion implantation fence is lower than a top surface of the trench.
58. A method for manufacturing a micro-LED, comprising:
providing an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, a first type cap layer, a light emitting layer, a second type cap layer, and a second type semiconductor layer sequentially from top to bottom;
patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence;
depositing a bottom contact on the mesa structure; and
performing an ion implantation process into the fence to form an ion implantation fence.
59. The method according to clause 58, wherein after patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, the method further comprises:
depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact;
patterning the bottom isolation layer to expose the bottom contact;
depositing metal material on the isolation layer and the bottom contact;
grinding the metal material to a top surface of the bottom isolation layer, to form a connection structure; and
turning the epitaxial structure upside down and bonding the connection structure with an integrated circuit (IC) backplane.
60. The method according to clause 59, wherein in depositing metal material on the isolation layer and the bottom contact, a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
61. The method according to clause 59, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.
62. The method according to clause 61, wherein turning the epitaxial structure upside down and bonding the connection structure with the IC backplane further comprises:
removing the substrate.
63. The method according to clause 61, wherein after turning the epitaxial structure upside down and bonding the connection structure with the IC backplane, the method further comprises:
forming a top contact and a top conductive layer on a top surface of a second type semiconductor layer.
64. The method according to clause 58, wherein depositing the bottom contact on the mesa structure further comprises:
forming a protective mask to protect an area where the bottom contact is not deposited;
depositing material of the bottom contact on the protective mask and on the first type semiconductor layer; and
removing the protective mask from the first type semiconductor layer and removing the material on the protective mask, to form the bottom contact on the mesa structure.
65. The method according to clause 58, wherein performing an ion implantation process into the fence to form the ion implantation fence further comprises:
forming a protective mask on an area not being ion implanted while leaving the fence exposed;
implanting ions into the fence; and
removing the protective mask.
66. The method according to clause 65, wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting with an energy of 0˜500 Kev.
67. The method according to clause 65, wherein in performing the ion implantation process into the fence to form the first ion implantation fence, implanting a dose of 1E10˜9E17.
68. The method according to clause 65, wherein in performing the ion implantation process into the fence to form an ion implantation fence, implanting ions into the ion implantation fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
69. The method according to clause 65, wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
70. The method according to clause 65, wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 200 nm, a diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.
71. The method according to clause 58, wherein in patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is not greater than 50% of a diameter of the mesa structure.
72. The method according to clause 58, wherein a conductive type of the first type semiconductor layer is P type and a conductive type of the second type semiconductor layer is N type, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
73. The method according to clause 58, wherein the ion implantation fence comprises a light absorption material.
74. The method according to clause 73, wherein the light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.
75. A micro-LED, comprising:
a first type semiconductor layer;
a first type cap layer formed on the first type semiconductor layer;
a light emitting layer formed on the first type cap layer;
a second type cap layer formed on the light emitting layer; and
a second type semiconductor layer formed on the second type cap layer;
wherein the first type is P type and the second type is N type;
the second type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure; wherein a bottom surface of the ion implantation fence is not lower than a bottom surface of the second type semiconductor layer; and
the ion implantation fence is formed around the trench and the trench is formed around the mesa structure; wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.
76. The micro-LED according to clause 75, wherein a top surface of the ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer; or the top surface of the ion implantation fence is higher than the top surface of the second type semiconductor layer.
77. The micro-LED according to clause 75, wherein the trench extends down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.
78. The micro-LED according to clause 77, wherein the bottom surface of the ion implantation fence is higher than or aligned with a bottom surface of the second trench.
79. The micro-LED according to clause 75, wherein the trench does not extend down through the bottom surface of the second type semiconductor layer.
80. The micro-LED according to clause 79, wherein the bottom surface of the ion implantation fence is lower than or aligned with a bottom surface of the trench.
81. The micro-LED according to clause 79, wherein the bottom surface of the ion implantation fence is higher than a bottom surface of the trench.
82. The micro-LED according to clause 75, wherein the mesa structure comprises one or more stair structures.
83. The micro-LED according to clause 75, wherein a width of the trench is not greater than 50% of a diameter of the mesa structure.
84. The micro-LED according to clause 83, wherein a width of the trench is not greater than 200 nm.
85. The micro-LED according to clause 75, wherein the ion implantation fence comprises a light absorption material, and the light absorption material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.
86. The micro-LED according to clause 75, wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.
87. The micro-LED according to clause 75, further comprising a dielectric layer filled in the trench.
88. The micro-LED according to clause 87, wherein a material of the dielectric layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
89. The micro-LED according to clause 75, further comprising a top conductive layer formed on a top surface and sidewalls of the mesa structure, on a top surface and sidewalls of the ion implantation fence and filled in the trench.
90. The micro-LED according to clause 75, wherein ions implanted into the ion implantation trench are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
91. The micro-LED according to clause 75, wherein the ion implantation fence is formed by at least implanting ions into the second type semiconductor layer.
92. The micro-LED according to clause 75, wherein a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
93. The micro-LED according to clause 75, wherein a width of the ion implantation fence is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 300 nm.
94. The micro-LED according to clause 75, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
95. The micro-LED according to clause 75, further comprising a top contact formed on a top surface of the second type semiconductor layer.
96. The micro-LED according to clause 75, further comprising an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.
97. The micro-LED according to clause 96, wherein the connection structure is a connection pillar or a metal bonding layer.
98. The micro-LED according to clause 96, further comprising: a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
99. A micro-LED array panel, comprising,
a first type semiconductor layer formed in the micro-LED array panel;
a first type cap layer formed on the first type semiconductor layer;
a light emitting layer formed on the first type cap layer;
a second type cap layer formed on the light emitting layer; and
a second type semiconductor layer formed on the second type cap layer;
wherein the first type is P type and the second type is N type;
the second type semiconductor layer comprises multiple mesa structures, multiple trenches, and multiple ion implantation fences separated from the mesa structures by the trenches; wherein a bottom surface of the ion implantation fence is higher than or aligned with a bottom surface of the second type semiconductor layer; and
the ion implantation fences are formed around the trench and between adjacent mesa structures; wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.
100. The micro-LED array panel according to clause 99, wherein the ion implantation fence is formed around the trench and the trench is formed around the mesa structure.
101. The micro-LED array panel according to clause 99, wherein a top surface of the ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer.
102. The micro-LED array panel according to clause 99, wherein a space between adjacent sidewalls of the mesa structures is not greater than 50% of a diameter of the mesa structure.
103. The micro-LED array panel according to clause 102, wherein the space between the adjacent sidewalls of the mesa structures is not greater than 600 nm.
104. The micro-LED array panel according to clause 99, wherein the ion implantation fence absorbs lights from the mesa structure; and the ion implantation fence comprises a light absorption material, wherein the light absorption material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.
105. The micro-LED array panel according to clause 99, wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.
106. The micro-LED array panel according to clause 99, further comprising a dielectric layer filled in the trench.
107. The micro-LED array panel according to clause 106, wherein a material of the dielectric layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
108. The micro-LED array panel according to clause 99, further comprising a top conductive layer formed on a top surface and sidewalls of the mesa structure, on a top surface and sidewalls of the ion implantation fence, and fills in the trench.
109. The micro-LED array panel according to clause 99, wherein ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
110. The micro-LED array panel according to clause 99, wherein the ion implantation fence is formed by at least implanting ions into the second type semiconductor layer.
111. The micro-LED array panel according to clause 99, wherein a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
112. The micro-LED array panel according to clause 111, wherein the width of the ion implantation is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.
113. The micro-LED array panel according to clause 99, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
114. The micro-LED array panel according to clause 99, further comprising: a top contact formed on a top surface of the second type semiconductor layer.
115. The micro-LED array panel according to clause 99, further comprising an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.
116. The micro-LED array panel according to clause 115, wherein the connection structure is a connection pillar or a metal bonding layer.
117. The micro-LED array panel according to clause 115, further comprising: a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
118. The micro-LED array panel according to clause 99, wherein the trench extends down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.
119. The micro-LED array panel according to clause 118, wherein the bottom surface of the ion implantation fence is higher than or aligned with a bottom surface of the trench.
120. The micro-LED array panel according to clause 99, wherein the trench does not extend down through the bottom surface of the second type semiconductor layer.
121. The micro-LED array panel according to clause 120, wherein the bottom surface of the ion implantation fence is lower than or aligned with a bottom surface of the trench.
122. The micro-LED array panel according to clause 99, wherein the bottom surface of the ion implantation fence is higher than a bottom surface of the trench.
123. A method for manufacturing a micro-LED, comprising:
providing an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, a first type cap layer, a light emitting layer, a second type cap layer, and a second type semiconductor layer sequentially from top to bottom;
bonding the epitaxial structure with an integrated circuit (IC) backplane;
patterning the second type semiconductor layer to form a mesa structure, a trench, and a fence;
depositing a top contact on the mesa structure;
performing an ion implantation process into the fence; and
depositing a top conductive layer on a top surface of the second type semiconductor layer, on a top contact, and in the trench.
124. The method according to clause 123, wherein providing the epitaxial structure further comprises:
depositing a bottom contact layer on a top surface of the first type semiconductor layer; and
depositing a metal bonding layer on a top surface of the bottom contact layer.
125. The method according to clause 124, wherein bonding the epitaxial structure with the IC backplane further comprises:
turning the epitaxial structure upside down; and
bonding the metal bonding layer with a contact pad of the IC backplane.
126. The method according to clause 125, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.
127. The method according to clause 126, wherein bonding the epitaxial structure with the IC backplane further comprises:
removing the substrate.
128. The method according to clause 123, wherein patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence further comprises:
etching the second type semiconductor layer to a surface of the light emitting layer.
129. The method according to clause 123, wherein depositing the top contact on the mesa structure further comprises:
forming a protective mask;
depositing a material of the top contact on the protective mask; and
removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask, to form the top contact on the mesa structure.
130. The method according to clause 123, wherein performing the ion implantation process into the fence further comprises:
forming a protective mask on an area not being ion implanted while leaving the fence exposed;
implanting ions into the fence; and
removing the protective mask.
131. The method according to clause 130, wherein in performing the ion implantation process into the fence, implanting with an energy 0˜500 KeV.
132. The method according to clause 130, wherein in performing the ion implantation process into the fence, implanting a dose of 1E10˜9E17.
133. The method according to clause 130, wherein in performing the ion implantation process into the fence, implanting ions into the ion implantation fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
134. The method according to clause 130, wherein in performing the ion implantation process into the fence, a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.
135. The method according to clause 130, wherein in performing the ion implantation process into the fence, a width of the ion implantation fence is not greater than 200 nm, a diameter of the mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.
136. The method according to clause 123, wherein a conductive type of the first type semiconductor layer is P type and a conductive type of the second type semiconductor layer is N type; wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
137. The method according to clause 136, wherein the ion implantation fence comprises a light absorption material.
138. The method according to clause 137, wherein the light absorption material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.
139. A micro-LED, comprising:
a first type semiconductor layer;
a first type cap layer formed on the first type semiconductor layer;
a light emitting layer formed on the first type cap layer;
a second type cap layer formed on the light emitting layer; and
a second type semiconductor layer formed on the second type cap layer;
wherein the first type is P type and the second type is N type;
the first type semiconductor layer comprises a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure; wherein a top surface of the first ion implantation fence is lower than or aligned with a top surface of the first type semiconductor layer;
the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; wherein a bottom surface of the second ion implantation fence is higher than or aligned with a bottom surface of the second type semiconductor layer;
the first ion implantation fence is formed around the first trench and the first trench is formed around the first mesa structure; wherein an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure; and
the second ion implantation fence is formed around the second trench and the second trench is formed around the second mesa structure, wherein an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.
140. The micro-LED according to clause 139, wherein a center of the first mesa structure is aligned with a center of the second mesa structure, a center of the first trench is aligned with a center of the second trench, and a center of the first ion implantation fence is aligned with a center of the second ion implantation fence.
141. The micro-LED according to clause 139, wherein a bottom surface of the first ion implantation fence is aligned with or higher than a bottom surface of the first type semiconductor layer, and a top surface of the second ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer; or
the bottom surface of the first ion implantation fence is lower than the bottom surface of the first type semiconductor layer, and the top surface of the second ion implantation fence is higher than the top surface of the second type semiconductor layer.
142. The micro-LED according to clause 139, wherein the first trench extends up through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer; and/or, the second trench extends down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.
143. The micro-LED according to clause 142, wherein the top surface of the first ion implantation fence is lower than or aligned with a top surface of the first trench; and/or, the bottom surface of the second ion implantation fence is higher than or aligned with a bottom surface of the second trench.
144. The micro-LED according to clause 139, wherein the first trench does not extend up through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer; and/or, the second trench does not extend down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.
145. The micro-LED according to clause 144, wherein the top surface of the first ion implantation fence is higher than or aligned with a top surface of the first trench; and/or, the bottom surface of the second ion implantation fence is lower than or aligned with a bottom surface of the second trench.
146. The micro-LED according to clause 144, wherein the top surface of the first ion implantation fence is lower than a top surface of the first trench; and/or, the bottom surface of the second ion implantation fence is higher than a bottom surface of the second trench.
147. The micro-LED according to clause 139, wherein the first mesa structure comprises one or more stair structures; and/or, the second mesa structure comprises one or more stair structures.
148. The micro-LED according to clause 139, wherein a width of the first trench is not greater than 50% of a diameter of the first mesa structure; and/or a width of the second trench is not greater than 50% of a diameter of the second mesa structure.
149. The micro-LED according to clause 148, wherein the width of the first trench is not greater than 200 nm; and/or, the width of the second trench is not greater than 200 nm.
150. The micro-LED according to clause 139, wherein the first ion implantation fence comprises a first light absorption material; and/or, the second ion implantation fence comprises a second light absorption material; wherein
the first light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and/or, the second light absorption material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.
151. The micro-LED according to clause 139, wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.
152. The micro-LED according to clause 139, further comprising a bottom isolation layer filled in the trench; and a dielectric layer filled in the second trench.
153. The micro-LED according to clause 152, wherein a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, or TiO2 and ZrO2; and/or, a material of the dielectric layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
154. The micro-LED according to clause 139, further comprising a top conductive layer formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implantation fence, and filled in the second trench.
155. The micro-LED according to clause 139, wherein ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and/or, ions implanted into the second ion implantation fence is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
156. The micro-LED according to clause 139, wherein the first ion implantation fence is formed by at least implanting ions into the first type semiconductor layer; and/or, the second ion implantation fence is formed by at least implanting ions into the second type semiconductor layer.
157. The micro-LED according to clause 139, wherein a width of the first ion implantation fence is not greater than 50% of a diameter of the first mesa structure; and/or, a width of the second ion implantation fence is not greater than 50% of a diameter of the second mesa structure.
158. The micro-LED according to clause 157, wherein the width of the first ion implantation fence is not greater than 200 nm, the diameter of the first mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm; and/or,
the width of the second ion implantation fence is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 300 nm.
159. The micro-LED according to clause 139, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and/or, a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
160. The micro-LED according to clause 139, further comprising: a top contact formed on a top surface of the second type semiconductor layer.
161. The micro-LED according to clause 139, further comprising an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.
162. The micro-LED according to clause 161, wherein the connection structure is a connection pillar or a metal bonding layer.
163. The micro-LED according to clause 161, wherein further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
164. A micro-LED array panel, comprising,
a first type semiconductor layer formed in the micro-LED array panel;
a first type cap layer formed on the first type semiconductor layer;
a light emitting layer formed on the first type cap layer;
a second type cap layer formed on the light emitting layer; and
a second type semiconductor layer formed on the second type cap layer;
wherein the first type is P type and the second type is N type;
the first type semiconductor layer comprises multiple first mesa structures, multiple first trenches, and multiple first ion implantation fences separated from the first mesa structures by the first trenches; a top surface of the first ion implantation fence is lower than or aligned with a top surface of the first type semiconductor layer;
the first ion implantation fences are formed around the first trench and between adjacent first type mesa structures; wherein an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure;
the second type semiconductor layer comprises multiple second mesa structures, multiple second trenches, and multiple second ion implantation fences separated from the second mesa structures by the second trenches; wherein a bottom surface of the second ion implantation fence is higher than or aligned with a bottom surface of the second type semiconductor layer; and
the second ion implantation fences are formed around the second trench and between adjacent second mesa structures; wherein an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.
165. The micro-LED array panel according to clause 164, wherein a center of the first mesa structure is aligned with a center of the second mesa structure, a center of the first trench is aligned with a center of the second trench, and a center of the first ion implantation region is aligned with a center of the first ion implantation region.
166. The micro-LED array panel according to clause 164, wherein the first ion implantation fence is formed around the first mesa structure and the first trench is formed around the first mesa structure; and the second ion implantation fence is formed around the second mesa structure and the second trench is formed around the second mesa structure.
167. The micro-LED array panel according to clause 164, wherein a bottom surface of the first ion implantation fence is aligned with or higher than a bottom surface of the first type semiconductor layer; and/or,
a top surface of the second ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer.
168. The micro-LED array panel according to clause 164, wherein a space between adjacent sidewalls of the first mesa structures is not greater than 50% of a diameter of the first mesa structure; and/or, a space between adjacent sidewalls of the second mesa structures is not greater than 50% of a diameter of the second mesa structure.
169. The micro-LED array panel according to clause 168, wherein the space between the adjacent sidewalls of the first mesa structures is not greater than 600 nm, and the space between the adjacent sidewalls of the second mesa structures is not greater than 600 nm.
170. The micro-LED array panel according to clause 164, wherein the first ion implantation fence absorbs lights from the first mesa structure; and the second ion implantation fence absorbs lights from the second mesa structure.
171. The micro-LED array panel according to clause 164, wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.
172. The micro-LED array panel according to clause 164, further comprising a bottom isolation layer filled in the first trenches; and a dielectric layer filled in the second trenches.
173. The micro-LED array panel according to clause 172, wherein a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2; and a material of the dielectric layer is selected from one or more of S SiO2, SiNx, Al2O3, HfO2, TiO2, or ZrO2.
174. The micro-LED array panel according to clause 164, further comprising a top conductive layer formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implantation fence, and filled in the second trench.
175. The micro-LED array panel according to clause 164, wherein ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and/or, ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
176. The micro-LED array panel according to clause 164, wherein the first ion implantation fence is formed by at least implanting ions into the first type semiconductor layer.
177. The micro-LED array panel according to clause 164, wherein a width of the first ion implantation fence is not greater than 50% of a diameter of the first mesa structure; and a width of the second ion implantation fence is not greater than 50% of a diameter of the second mesa structure.
178. The micro-LED array panel according to clause 178, wherein the width of the ion implantation is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm; and
the width of the second ion implantation is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.
179. The micro-LED array panel according to clause 164, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and/or, a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
180. The micro-LED array panel according to 164, further comprising: a top contact formed on a top surface of the second type semiconductor layer.
181. The micro-LED array panel according to clause 164, further comprising an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.
182. The micro-LED array panel according to clause 181, wherein the connection structure is a connection pillar or a metal bonding layer.
183. The micro-LED array panel according to clause 181, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
184. The micro-LED array panel according to clause 164, wherein the first trench extends up through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer; and/or, the second trench extends down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.
185. The micro-LED array panel according to clause 184, wherein the top surface of the first ion implantation fence is lower than or aligned with a top surface of the first trench; and/or, the bottom surface of the second ion implantation fence is higher than or aligned with a bottom surface of the second trench.
186. The micro-LED array panel according to clause 164, wherein the first trench does not extend up through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer; and/or, the second trench does not extend down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.
187. The micro-LED array panel according to clause 186, wherein the top surface of the first ion implantation fence is higher than or aligned with a top surface of the first trench; and/or, the bottom surface of the second ion implantation fence is lower than or aligned with a bottom surface of the first trench.
188. The micro-LED array panel according to clause 186, wherein the top surface of the first ion implantation fence is lower than a top surface of the first trench; and/or, the bottom surface of the second ion implantation fence is higher than a bottom surface of the second trench.
189. A method for manufacturing a micro-LED, comprising:
a process I comprising patterning a first type semiconductor layer; and implanting first ions into the first type semiconductor layer; and
a process II comprising patterning a second type semiconductor layer; and implanting second ions into the second type semiconductor layer.
190. The method according to clause 189, wherein the process I further comprises:
providing an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, a first type cap layer, a light emitting layer, a second type cap layer, and a second type semiconductor layer sequentially from top to bottom;
patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence;
depositing a bottom contact on the mesa structure;
performing an ion implantation process into the fence, to form an ion implantation fence;
depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact;
patterning the bottom isolation layer to expose the bottom contact;
depositing metal material on the isolation layer and the bottom contact;
grinding the metal material to a top surface of the bottom isolation layer, to form a connection structure;
turning the epitaxial structure upside down and bonding the connection structure with an integrated circuit (IC) backplane.
191. The method according to clause 189, wherein depositing the bottom contact on the mesa structure further comprises:
forming a protective mask to protect an area where the bottom contact is not being deposited;
depositing a material of the bottom contact on the protective mask and on the first type semiconductor layer; and
removing the protective mask from the first type semiconductor layer and removing the material on the protective mask, to form the bottom contact on the mesa structure.
192. The method according to clause 190, wherein performing the ion implantation process into the fence to form the ion implantation fence further comprises:
forming a protective mask on an area not being ion implanted while leaving the fence exposed;
implanting ions into the fence; and
removing the protective mask.
193. The method according to clause 192, wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting with an energy of 0˜500 Kev, and implanting a dose of 1E10˜9E17.
194. The method according to clause 192, wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting ions into the fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
195. The method according to clause 192, wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure; the width of the ion implantation fence is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.
196. The method according to clause 190, wherein in patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is not greater than 50% of a diameter of the mesa structure.
197. The method according to clause 189, wherein the mesa structure, the trench, and the fence are a first mesa structure, a first trench, and a first fence respectively; wherein the process II further comprises:
patterning the second type semiconductor layer to form a second mesa structure, a second trench, and a second fence;
depositing a top contact on the second mesa structure;
performing an ion implantation process into the second fence; and
depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the second trench.
198. The method according to clause 197, wherein depositing the top contact on the second mesa structure further comprises:
forming a protective mask;
depositing a material of the top contact on the protective mask; and
removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask, to form a top contact on the second mesa structure.
199. The method according to clause 197, wherein performing the ion implantation process into the second fence further comprises:
forming a protective mask on an area not being implanted while leaving the second fence exposed;
implanting the ions into the second fence; and
removing the protective mask.
200. The method according to clause 197, wherein in performing the ion implantation process into the second fence, implanting with an energy of 0˜500 KeV and implanting a dose of 1E10˜9E17.
201. The method according to clause 197, wherein in performing the ion implantation process into the second fence, implanting ions into the second fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.
202. The method according to clause 197, wherein in performing the ion implantation process into the second fence, a width of the second ion implantation fence is not greater than 50% of a diameter of the second mesa structure; the width of the second ion implantation fence is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.
203. The method according to clause 190, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate; the turning the epitaxial structure upside down and bonding the connection structure with the IC backplane further comprises:
removing the substrate.
204. The method according to clause 190, wherein in depositing the bottom isolation layer on the first type semiconductor layer and the bottom contact, a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.
205. The method according to clause 190, wherein the ion implantation fence comprises a light absorption material.
206. The method according to clause 205, wherein a conductive type of the light absorption material is the same as a conductive type of the first type semiconductor layer, and the light absorption material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.
207. The method according to clause 190, wherein a conductive type of the first type semiconductor layer is P type and a conductive type of the second type semiconductor layer is N type; a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN or p-AlGaN; and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.
It should be noted that relational terms herein such as “first” and “second” are used only to differentiate an entity or operation from another entity or operation, and do not require or imply any actual relationship or sequence between these entities or operations. Moreover, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items.
As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.
In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain adaptations and modifications of the described embodiments can be made. Other embodiments can be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. It is also intended that the sequence of steps shown in figures are only for illustrative purposes and are not intended to be limited to any particular sequence of steps. As such, those skilled in the art can appreciate that these steps can be performed in a different order while implementing the same method.
In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.
Number | Date | Country | Kind |
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PCT/CN2022/075284 | Jan 2022 | WO | international |
The disclosure claims the benefits of priority to PCT Application No. PCT/CN2022/075284, filed on Jan. 31, 2022, which is incorporated herein by reference in its entirety.