The disclosure relates to a semiconductor device, and more particularly to a micro light-emitting device, a micro light-emitting diode, and a method for manufacturing a micro light-emitting device.
A micro light-emitting diode (mLED) has advantages of being self-emitting, high efficiency, low power consumption, high luminous intensity, high stability, ultra-high resolution and color saturation, fast response rate, and long lifespan, and is widely applied in display, optical communication, indoor positioning, and biological and medical fields. mLED is expected to further expand its application to wearable/implantable devices, augmented display/virtual reality, in-vehicle display, ultra-large display and optical communication/optical interconnection, medical detection, intelligent vehicle lights, spatial imaging, and many other fields. It has a clear and considerable market prospect.
There are still many technical challenges to be overcome for the mLED, and one of key challenges is improving yield of mass transfer of the mLED.
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Therefore, an object of the disclosure is to provide a micro light-emitting device, a micro light-emitting diode, and a method of manufacturing a micro light-emitting device that can alleviate at least one of the drawbacks of the prior art.
According to a first aspect of the disclosure, a micro light-emitting device includes a micro light-emitting diode, a base frame, and a bridging structure.
The micro light-emitting diode includes a semiconductor epitaxial structure, a first contact electrode, a second contact electrode, a first bonding electrode, and a second bonding electrode.
The semiconductor epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer. The semiconductor epitaxial structure has a first mesa surface defined by the first semiconductor layer that is exposed from a recess of the semiconductor epitaxial structure, a second mesa surface defined by the second semiconductor layer, and a connecting wall disposed between and interconnecting the first mesa surface and the second mesa surface. The connecting wall cooperates with the first mesa surface to form a first included angle that ranges from 105° to 165°.
The first contact electrode is disposed on the first mesa surface and electrically connected to the first semiconductor layer. The second contact electrode is disposed on the second mesa surface and electrically connected to the second semiconductor layer. The first bonding electrode is disposed on and electrically connected to the first contact electrode, and the second bonding electrode is disposed on and electrically connected to the second contact electrode.
The base frame is disposed on and supports the micro light-emitting diode. The bridging structure interconnects the micro light-emitting diode and the base frame, and a periphery of the micro light-emitting diode is disposed on the bridging structure.
According to a second aspect of the disclosure, a micro light-emitting diode includes elements and structures the same as the aforementioned micro light-emitting diode.
According to a third aspect of the disclosure, a method for manufacturing a micro light-emitting device includes steps of:
Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment(s) with reference to the accompanying drawings. It is noted that various features may not be drawn to scale.
Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.
It should be noted herein that for clarity of description, spatially relative terms such as “top,” “bottom,” “upper,” “lower,” “on,” “above,” “over,” “downwardly,” “upwardly” and the like may be used throughout the disclosure while making reference to the features as illustrated in the drawings. The features may be oriented differently (e.g., rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be interpreted accordingly.
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The micro light-emitting diode includes a semiconductor epitaxial structure, a first contact electrode 104, a second contact electrode 105, a first bonding electrode 107 and a second bonding electrode 108. The semiconductor epitaxial structure includes a first semiconductor layer 101, a second semiconductor layer 103, and an active layer 102 disposed between the first semiconductor layer 101 and the second semiconductor layer 103. The semiconductor epitaxial structure has a first mesa surface (S1) defined by a the first semiconductor layer 101 that is exposed from a recess of the semiconductor epitaxial structure, a second mesa surface (S2) defined by the second semiconductor layer 103, and a connecting wall (W1) disposed between and interconnecting the first mesa surface (S1) and the second mesa surface (S2). The first contact electrode 104 is disposed on the first mesa surface (S1) and electrically connected to the first semiconductor layer 101. The second contact electrode 105 is disposed on the second mesa surface (S2) and electrically connected to the second semiconductor layer 103. The first bonding electrode 107 is disposed on and electrically connected to the first contact electrode 104. The second bonding electrode 108 is disposed on and electrically connected to the second contact electrode 105.
The first semiconductor layer 101 may be made of a group III-V or group II-VI compound semiconductor material, and may be doped with a first dopant. The first semiconductor layer 101 may be made of a semiconductor material having a composition that is represented by InxAly1Ga1-x1-y1N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), e.g., GaN, AlGaN, InGaN, InAlGaN, etc., or a material selected from AlGaAs, GaP, GaAs, GaAsP, and AlGaInP. In addition, the first dopant may be an n-type dopant, such as Si, Ge, Sn, Se, and Te. When the first dopant is an n-type dopant, the first semiconductor layer 101 doped with the first dopant is an n-type semiconductor layer. The first dopant may be a p-type dopant, such as Mg, Zn, Ca, Sr, and Ba. The first semiconductor layer 101 doped with the p-type dopant is a p-type semiconductor layer. A surface of the first semiconductor layer 101 away from the active layer 102 is a light-emitting surface. To improve light extraction efficiency of the micro light-emitting diode, the light-emitting surface of the first semiconductor layer 101 may be roughened to form a roughened structure. In some embodiments, the light-emitting surface of the first semiconductor layer 101 may not be roughened.
The active layer 102 is disposed between the first semiconductor layer 101 and the second semiconductor layer 103. The active layer 102 is a region for electrons and holes to recombine for light emitting. Depending on a wavelength of light emitted by the active layer 102, materials for the active layer 102 may vary. The active layer 102 may have a single quantum well structure or a multiple quantum well structure. The active layer 102 may include well layer(s) and barrier layer(s), and a bandgap of the barrier layer is greater than that of the well layer. By adjusting a composition of the semiconductor material of the active layer 102, the active layer 102 may emit a pre-determined wavelength of light.
The second semiconductor layer 103 is disposed on the active layer 102, and may be made of a group III-V or group II-VI compound semiconductor material. The second semiconductor layer 103 may be doped with a second dopant. The second semiconductor layer 103 may be made of a semiconductor material having a composition that is represented by Inx2Aly2Ga1-x2-y2N (0≤x2≤1, 0≤y2≤1, 0≤x2+y2≤1), or a material selected from AlGaAs, GaP, GaAs, GaAsP, and AlGaInP. When the second dopant is a p-type dopant, such as Mg, Zn, Ca, Sr, and Ba, the second semiconductor layer 103 doped with the second dopant is a p-type semiconductor layer. The second dopant may be an n-type dopant, such as Si, Ge, Sn, Se, and Te. When the second semiconductor layer 103 doped with the n-type dopant, the second semiconductor layer 103 is an n-type semiconductor layer. When the first semiconductor layer 101 is an n-type semiconductor layer, the second semiconductor layer 103 is a p-type semiconductor layer. Conversely, when the first semiconductor layer 101 is a p-type semiconductor layer, the second semiconductor layer 103 is an n-type semiconductor layer.
The semiconductor epitaxial structure may also include other layers, such as a current spreading layer, a window layer, or an ohmic contact layer, etc. Each of the layers may have a different doping concentration or component content. The semiconductor epitaxial structure may be formed on a growth substrate 100 (see
To increase reliability of the micro light-emitting diode, the micro light-emitting diode further includes an insulation layer 106 that covers the connecting wall (W1), the first mesa surface (S1), and the second mesa surface (S2). The insulation layer 106 may be made of SiNx (e.g., Si3N4) or SiO2, and has a thickness no smaller than 1 μm.
The first contact electrode 104 and the second contact electrode 105 may be made of, for example, Au or AuZn. In certain embodiments, the first contact electrode 104 has a multi-layered structure which includes Au/Ni/Au/GeAu/Ni/Au, and the second contact electrode 105 has a multi-layered structure which includes Au/AuZn/Au. The first bonding electrode 107 and the second bonding electrode 108 may be made of one of Au, Ag, Al, Pt, Ti, Ni, Cr, or combinations thereof. In some embodiments, the first bonding electrode 107 and the second bonding electrode 108 may be made of a reflective metal such as Au or Al, which may increase the light extraction efficiency and luminous intensity of the micro light-emitting diode. Each of the first bonding electrode 107 and the second bonding electrode 108 has a thickness ranging from 0.5 μm to 3 μm.
The micro light-emitting device further includes a bridging structure 140 and a base frame 150 supporting the micro light-emitting diode. The base frame 150 is disposed on the micro light-emitting diode, and has an indented receiving space 130 for disposing the micro light-emitting diode. The bridging structure 140 is connected to the micro light-emitting diode and the base frame 150. The base frame 150 includes a substrate 120 and a bonding layer 110 disposed on the substrate 120. The bonding layer 110 may be made of a benzocyclobutene (BCB) adhesive, silicone, an ultraviolet (UV) adhesive or resin. The resin may be gamma-butyrolactone, 1-methoxy-2-propyl acetate, polyamic acid, or combinations thereof, or a mixture of benzocyclobutene or bisphenol fluorene epoxy acrylate additives with propylene glycol monomethyl ether acetate. The bridging structure 140 may be made of a dielectric material, a metal material, or a semiconductor material. In certain embodiments, the bridging structure 140 is integrally formed with the insulation layer 106, and is connected to and extends from the insulation layer 106 away from the semiconductor epitaxial structure. The bridging structure 140 may also be seen as a horizontal portion 1061 of the insulation layer 106. The bridging structure 140 is disposed on the bonding layer 110, connects the bonding layer 110 to the micro light-emitting diode, and interconnects the micro light-emitting diode and the base frame 150 with a periphery of the micro light-emitting diode being disposed on the bridging structure 140.
The micro light-emitting diode is separated from the base frame 150 by transfer printing. In some cases, the micro light-emitting device includes a sacrificial layer 109 that is disposed in the indented receiving space 130 and between the micro light-emitting diode and the base frame 150. In certain circumstances, the sacrificial layer 109 has a higher removal efficiency than that of the micro light-emitting diode and may be removed by chemical degradation or physical degradation, such as UV decomposition, etching, or pyrolysis. Examples of a material for the sacrificial layer 109 include polydimethylsiloxane (PDMS), silicone, a pyrolysis adhesive, and a UV adhesive. A part of the sacrificial layer 109 covering the connecting wall (W1) has a thickness no smaller than 1 μm measured from the connecting wall (W1).
In the prior art, the first mesa surface (S1) and the second mesa surface (S2) have a difference in height, and the connecting wall (W1) is substantially vertical. When the sacrificial layer 109 covers the first mesa surface (S1), the second mesa surface (S2), and the connecting wall (W1), the sacrificial layer 109 may easily break. Then, during bonding of the micro light-emitting diode to the substrate 120, material of the bonding layer 110 may easily diffuse into the sacrificial layer 109 and contacts the micro light-emitting diode, thereby causing an abnormal transfer of the micro light-emitting diode and affecting yield of the product.
To resolve the above-mentioned problem, in the present disclosure, the connecting wall (W1), which is tilted, cooperates with the first mesa surface (S1) to form a first included angle (θ1), where 105°≤θ1≤165°. In some embodiments, 120°≤θ1≤150°. A part of the insulation layer 106 that covers the connecting wall (W1) cooperates with a part of the insulation layer 106 that covers the first mesa surface (S1) to form a second included angle (θ2), where 105°≤θ2≤165°. In some embodiments, 120°≤θ2≤150°. The sacrificial layer 109 may then better cover the connecting wall (W1), and breakage of the sacrificial layer 109 may be avoided, so that the material of the bonding layer 110 may not diffuse into the sacrificial layer 109 and contacts the micro light-emitting diode, so the abnormal transfer of the micro light-emitting diode may be avoided.
In some embodiments, the first bonding electrode 107 extends onto the second mesa surface (S2) and is flush with the second bonding electrode 108. By virtue of the first bonding electrode 107 covering the connecting wall (W1), and connecting to the second mesa surface (S2), the sacrificial layer 109 may better cover the connecting wall (W1) without breakage, thereby improving transfer yield of the micro light-emitting diode. Meanwhile, the first bonding electrode 107 is flush with the second bonding electrode 108, which is conducive to subsequent packaging and improves packaging yield.
The present disclosure also provides a micro light-emitting diode as described in the aforesaid embodiment of the light-emitting device.
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Then, the base frame (150) having the indented receiving space 130 is provided on the sacrificial layer 109 to support the micro light-emitting diode.
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Next, the micro light-emitting diode is separated from the base frame 150 by a transfer printing and is transferred onto a packaging substrate (not shown in the figure).
The present disclosure may improve the transfer yield of the micro light-emitting diode by designing the connecting wall (W1) to have the first included angle (θ1). By having the first bonding electrode 107 extending onto the second mesa surface (S2), the sacrificial layer 109 may better cover the slanted connecting wall (W1), thereby reducing the difference in height between the first mesa surface (S1) and the second mesa surface (S2) and resolving the breaking of the sacrificial layer 109 during the bonding process. In this way, the material of the bonding layer 110 may not diffuse into the sacrificial layer 109 and contacts the micro light-emitting diode, thereby avoiding the abnormal transfer of the micro light-emitting diode. The transfer yield of the micro light-emitting diode is then improved. In addition, each of the first bonding electrode 107 and the second bonding electrode 108 may be made of a reflective metal material to improve reflection of light, thereby enhancing the luminous intensity of the micro light-emitting diode and improving wall-plug efficiency (WPE). The first bonding electrode 107 and the second bonding electrode 108 of the micro light-emitting diode are flush with each other, which is conducive to the subsequent packaging, and improves the packaging yield.
In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment(s). It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects; such does not mean that every one of these features needs to be practiced with the presence of all the other features. In other words, in any described embodiment, when implementation of one or more features or specific details does not affect implementation of another one or more features or specific details, said one or more features may be singled out and practiced alone without said another one or more features or specific details. It should be further noted that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure.
While the disclosure has been described in connection with what is(are) considered the exemplary embodiment(s), it is understood that this disclosure is not limited to the disclosed embodiment(s) but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
This application is a continuation-in-part (CIP) of International Application No. PCT/CN2021/080560, filed on Mar. 12, 2021, which is incorporated herein by reference in its entirety.
Number | Date | Country | |
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Parent | PCT/CN2021/080560 | Mar 2021 | US |
Child | 18462798 | US |