Claims
- 1. A semiconductor integrated circuit formed on a semiconductor body, comprising:
- a central processing unit (CPU) for processing data;
- memory means for storing data and being able to be controllably accessed;
- a common bus, including at least a data bus, coupled to said central processing unit and coupled to said memory means;
- first inhibition means, coupled to said data bus, providing a first inhibiting operation thereby preventing access operations to said memory means from outside said semiconductor body, via said data bus, said first inhibition means releasing said first inhibiting operation in response to a signal from outside said semiconductor body; and
- second inhibition means, coupled to said data bus, providing a second inhibiting operation thereby preventing access operations to said memory means from outside said semiconductor body, via said data bus, and permanently disabling the access operations to said memory means from outside said semiconductor body irrespective of a releasing of said first inhibiting operation after said second inhibiting operation takes effect.
- 2. A semiconductor integrated circuit according to claim 1, wherein said integrated circuit is a microcomputer.
- 3. A semiconductor integrated circuit according to claim 2, wherein said memory means is a programmable read only memory (PROM).
- 4. A semiconductor integrated circuit according to claim 3, wherein said PROM is an electrically erasable and programmable read only memory (EEPROM).
- 5. A semiconductor integrated circuit according to claim 3, wherein said programmable read only memory comprises a first PROM region and a second PROM region, each of said first and second PROM regions is accessible for write and read operations, and wherein the write and read operations of said first PROM region are selectively controlled in response to control signals from said CPU via said common bus, and external signals received from outside said semiconductor body, and the write and read operations of said second PROM region are controlled by said external signals.
- 6. A semiconductor integrated circuit according to claim 5, further including read means, coupled to said PROM for reading out data from said first and second PROM regions to said data bus.
- 7. A semiconductor integrated circuit according to claim 6, wherein said read means includes a sense amplifier.
- 8. A semiconductor integrated circuit according to claim 6, wherein said PROM is an electrically erasable and programmable read only memory (EEPROM) including first and second EEPROM regions corresponding to said first and second PROM regions, respectively.
- 9. A semiconductor integrated circuit according to claim 8, wherein said second EEPROM region includes an area for write/read inhibition binary data which is input from outside said semiconductor body via said data bus, and said first inhibition means operates in response to said inhibition binary data.
- 10. A semiconductor integrated circuit according to claim 9, wherein memory location selection in said EEPROM is effected in response to an address signal from said CPU during a non-testing mode of said microcomputer and during a test mode thereof memory location selection in said EEPROM is effected in response to an address signal received from outside said semiconductor body.
- 11. A semiconductor integrated circuit according to claim 10, wherein said external signals are received during said test mode and said control signals are received from said CPU, via said common bus, during the non-testing mode.
- 12. A semiconductor integrated circuit according to claim 11, wherein said read means is coupled to said first and second EEPROM regions via a decoder circuit for reading out data to said data bus during the non-testing and testing modes, respectively.
- 13. A semiconductor integrated circuit according to claim 12, wherein said read means includes a sense amplifier.
Priority Claims (1)
Number |
Date |
Country |
Kind |
60-217844 |
Oct 1985 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/387,383, filed on Jul. 31, 1989, now abandoned, which in turn is a continuation application of Ser. No. 06/914,674, filed Oct. 2, 1986, now abandoned.
US Referenced Citations (9)
Continuations (2)
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Number |
Date |
Country |
Parent |
387383 |
Jul 1989 |
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Parent |
914674 |
Oct 1986 |
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