Patent Grant
8731737
The present application claims the benefit under 35 U.S.C. §119 of German Patent Application No. 102010028259.6, filed on Apr. 27, 2010, which is expressly incorporated herein by reference in its entirety.
The present invention is directed to a microcontroller having a computing unit and a logic circuit, and to a method for carrying out computations by a microcontroller for a regulation or a control in a vehicle.
Computationally intensive mathematical problems in control units in the automotive sector may be solved in various ways. Standard processors are not generally usable in the embedded region. Factors such as high costs, limited temperature range, poor predictability, and safety requirements preclude such use. Therefore, specialized microcontrollers are used in the embedded region. Computation on these microcontrollers is much slower, since as a rule the clock frequency is lower, fewer caches are available, the pipeline stages do not implement high parallelization, no speculative computations are performed, etc. For this reason, multicore computing units or additional digital signal processors (DSP) are used in the embedded region in the case of high computing requirements. A multicore system for use in the automotive sector is described in European Patent No. EP-1456720. A system controller in the automotive sector, having a digital signal processor, is described in German Patent Application No. DE-102005022247.
An example logic circuit of the microcontroller proposed herein is able to carry out computations in the microcontroller by providing computed exponential functions, thus allowing quicker, more advantageous (from the standpoint of costs and space requirements), more energy-efficient, and more reliable computations of tasks of the microcontroller, for which the computation of exponential functions represents a subtask. One particular advantage is that by transferring the exponential function computations to the logic circuit, the computing unit of the microcontroller is relieved of computations and access operations. Due to the option for configuring the logic circuit, particularly flexible but more efficient computation support is achieved.
Since the logic circuit is present as a separate hardware component outside the processor, there are no direct dependencies on the processor. Mutual influences on the execution speed of the further processor functions are thus avoided. The execution of the software is not directly influenced. Despite the limited functionality, the implemented functionality may still be used in a very flexible manner, and for this purpose is controlled by a software processor.
In addition, hard real-time requirements in the embedded region may also be met using this approach.
The logic circuit may be used in the microcontroller in a particularly flexible manner when the logic circuit is configurable, for example is able to read configuration data from a configuration data memory for the purpose of configuring the logic circuit. Such data may relate to which exponential function is to be computed, i.e., may relate to the free parameters or constants of the exponential function, for example. It may also be specified that the logic circuit computes exponential functions of sums, and it may be provided that the number of summands to be added is configurable. In addition, the summation of various exponential functions may be provided, the parameters and the number of exponential functions to be summed being configurable for each of the exponential functions to be summed. Furthermore, the configuration may also relate to the type of computation of the exponential function, for example if various computation paths are possible via the logic circuit, or if a parallelization of computations, for example, is possible within the logic circuit. Optionally, the logic circuit may also compute the values themselves which are to be summed, and which are formed by computing an internal term.
The configuration data may advantageously be generated by the microcontroller or by a computing unit of the microcontroller, preferably as a function of the task to be computed or as a function of certain vehicle information, and may be written in a configuration data memory to which the logic circuit has access. The logic circuit may thus be flexibly adapted to the tasks to be computed, as well as to other conditions.
For efficient implementation of the configuration, the logic circuit may have a connected (local) memory in which the configuration data are stored.
If the use of a local memory is to be eliminated, it may also be advantageous to store the configuration data in a global memory to which the logic circuit may have direct memory access (DMA), for example, in order to allow a rapid and reliable configuration in this approach as well.
The proposed microcontroller may be used in a particularly advantageous manner to compute output variables using Bayesian regression, based on input variables and training values, the exponential function computations required for the Bayesian regression being performed by the specialized logic circuit. The microcontroller thus allows more efficient and accurate control of vehicle functions, with a particularly efficient design of the microcontroller.
Exemplary embodiments of the present invention are illustrated in the figures and explained in greater detail below.
In the description of the example embodiment of the present invention, a logic circuit refers to a pure, in particular hard-wired, logic circuit which does not have a processor that executes software.
Global memory units 12 and 13 may be designed as RAM or flash memory, for example. Providing two global memories in
Circuit system 14 is designed to compute an exponential function, or, since it is configurable, to compute various exponential functions and optionally the sum of exponential functions. The circuit system represents an automatic state machine which retrieves input data for the computation from an input memory, and in the course of the computation computes an exponential function, and optionally via a sequence control in communication with the computing unit or with processor core 11 of the microcontroller computes the sum of exponential functions in the required loop operations, and is thus used, in a manner of speaking, as a hardware accelerator in carrying out complex tasks of the microcontroller or computations of processor core 11. Logic circuit 14 is present as a separate hardware component outside the processor.
Many implementations of the computation of exponential functions in hardware circuits are known. For example, a BKM (Bajard, Kla, Muller) algorithm, a CORDIC algorithm, or conventional expansion series may be used for approximating exponential functions. Other methods which approximately simulate an exponential function are also possible.
One technology used in the automotive sector for regulating and controlling systems is the representation of system-specific properties with the aid of characteristic maps. The characteristic map data represent the approximate mapping of the specific system behavior. During operation the data are directly used or evaluated by interpolation, for example to determine a working point, or, for example, to deduce unknown parameters from known states and parameters. Complex characteristic maps often have multiple dimensions. The data points of the characteristic map are characterized by a predefined quantity of data. The data points are computed offline, i.e., at the time of calibration, and are permanently stored, for example in the flash memory of the microprocessor, upon delivery of the control unit.
The shortcoming of the characteristic map approach is that the number of data points increases disproportionately as the number of dimensions increases. Since these data points consume correspondingly more memory, this approach is not cost-effective. In addition, values between data points must be interpolated. The number and complexity of interpolations increase with an increasing number of dimensions. Reading out the data points from the memory and interpolation are time- and computation-intensive. In particular, access to the characteristic maps which are situated in the flash memory, for example, which is usually not predictable and therefore not bufferable, results in long waiting times for the processor in the range of multiple cycles for each read access. This time is generally not usable in some other way, so that considerable computing power is wasted. In addition, the interpolation and the limited number of data points are accompanied by a loss in accuracy, which in turn is reflected in decreased regulation or control accuracy.
In this regard, the example logic circuit as a hardware accelerator of exponential function computations for a control unit-computing unit allows, for example, use of methods, which heretofore have not been feasible due to limited computing resources, for determining unknown parameters as a function of known (measured and/or computed, for example) parameters for controlling vehicle functions, and allows use of the parameters in real time by a control unit.
As an example of such, nonparametric regression methods such as Bayesian regression are mentioned in one particularly advantageous embodiment. Bayesian regression methods, for example kriging, Gaussian processes, sparse Gaussian processes, etc., may be used on the control unit for predicting, for example, engine-relevant parameters (for example, combustion variables, air feed system variables, etc.) for the control and/or regulation. A portion of the computation of the Bayesian regression methods, in particular computation of exponential functions or computing steps for computing exponential functions, is transferred to the logic circuit.
Compared to the conventional methods, such Bayesian regression models provide more accurate results and may be used in a more flexible manner. Bayesian regression models are able to easily map high-dimensional, nonlinear relationships without prior knowledge and without parameterization, based solely on training data. These are black box models. Simply stated, the best random functions are averaged for determining the needed parameters, from a large number of ascertained random functions based on deviations of certain input variables from training values measured offline before the control unit is used. In this simplified picture, the accuracy of the method corresponds to the deviation of the averaged best functions from one another. Thus, in contrast to the conventional methods, in addition to the model prediction, the Bayesian regression models are also able to provide conclusions concerning model variance (model uncertainty).
In the case of such a use of the microcontroller or the logic circuit, the control unit receives signals from an external control unit, for example from sensors or other control units, computing units, or other modules. In this case these variables are referred to as input variables, and may represent temperature signals, rotational speed signals, quantity signals, etc. Values which have been determined in test measurements for certain variables offline, i.e., before the control unit or the vehicle is operated, and stored in the memory unit, are stored in a memory unit. Here and in the following description, these values are referred to as training values. The terms “offline” or “before operation” specify a phase in which the control unit is not used for real-time regulation and control tasks during normal operation of the vehicle (“online”, “in operation”), but instead, in which vehicle functions which are relevant for the control unit are tested, calibrated, and determined, for example in a calibration of the control unit in the facilities of an automotive supplier or automobile manufacturer, in a repair shop, or in a test operation.
Parameters and variables which have been received or computed by the control unit, and which are likewise included in the input variables, may also be stored in the memory. Independently or in conjunction with the computing unit of the control program, the logic circuit determines one or multiple output variables for meeting the control or regulation functions of the control unit. Output variables refer to variables or intermediate values which are necessary for the control/regulation, are not directly measurable or determinable in the vehicle except with great effort, and which therefore are determined from the available input variables. For this purpose, during operation the control unit carries out a Bayesian regression using the training data stored in the memory which are relevant for the output variable to be determined, taking into account the input variables which are relevant for the output variable to be determined. For this purpose, the computing unit may process the algorithms necessary for carrying out the regression partly in software; however, certain computing steps which involve the computation of exponential functions are transferred to the specialized logic circuit. The determined output variable or a control or regulation signal which is thus determined is output via an output of the control unit to an actuator, for example, or is entered as an intermediate value in further computations.
The fundamentals of Bayesian regression are described in Gaussian Processes for Machine Learning, C. E. Rasmusen and C. Williams, MIT Press, 2006. For the use of such regression methods, the basic formula for computing a certain prediction of a necessary parameter as a function of known parameters in the control unit in real time, i.e., during operation of the control unit, for controlling vehicle functions includes the computation of exponential functions, in particular for the methods which use the so-called squared exponential kernel. Such methods or comparable methods may be used in a particularly efficient manner in motor vehicle control units due to the proposed transfer of certain computing operations with regard to the computation of exponential functions to logic circuit 14. For such nonparametric methods, the following formula, for example, may be mentioned as a particularly relevant example of the exponential functions to be computed or the exponential functions whose computation is to be accelerated, without limiting the present invention to formulas of this type:
The formula is characterized by the exponential function e( ) having an internal term. The internal term normalizes input variables C4 by dividing by C5, and computes the difference from the training values or specific characteristic values by subtracting from C3. The intermediate result is then exponentiated by C6, multiplied by a weighting factor C2, and added to form a sum. The function e( ) is then applied to this sum result (internal term). The result may be weighted by multiplying by C1. Typically, C6=2 and C2=1.
Thus, the exponential function of a sum of N summands is computed, corresponding to the dimension of the input variable. Values C1-C6 as well as the run indices of the summation (starting value of the sum, number of summands, end value of the sum) may be provided to be configurable.
Alternatively, it is possible to configure only a portion of these parameters, and to predefine other parameters.
The exponential function to be computed may be calculated completely in the logic circuit, with or without an internal term, subcomputations may be performed elsewhere, and the exponential function may also be part of a larger formula which the logic circuit computes. Furthermore, the logic circuit may be designed in such a way that, in addition to an exponential function computation, it is able to carry out other computations, which may be performed in parallel with or instead of the exponential function computation. The logic circuit may internally parallelize the execution of the algorithms as desired. Externally, it is necessary only to ensure consistency, or to externally signal inconsistent states using suitable means.
Optionally, the logic circuit may compute more than one of the formulas or tasks simultaneously without influencing the individual results with respect to one another. This may be implemented using parallel arithmetic units, or sequentially on one arithmetic unit. In order to differentiate among the formula instances, the configuration parameters for each of the formulas are known to the hardware accelerator. For this purpose, it is advantageously possible to switch between the configuration sets, i.e., to have separate access to individual configuration sets, and to reuse portions of configuration sets of a formula or task in another formula or task.
Optionally, the logic circuit may be designed to be executed periodically. All or part of the configuration data should be updated by interaction with the software processor, and optionally other involved hardware components, before each execution is restarted.
The present invention may be supplemented by the optional possibility of accumulating multiple computed results, for example by executing an external loop. For this purpose, the hardware accelerator may be configured so that the individual results (i.e., parameters or configuration data) to be accumulated are to be selectively adjusted for the different individual tasks.
As shown in
The communication between processor 11, logic circuit 14, and memories 12 and 13 may take place via common bus 10, as shown in
During run time, logic circuit 14 may be dynamically configured by the processor with regard to:
The configuration data may optionally be contiguously combined as one or multiple clusters in a specified manner. The type of access to each configuration cluster must be known to logic circuit 14. Logic circuit 14 may optionally be configured during run time with respect to location and access to the cluster. It is possible to store the configuration data, for example, only in a local memory 15, only in one of global memory units 12 and 13, or between these memory components in a distributed manner. For example, if configuration data are completely or partially stored in one or multiple global memories 12 and 13, logic circuit 14 is able to access the globally visible memory range, i.e., these global memories, in particular via direct memory access (DMA).
Optionally, for reasons of access optimization, the constants of the formulas or task may be indexed in such a way that, with respect to time, linear or approximately linear access to constants of an array is achieved. The same applies for the execution of multiple formulas, whose configuration data are then ideally stored linearly in succession.
In a departure from the dynamic configurability, it is possible as mentioned to directly specify individual values in the hardware accelerator. It is also possible to permanently or configurably specify alternative values, from which the previously described configuration may be indirectly deduced.
Logic circuit 14 is dynamically configured by the writing of configuration registers or a configuration memory by the remaining system components, in particular using the software which is executed on processor 11.
Optionally, the configuration may be performed using a direct memory access (DMA) controller, which in turn may be controlled by the software of the processor. A configuration by other components of the overall system is also possible.
As described, logic circuit 14 may optionally have a local memory or a local register set from which it obtains the configuration. If logic circuit 14 has such a local memory or a local register set 15, the local memory or local register set should optionally be globally visible, i.e., should be located in the global address range. If necessary, the contents may be modified by further components such as the software processor. In addition to configuration of the hardware accelerator, the procedure also allows use of memory 15 for other uses when memory 15 is not needed, or is not completely needed, by logic circuit 14 for the computation. The logic circuit may have internal optimization measures which convert a precalculation or a preloading of data, or which maintain the results or intermediate results in a buffer or a pipeline. To achieve high flexibility, in each case the logic circuit optionally may have the capabilities of interruptibility, storage of intermediate values, resumption of computations, switching to the computation of the same formula having different configuration parameters, and other optimization measures. Upon interruption, all relevant information should be stored and optionally made readable in order to allow resumption of the computation immediately or at a later point in time. It is acceptable to discard a negligibly small portion of a computation which has already been performed (“negligible” in the sense that the computing time has no influence on the execution in interaction with the other system components).
The starting of the computation by the logic circuit may be initiated by any other system components, in particular by the software processor.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2010 028 259 | Apr 2010 | DE | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4881172 | Miller | Nov 1989 | A |
| 6076030 | Rowe | Jun 2000 | A |
| 6671611 | Peltier | Dec 2003 | B1 |
| 6862514 | Ehara | Mar 2005 | B2 |
| 20030204292 | Wang et al. | Oct 2003 | A1 |
| 20050154519 | Kim | Jul 2005 | A1 |
| 20050252283 | Heap et al. | Nov 2005 | A1 |
| 20080162386 | Rifkin et al. | Jul 2008 | A1 |
| 20110264353 | Atkinson et al. | Oct 2011 | A1 |
| Number | Date | Country |
|---|---|---|
| 102005022247 | May 2006 | DE |
| WO 03050624 | Dec 2002 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20110282517 A1 | Nov 2011 | US |
