Patent Application
20100011172
The present invention relates to microcontroller systems, and in particular, to a microcontroller including arbitration devices for controlling access to storage devices by multiple clients through separate address buses and data buses.
Conventional microcontroller systems employ a single, shared address and data bus that are connected from a processor to all storage devices such as RAMs and registers within a system. Read and write operations share this same bus. As a result, only one address (and request) can be output in a cycle, and only one read or write data transfer can complete in a cycle. Consequently, the shared address and data bus limits system performance.
The present invention is directed to a microcontroller system including at least one processor and at least one storage unit for storing data received from or to be sent to the processor. At least two read clients are provided in the processor for retrieving data from the storage unit, and at least one write client is provided in the processor for writing data in the storage unit. The system further includes a memory device provided in the storage unit for storing data, and an arbitration device provided in the storage unit for enabling access to the memory device by the read and the write client. The read clients each have a dedicated read address line connected to the arbitration device for sending a read address of read data to be retrieved from the memory device, and a shared read data bus connected to the memory device for receiving the read data from the read address.
The present invention uses multiple address and data buses for reading operands and writing results. The read and write operations are performed by multiple arbitration clients each having an address bus, a data bus, and a mechanism for making requests and receiving grants, and an arbiter for determining which arbitration client is granted access to a given memory resource in a particular cycle. Each microcontroller contains two (or more) read arbitration clients and one (or more) write arbitration client. Thus, it is possible to read two (or more) operands and write one or more results in the same cycle.
Turning now to
In the preferred embodiment, the instruction pipeline 18 requires at least an instruction fetch (IF) stage 20 for locating and retrieving the next instructions into the processor 12 for execution, a data fetch (DF) stage 22 for retrieving data from the storage units 14, 16 as specified by the instructions in the IF stage, and an arithmetic logic unit (ALU) stage 24 for performing calculations. The instruction pipeline 18 also includes a write back (WB) stage 26 for writing any results that were computed in the ALU stage to the storage units 14, 16.
The processor 12 also includes a pair of read arbitration (ARB) clients 28, 30 for fetching data from the storage units 14, 16 during reading operations, and a write arbitration (ARB) client 32 for writing data to the storage units during writing operations, as instructed by the write back stage 26 of the instruction pipeline 18. The read ARB clients 28, 30 each have a dedicated read address lines 34, 36, respectively, for enabling the processor 12 to fetch data from the two storage units 14, 16, in parallel, through shared read data bus lines 38 or 40. The write ARB client 32 has a dedicated write address line 41 for carrying the addresses to the memory units 14, 16 in which to store data, and a separate write data bus 43 for carrying data to be stored in the addresses indicated in the write address line.
Thus described arrangement of the microcontroller system 10 enables the two read ARB clients 28, 32 to fetch two operands from two different storage units 14, 16 simultaneously, and the write ARB client 32 to output a single result. While only two read ARB clients 28, 30 and one write ARB client 32 are shown and described, any additional read and write ARB clients may be added to the processor 12, and each would have the same configuration.
The storage unit 14 includes an arbiter 42 and a memory device 44, and the storage unit 16 includes an arbiter 46 and a memory device 48. In the exemplary embodiment, the memory devices 44 and 48 are two port RAMs. However, other storage units such as registers and peripheral interfaces may be used in place of or along with RAMs, depending on the intended use of the microcontroller system 10. Moreover, the two port memory devices 44, 48 may be implemented using a three port RAM that allows two reads and one write simultaneously. This would enable the read ARB clients 28, 30 to fetch two operands from the same one of the storage units 14, 16 simultaneously.
Each of the arbiters 42 and 46 is communicatively connected to the read ARB clients 28, 30, and the write ARB client 32. The arbiters 42, 46 receive read and write requests from these sources, and grants access to the corresponding memory devices 44 or 48. More specifically, the arbiters 42 and 46 each receives read addresses from the read ARB clients 28 and 30 through the read address lines 34, 36. The arbiters 42 and 46 also receive read requests from and grant accesses to the ARB clients 28, 30 through a corresponding read request/grant lines 50, 51. Thus, the read ARB client 28 is connected to both arbiters 42 and 46 via the read address line 34 and two separate read requests/grant lines 50 each going to the corresponding arbiter. Similarly, the read ARB client 30 has the read address line 36 going to both of the arbiters 42 and 46, and two separate read requests/grant lines 51 each going to their respective arbiters.
The write ARB client 32 includes two separate write requests/grant lines 52, each going to the corresponding arbiter 42 or 46, the write address line 41 which is connected to both of the arbiters, and the separate write data line 43 that also goes to both arbiters 42 and 46. The write ARB client 32 is also connected to the instruction pipeline 18, specifically the write back (WB) stage 26 for receiving write instructions from the instruction pipeline via a write line 55, and for receiving data to be written via a dedicated write data line 54. Thus, the arbiters 42 and 46 each receives write requests from and grants accesses to the write ARB client 32 through the dedicated write request/grant line 52, a write address from the write ARB client 32 through the write address line 41, and the write data through the write data line 43.
The memory devices 44, 48 store data used by the processor 12, and receive read and write signals from their respective arbiters 42, 46. The memory devices 44, 48 output data requested by the read ARB clients 28, 30 through the corresponding read data bus 38 and 40, each of which are shared by read ARB clients 28 and 30.
Referring to
When the arbiter 42 or 46 corresponding to the targeted memory device 44 or 48 decides to grant access to the read ARB client 28 or 30 issuing the read request signal, it sends a READ GRANT signal to the read grant indicator 60 in the read ARB client, through the read request/grant line 50 or 51 (see
Upon receiving the READ grant signal from the arbiter 42 or 46 of the targeted memory device 44 or 48, the read grant indicator 60 sends a grant signal to the read controller 56. In response, the read controller 56 outputs a DATA AVAILABLE signal to the data fetch stage 22 of the pipeline 18 indicating that the requested data is available. The data fetch stage 22 of the read ARB client 28 or 30 requesting the read request then receives the data from the read data receiver 62. A data select signal is also output by the read controller 56 to the read data receiver 62 indicating which of the read data received from the memory device 44 or 48 corresponding to the targeted data should be output by the read data receiver.
Referring now to
The write controller 64 receives a WRITE signal indicating that a write process is needed, a WRITE ADDRESS signal providing the destination address of the write data in the memory devices 44 or 48, and data (WRITE DATA) to be written in the target address. The WRITE and WRITE ADDRESS signals are received simultaneously from the write back (WB) stage 26 via the write lines 55, and the WRITE DATA via the write data line 54. The write controller 64 outputs a write request signal to the write request generator 68, which analyzes the target address and sends a WRITE REQUEST signal to the appropriate arbiter 42 or 46 corresponding to the memory devices 44 or 48 where the data will be written. In conjunction with the WRITE REQUEST signal, the write controller 64 also outputs the WRITE ADDRESS on the dedicated write address line 41 and the WRITE DATA on the separate write data bus 43 to the same arbiter 42 or 46.
When the arbiter 42 or 46 corresponding to the targeted memory device 44 or 48 decides to grant access to the write ARB client 32, it sends a WRITE GRANT signal to the write grant indicator 66 in the write ARB client via the write request/grant line 52. The grant indicator 66 then sends a grant signal to the write controller 64, which outputs a WRITE DONE signal to the write back stage 26 of the instruction pipeline 18 indicating that the write process has been completed.
Turning now to
The read access granter 70 receives a READ REQUEST from all the read ARB clients 28, 30 (and any additional read ARB clients in the microcontroller system 10 or other microcontroller systems), and outputs READ GRANT signals indicating to the read ARB client 28 or 30 that an access has been granted. In addition to these outputs, the read access granter 70 further communicates to the read address selector 72, the read ARB client given access to the requested data. Based upon the signal received from the read access granter 70, the read address selector 72 receives the corresponding address from the selected read ARB client 28 or 30, and outputs the selected READ ADDRESS to the memory device 44 or 48.
The read access granter 70 further outputs a read enable signal to the memory device 44 or 48, so that the memory device 44 or 48 outputs the data from the memory location indicated in the selected read address received from the read address selector 72. The data read from that address (memory location) is output by the memory device 44 or 48 to the corresponding read data bus 38 or 40, which carries the data to the read ARB client 28 or 30 requesting the data, specifically, to the data receiver 62 of the read ARB client.
In one embodiment, the read access granter 70 employs a priority encoded method of determining access by the competing read ARB clients, and a single grant is generated in response to the highest priority request. However, other arbitration schemes may be used, such as the round robin or the first-come, first-served methods.
The write access granter 74 receives WRITE REQUEST signals from the write ARB client 32 (or any additional write ARB clients in the microcontroller system 10 or other microcontroller systems) and determines, based upon the type of arbitration scheme used, which of the WRITE REQUEST signals is selected for operation in the targeted memory device 44 or 48. Once the write access granter 74 selects the WRITE REQUEST signal from the write ARB clients, it outputs a select signal to the write address selector 76 and to the write data selector 78. The write address selector 76 allows the WRITE ADDRESS corresponding to the selected write ARB client to be supplied to the memory device 44 or 48. The write data selector 78 selects the WRITE DATA corresponding to the selected write ARB client and sends the selected WRITE DATA to the memory device 44 or 48, where the data is written to the indicated WRITE ADDRESS from the write address selector 76. The write access granter 74 also outputs WRITE GRANT signals that are sent to the grant indicator 66 of the write ARB client 32 via the write request/grant line 52. A write enable signal output from the write access granter 74 enables the target memory device 44 or 48 to store the WRITE DATA received from the write data selector 78 in the WRITE ADDRESS indicated by the write address selector 76.
The write access granter 74 and the read access granter 70 are implemented in hardwired logic, and the read address selector 72, the write address selector 76 and the write data selector 78 are implemented using multiplexers.
In operation, if the two read ARB clients 28 and 30 within the processor 12 target different memory devices 44 and 48, data for both read ARB clients can return in the same cycle. However, if the same memory device 44 or 48 is targeted, the data must be returned serially from the targeted memory device to the read ARB clients 28 and 30. In this case, each of the read ARB clients 28 and 30 makes its request to the appropriate arbiter 42 or 46, and the arbiter determines which read ARB client is granted access first.
It should also be appreciated that the order data is fetched is not predetermined. This prevents stalled data fetches from delaying data fetches that would otherwise not stall. For example, when one memory device 44 or 48 is able to provide a grant immediately but the other cannot, one read will complete even if it is the “second” data requested.
While various embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.
Various features of the invention are set forth in the appended claims.
