The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiment as set forth below. The Description of the Preferred Embodiment is understood within the context of the accompanying drawings, that form a material part of this disclosure, wherein:
The invention, which comprises a microelectronic structure (i.e., generally a semiconductor structure) that in turn comprises a resistor structure, is understood within the context of the description provided below. The description is understood within the context of the accompanying drawings, as described above. The drawings are intended for illustrative purposes, and as such the drawings are not necessarily drawn to scale.
The semiconductor substrate 10 and remaining structures designated above may comprise materials and have dimensions that are conventional in the semiconductor fabrication art. The semiconductor substrate 10 and remaining structures designated above may also be formed using methods that are conventional in the semiconductor fabrication art.
The semiconductor substrate 10 comprises a semiconductor material. Non-limiting examples of semiconductor materials include silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy and compound semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide semiconductor materials.
The semiconductor substrate 10 may comprise a bulk semiconductor material as is generally illustrated within the schematic cross-sectional diagram of
The isolation regions 12 comprise isolation materials that are typically dielectric isolation materials. The dielectric isolation materials may comprise any of several dielectric materials. Non-limiting examples of dielectric materials include oxides, nitrides and oxynitrides of silicon. Oxides, nitrides and oxynitrides of other elements are not excluded. Also contemplated are laminates and composites of the foregoing dielectric isolation materials. Similarly, the dielectric isolation materials may also be a crystalline material or a non-crystalline material. The isolation regions 12 may be formed using any of several methods. Non-limiting examples include thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods (including atomic layer chemical vapor deposition methods) and physical vapor deposition methods (including sputtering methods). Typically, the isolation regions 12 comprise at least in part a silicon oxide dielectric material that has a thickness (i.e., trench depth) from about 2000 to about 6000 angstroms.
The transistors T comprise gate dielectrics 14. Gate electrodes 16 are located upon gate dielectrics 14. Spacer layers 15 adjoin sidewalls of gate electrodes 16. Source/drain regions 17 are located within the semiconductor substrate 10 and separated by channel regions located beneath the gate electrodes 16.
Each of the foregoing structures that comprise the transistors T may comprise materials and have dimensions that are conventional in the semiconductor fabrication art. Each of the foregoing structures that comprise the transistors T may be formed using methods that are conventional in the semiconductor fabrication art.
Gate dielectrics 14 may comprise generally conventional gate dielectric materials having a dielectric constant from about 4 to about 20, measured in vacuum. Non-limiting examples of these gate dielectric materials include silicon oxide, silicon nitride and silicon oxynitride gate dielectric materials. The gate dielectrics 14 may also comprise generally higher dielectric constant gate dielectric materials having a dielectric constant from about 20 to at least about 100, also measured in vacuum. Non-limiting examples of these gate dielectric materials include hafnium oxides, haffiium silicates, titanium oxides, lanthanum oxides, barium-strontium titanates (BSTs) and lead-zirconate titanates (PZTs). The gate dielectrics 14 may be formed using methods that are conventional in the semiconductor fabrication art. Non limiting examples include thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. Typically, the gate dielectrics 14 comprise a thermal silicon oxide gate dielectric material that has a thickness from about 15 to about 50 angstroms.
The gate electrodes 16 may similarly comprise gate electrode materials that are conventional in the semiconductor fabrication art. Included, but not limiting, are certain metals, metal alloys, metal nitrides and metal silicides. Also included, but not limiting, are doped polysilicon and polycide gate electrode materials. The gate electrode materials may be deposited using methods that are appropriate to their material of composition. Non-limiting examples include plating methods, chemical vapor deposition methods and physical vapor deposition sputtering methods. Typically, the gate electrodes 16 comprise a metal gate material, a polycide gate material or a polysilicon gate material that has a thickness from about 2000 to about 5000 angstroms.
The spacer layers 15 (which are illustrated as plural layers in cross-section but are actually single layers that completely surround gate electrodes 16 in plan view) typically comprise dielectric spacer materials, although conductor spacer materials are also known. Dielectric spacer materials may comprise the same materials as the isolation regions 12. Conductor spacer materials may use the same materials as the gate electrodes 16. Typically, the spacers 15 comprise at least in part a dielectric spacer material. The spacers 15 are formed using a blanket layer deposition and anisotropic etchback method that is otherwise generally conventional in the semiconductor fabrication art.
The source/drain regions 17 comprise a dopant of polarity appropriate for a polarity of a transistor T desired to be formed. Typically, the source/drain regions 17 are formed using a two step ion implantation process. A first step within the two step ion implantation process uses the gate 16 as a mask absent the spacers 15 to form extension regions into the semiconductor substrate 10. A second step within the two step ion implantation process uses the gate electrode 16 and spacers 15 as a mask to form contact region portions of the source/drain regions 17 that incorporate the extension regions. Typically, the extension regions have a dopant concentrations from about 1e15 to about 1e16 dopant atoms per cubic centimeter and the contact regions have a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter.
Capping layer 18 typically comprises a dielectric capping material. Dielectric capping materials may be selected from the same group of materials as the isolation regions 12. The dielectric capping materials may also be deposited using the same methods as disclosed above for the isolation regions 12. Typically, the capping layer 18 has a thickness from about 200 to about 700 angstroms.
The resistor 20 comprises a resistive material, but the resistor 20 is not necessarily intended as a resistor in accordance with the invention. Typically the resistor 20 is a generally lower resistance resistor that may comprise a generally conventional resistive material, such as a polysilicon resistive material. Typically, the resistor 20 has a thickness from about 200 to about 2000 angstroms.
To obtain the semiconductor structure that is illustrated within the schematic cross-sectional diagram of
Subsequent to patterning the passivation layer 22 to yield the passivation layer 22′, the contact studs 24 are then located and formed into the contact vias. The contact studs 24 may comprise any of several conductor materials. Included, but not limiting, are metals, metal alloys, doped polysilicon and polycide contact stud materials. Particular metals include tungsten, copper and aluminum metals, but the foregoing selections do not limit the invention. Tungsten metal is particularly common as a contact stud material. The contact studs 24 may be formed using methods that are conventional in the semiconductor fabrication art. Included, but not limiting, are plating methods, chemical vapor deposition methods and physical vapor deposition methods.
Within the instant embodiment, dimensions of the dual damascene apertures 33 (and the resulting stud/interconnect layers 34) are selected such that advantages of a Blech effect (i.e., a short length effect for electromigration inhibition) can be utilized when an electrical current passes through the stud/interconnect layers 34 and subsequently the resistor 30. A Blech effect is defined within the context of a Blech constant C for a particular conductor material (i.e., the Blech constant is a conductor material specific constant below which electromigration does not occur). To utilize a Blech constant C within the context of electromigration inhibition considerations, one determines the product of J×L, where J equals a current density through a conductor material of interest and L equals an interconnect length of the conductor material of interest. When the product of J×L exceeds the Blech constant C for the material of interest, electromigration of the conductor material occurs. For copper, a Blech constant C is typically about 300 mA/um. Blech constants will vary with material properties (both conductor itself and the surrounding insulator).
Thus, within the context of the instant embodiment, in order to take advantage of Blech effect for the stud/interconnect layers 34 (i.e., an electromigration effect), a stud length L within the stud/interconnect layer 34 as illustrated in
Also, within the instant embodiment the heat sink layer 34′ is intended to alleviate overheating of the resistor 30 and thus provide a uniform and lower temperature profile of the resistor 30. Typically, the uniform and lower temperature profile assists in providing a stable resistance for the resistor 30. The uniform and lower temperature profile also assists in providing higher current carrying capacity for the stud/interconnect layers 34. For example, for stud/interconnect layers 34 comprising copper, a maximum normalized current density of the stud/interconnect layers decreases by about a factor of 4 for a temperature increase from about 90° C. to about 110° C.
The passivation layer 36′ may comprise materials, have dimensions and be formed using methods analogous, equivalent or identical to the materials, dimensions and methods used within the context of the underlying passivation layers 32′, 26′ and 22′. Similarly, the stud/interconnect layers 38 may also comprise materials, have dimensions and be formed using methods analogous, equivalent or identical to the materials, dimensions and methods used within the context of the stud/interconnect layers 34.
The passivation layer 40′ may comprise materials, have dimensions and be formed using methods analogous, equivalent or identical to the materials, dimensions and methods used within the context of the underlying passivation layers 36′, 32′, 26′ and 22′. Similarly, the stud/interconnect layers 42 may also comprise materials, have dimensions and be formed using methods analogous, equivalent or identical to the materials, dimensions and methods used within the context of the stud/interconnect layers 38 and 34.
The passivation layer 44′ may comprise materials, have dimensions and be formed using methods analogous, equivalent or identical to the materials, dimension and methods used within the context of the underlying passivation layers 40′, 36′, 32′, 26′ and 22′. Similarly, the stud/interconnect layers 46 may also comprise materials, have dimensions and be formed using methods analogous, equivalent or identical to the materials, dimensions and methods used within the context of the stud/interconnect layers 42, 38 and 34.
Within the context of the instant embodiment, and similarly with the stud/interconnect layers 34, each of the stud/interconnect layers 38, 42 and 46 is designed in size so that a Blech effect (i.e., an electromigration effect) within the stud interconnect layers 46, 42 and 38 may be avoided when power is supplied to the resistor 30. In addition, within the context of the instant embodiment, the stud/interconnect layers 46, 42, 38 and 34 are aligned vertically so that current flow is in a vertical only, until upper wiring levels (which are generally larger and have a linewidth from about 0.3 to about 1 microns), are reached. This vertical alignment of the stud/interconnect layers 46, 42, 38 and 34 also provides for enhanced heat dissipation from the resistor 30.
The embodiment also illustrates a heat sink layer 34′ located contacting the high current density resistor 30. The heat sink layer 34′ also assists in providing heat dissipation within the high current density resistor 30.
The preferred embodiments of the invention are illustrative of the invention rather than limiting of the invention. Revisions and modifications may be made to methods, materials, structures and dimensions of a microelectronic structure in accordance with the preferred embodiments of the invention, while still providing a microelectronic structure in accordance with the invention, further in accordance with the accompanying claims.