Claims
- 1. A method of protecting a first active area in a first surface of a first chip comprising:aligning a first bond pad on a first surface of a second chip with a first trace on said first surface of said first chip; physically connecting said first bond pad to said first trace, wherein said first active area is a micromachine area comprising a miniature moveable structure; and forming a bead around a periphery of said second chip, wherein said first chip, said second chip, and said bead form an enclosure which defines a cavity, said first active area being located within said cavity.
- 2. The method of claim 1 wherein said physically connecting comprises:forming a flip chip bump on said first bond pad; and reflowing said flip chip bump.
- 3. The method of claim 1 wherein said physically connecting comprises:forming a flip chip bump on said first trace; and reflowing said flip chip bump.
- 4. The method of claim 1 wherein said first bond pad is physically connected to said first trace by a flip chip bump.
- 5. The method of claim 4 wherein said flip chip bump is formed of a material selected from the group consisting of solder, gold, electrically conductive epoxy paste and electrically conductive epoxy film.
- 6. The method of claim 1 wherein said physically connecting comprises directly connecting said first bond pad to said first trace.
- 7. The method of claim 6 wherein said directly connecting comprises thermo-compression bonding said first bond pad to said first trace.
- 8. The method of claim 1 wherein said forming a bead comprises:dispensing a limited flow material around said second chip, wherein said limited flow material is drawn slightly between said first chip and said second chip; and curing said limited flow material.
- 9. The method of claim 8 wherein said limited flow material comprises a liquid encapsulant.
- 10. The method of claim 1 wherein said second chip comprises a second active area in said first surface of said second chip, said second active area being located within said cavity.
- 11. The method of claim 1 wherein said first chip is a micromachine chip.
- 12. The method of claim 11 wherein said second chip is a controller chip.
- 13. The method of claim 1 further comprising electrically connecting said first trace to a first lead.
- 14. The method of claim 1 further comprising forming a bond wire between said first trace and a first lead.
- 15. The method of claim 12 wherein said controller chip is a controller for said micromachine chip.
- 16. The method of claim 1 wherein said first trace extends from said first active area to a periphery of said first surface of said first chip adjacent bond pads of said first chip.
- 17. A method of forming a package comprising a first chip and a second chip, said method comprising:aligning a first bond pad on a first surface of said second chip with a first trace on a first surface of said first chip, a first active area being in said first surface of said second chip, wherein said first active area is a micromachine area comprising a miniature moveable structure; physically connecting said first bond pad to said first trace; and forming a bead around a periphery of said second chip, wherein said first chip, said second chip, and said bead form an enclosure which defines a cavity, said first active area being located within said cavity.
- 18. A method of forming a package comprising a first micromachine chip and a second micromachine chip comprising:aligning a first bond pad on a first surface of said second micromachine chip with a first trace on a first surface of said first micromachine chip, said first trace extending from a first micromachine area of said first micromachine chip to a periphery of said first surface of said first micromachine chip adjacent bond pads of said first micromachine chip; physically connecting said first bond pad to said first trace; and forming a bead around a periphery of said second micromachine chip to form an enclosure which defines a cavity, said first micromachine area of said first micromachine chip and a second micromachine area of said second micromachine chip being located within said cavity.
Parent Case Info
This application is related to Glenn et al., commonly assigned and co-filed U.S. patent application Ser. No. 09/640,499, entitled “MICROMACHINE STACKED WIREBONDED PACKAGE”; Glenn et al., commonly assigned and co-filed U.S. patent application Ser. No. 09/670,500, “MICROMACHINE STACKED WIREBONDED PACKAGE FABRICATION METHOD”; Glenn et al., commonly assigned and co-filed U.S. patent application Ser. No. 09/670,498, entitled “MICROMACHINE STACKED FLIP CHIP PACKAGE”, which are all herein incorporated by reference in their entirety.
US Referenced Citations (15)