This application claims the benefit of U.S. Provisional application Ser. No. 60/034,131, filed Dec. 31, 1996.
Number | Name | Date | Kind |
---|---|---|---|
5357618 | Mirza et al. | Oct 1994 | |
5434985 | Emma et al. | Jul 1995 | |
5442760 | Rustad et al. | Aug 1995 | |
5694568 | Harrison, III et al. | Dec 1997 | |
5752037 | Gornish et al. | May 1998 | |
5761706 | Kessler et al. | Jun 1998 | |
5778435 | Berenbaum et al. | Jul 1998 | |
5834921 | Pickett | Dec 1998 |
Entry |
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Reducing Memory Latency via Non-blocking and Prefetching Caches, Tien-Fu Chen, et al, University of Washington, Seattle, WA 98105. |
Hardware Support for Hiding Cache Latency, Michael Golden, et al., University of Michigan Technical Report, An Arbor, MI 48109-2122. |
Stride Directed Prefetching in Scalar Processors, John W. C. Fu, et al. Intel Corp., 1900 Praire City Rd. Folsom, CA 95630. |