Patent Application
20250174863
The present invention generally relates to microstrip phase inverters in microwave circuit designs, which are used in high-power devices.
The microstrip phase inverter provides a 180° phase shift by reversing both the signal and the ground line. Various types of phase inverters, integrated into structures such as microstrips, coplanar waveguides, asymmetrical coplanar strips, and parallel strip lines (PSL), have played a pivotal role in reducing the size of microwave components, including rat-race hybrids, filters, and power dividers.
Despite their versatility, current phase inverters face limitations in high-power applications in which significant heat is generated by the high-power amplifiers. Traditionally, the underside of a microwave component requires a large metal ground plane for mounting on the heat sink alongside the high-power amplifier. When the circuit is fabricated in monolithic microwave integrated circuit (MMIC), the underside of the die is also the metal ground plane. However, in conventional microstrip phase inverter designs, there are often circuit portions on the bottom side, especially in the transition from the microstrip line to other transmission line structures. This configuration presents challenges when grounded on the heat sink, notably impacting the S-parameters.
Therefore, there is a pressing need for a microstrip phase inverter specifically tailored to address the limitations and challenges posed by high-power applications.
It is an objective of the present invention to provide an apparatus and a circuit design to address the aforementioned shortcomings and unmet needs in the state of the art.
In accordance with one aspect of the present invention, provided is a microstrip phase inverter that includes a bottom layer, a first dielectric layer, an insert conductor (IC) layer, a second dielectric layer, a top layer, at least one first via, and a pair of second vias. The first dielectric layer is disposed over the bottom layer. The IC layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the IC layer. The top layer is disposed over the second dielectric layer and includes a first strip line and a second strip line which extend along a first direction and across at least one edge of the IC layer and are narrower than the IC layer along a second direction different than the first direction. The first via electrically connects the bottom layer to the IC layer. The second vias electrically connect the IC layer to the first strip line and the second strip line, respectively.
In accordance with another aspect of the present invention, provided is an microstrip phase inverter that includes a bottom layer, an insert conductor (IC) layer, and a top layer. The bottom layer has a top border and a bottom border opposite the top border which extend along a first direction. The IC layer is located between the top and bottom borders of the bottom layer in viewing along a normal direction of the bottom layer, in which the IC layer has a top border and a bottom border opposite the top border which extend along the first direction and a left border and a right border opposite the left border which extend along a second direction different than the first direction. The top layer is located between the top and bottom borders of the IC layer and has a first strip line pattern and a second strip line pattern which are separated than each other. The first strip line pattern extends along the first direction and across the left border of the IC layer, and the second strip line pattern extends along the first direction and across the right border of the IC layer, such that the first strip line pattern and the second strip line pattern span from inside to outside of the IC layer.
By the above configuration, the microstrip phase inverter of the present invention can achieve certain amount of size reduction, preventing subsequent component integration stages from becoming excessively large; and the microstrip phase inverter of the present invention features a complete ground plane without any circuit on the bottom side so it is easy to connect with other microstrip components by placing on heat sink in high-power application and integrated in MMIC. As such, the microstrip phase inverter of the present invention presents a topology that is available to be incorporated into monolithic microwave integrated circuits (MMICs).
Embodiments of the invention are described in more details hereinafter with reference to the drawings, in which:
In the following description, microstrip phase inverters and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
Referring to
The bottom layer 110 can serve as a ground plane for the microstrip phase inverter 100. In an embodiment, the bottom layer 110 is conductive, such as a metal layer or an alloy layer.
The first dielectric layer 120 is disposed over the bottom layer 110. In an embodiment, the first dielectric layer 120 includes at least one dielectric material with a dielectric constant in a range from 4 to 4.5, such as silicon oxide, oxides, silicon nitride, nitrides, or combinations thereof. In an embodiment, the first dielectric layer 120 is a multi-layered structure, such as a composite dielectric layer. It is noted that the dielectric constant is not limited but flexible; in an embodiment, the dielectric constant is in a range from 2 to 10.
The IC layer 130 is disposed over the first dielectric layer 120. In an embodiment, the IC layer 130 is a conductive layer, such as a metal layer or an alloy layer. In the top viewing as
The second dielectric layer 140 is disposed over the IC layer 130 and is thinner than the first dielectric layer 120. In an embodiment, the second dielectric layer 140 includes at least one dielectric material with a dielectric constant in a range from 4 to 4.5, such as silicon oxide, oxides, silicon nitride, nitrides, or combinations thereof. In an embodiment, the second dielectric layer 140 is a multi-layered structure, such as a composite dielectric layer. It is noted that the dielectric constant is not limited but flexible; in an embodiment, the dielectric constant is in a range from 2 to 10.
The top layer is disposed over the second dielectric layer 150 and includes a first strip line 152 and a second strip line 154 which are spaced apart and extend along the first direction D1. In an embodiment, for forming the phase inverter, the IC layer 130 is about 0.2 mm below the top layer 150. More specifically, for example, the IC layer 130 is at a first height H1 with respect to the bottom layer 110, and the top layer 150 is at a second height H2 with respect to the bottom layer 110, in which a difference between the first height H1 and the second height H2 is between 0.1 mm and 0.3 mm.
The relationship, such as position, location, profile, between the IC layer 130 and the top layer 150, which serves as features for the layout thereof, is relative to the operation performance for the microstrip phase inverter 100; that is, those features can define the operation frequency and the S-parameter for the desired purpose.
The first strip line 152 and the second strip line 154 can extend across opposite edges of the IC layer 130 and are narrower than the IC layer 130 along the second direction. More specifically, the first strip line 152 spans across the first rectangle portion 132, extending from a position directly above the neck portion 136 to a position without vertical overlap with the first rectangle portion 132. The first strip line 152 can span across two opposite sides of the first rectangle portion 132. Similarly, the second strip line 154 spans across the second rectangle portion 134, extending from a position directly above the neck portion 136 to a position without vertical overlap with the second rectangle portion 134. The second strip line 154 can span across two opposite sides of the second rectangle portion 134. As such, a vertical projection of the first strip line 152 on the IC layer 130 overlaps with the first rectangle portion 132 and the neck portion 136 (e.g., the second pattern FP2 of the neck portion 136), and a vertical projection of the second strip line 154 on the IC layer 130 overlaps with the second rectangle portion 134 and the neck portion 136 (e.g., the first pattern FP1 of the neck portion 136). The first strip line 152 and the second strip line 154 are spaced apart from each other by a gap directly and vertically located above the neck portion 136 of the IC layer 130. The first strip line 152 is free from vertically overlapping with the second rectangle portion 134, and the second strip line 154 is free from vertically overlapping with the first rectangle portion 132. In one embodiment, the first strip line 152 has an end portion with a length along the second direction that is substantially equal to a length of the second pattern FP2 of the neck portion 136 along the second direction. In one embodiment, the second strip line 154 has an end portion with a length along the second direction that is substantially equal to a length of the first pattern FP1 of the neck portion 136 along the second direction.
The first via 160 electrically connects the bottom layer 110 to the IC layer 130. The second vias 170 electrically connect the IC layer 130 to the first strip line 152 and the second strip line 154, respectively. Specifically, one of the second vias 170 landing on the first pattern FP1 of the neck portion 136 can electrically connect the first pattern FP1 of the neck portion 136 to the first rectangle portion 132; and another one of the second vias 170 landing on the second pattern FP2 of the neck portion 136 can electrically connect the second pattern FP2 of the neck portion 136 to the second rectangle portion 132. In an embodiment, the formed microstrip phase inverter 100 has a thickness from the bottom layer 110 to the top layer 150 in a range from 1.1 mm to 1.3 mm, which is suitable for integration into a circuit design without affecting circuit size. It should be noted that the thickness is not rigidly constrained but rather flexible; it can vary to accommodate other dimension.
In the top viewing for layout design as
Simulation and experimental results are conducted as example as follows to prove the structure of the present invention that is workable. As the parameters for W and L, with a width (W) of 8 mm and different lengths (L) of 8, 10, and 11.5 mm, frequencies ranging from 0.5 GHz to 3.5 GHz are applied to the simulation. Referring to simulated results for the microstrip phase inverter in
In an embodiment, the microstrip phase inverter of the present invention can be implemented in offset lines at the input of the peaking amplifier and output of carrier amplifier, as shown in
In this regard, the DPAs take the mainstream architecture of a mobile PA/base station PA because of the cancelling even-order harmonic terms that can improve the efficiency. Apart from cancelling even-order harmonic terms in DPAs, the common emitter of transistors used eliminates the inductance from the emitter to the backside vias, which contributes significantly to power loss at high frequencies. This improves both the gain and efficiency of the DPA, which is important to the lack of gain at high frequencies in the transmitter. Therefore, the differential input divider and output combiner are important to the DPA design. The microstrip phase inverter of the present invention can be implemented in the divider and combiner to reduce their circuit size; however, those existed phase invertors cannot achieve as such since there may be a circuit such as transition of transmission lines therein.
The microstrip phase inverter 100 can be fabricated with two ports (e.g., port 1 and port 2), as shown in
Phase inverters play a crucial role in reducing the size of microwave components. However, as the issues as afore-described, some phase inverters face limitations in high-power applications. The microstrip phase inverter of the present invention addresses these limitations and offers two significant advantages for high-power applications.
(1) The microstrip phase inverter of the present invention achieves size reduction, preventing subsequent component integration stages from becoming excessively large.
(2) The microstrip phase inverter of the present invention features a complete ground plane without any circuit on the bottom side, making it a pure microstrip structure. This design facilitates easy connection with other microstrip components and allows for placement on a heat sink in high-power applications, distinguishing it from other phase inverters that have circuits on their bottom sides.
The microstrip phase inverter of the present invention can be applied to passive components for size reduction and use in high-power applications and MMICs. For example, it is applicable to integrate the microstrip phase inverter into high-power power amplifiers.
Another example for the microstrip phase inverter is provided with accompanying
In the present disclosure, spatial descriptions, such as “above,” “on,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, to orient the component(s) as shown in the associated figure. The spatial descriptions used herein are for illustrative purposes only, and practical implementations of the structures described herein can be spatially arranged in any orientation or manner.
As used herein and not otherwise defined, the terms “substantially,” “substantial,” “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to +10% of that numerical value.
The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.
The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.
