Patent Application
20080100394
1. Field of the Invention
This invention relates generally to micro-machined transitions for vertically integrated RF systems on chip and, more particularly, to micro-machined microstrip-to-coplanar waveguide transitions for vertically integrated RF systems on chip.
2. Discussion of the Related Art
Micro-electromechanical switches (MEMS) used for RF applications is a technology area that has potential for providing a major impact on existing RF architectures in sensors and communications devices by reducing the weight, cost, size and power dissipation in these devices, possibly by a few orders of magnitude. Key devices for existing RF architectures include switches in radar systems and filters in communications systems. However, while MEMS technology has demonstrated the potential to revolutionize such devices, MEMS devices have not been specifically designed for performance in harsh environments, typically required for military applications, such as unmanned aerial vehicles (UAV) and national missile defense (NMD) systems. Particularly, MEMS technology requires further development in order to be able to provide effective performance under large temperature variations, strong vibrations and other extreme environmental conditions.
An appropriate packaging scheme that combines the properties of traditional high-speed packages and compatibility with planar technology offers a solution to this issue. Packaging is one of the most critical parts of the RF and MEMS fabrication process. Packaging is the most expensive step in the production line and will ultimately determine the performance and longevity of the device.
A large number of publications exist relating to RF MEMS based circuits, including phase shifters, single-pole multiple-through circuits, tunable filters, matching networks, etc. Many of these circuits have been designed based on a microstrip line configuration. Therefore, in order to develop a compatible on-wafer packaging scheme, a microstrip-to-microstrip transition needs to be provided. Such a transition for a MEMS is disclosed in U.S. Pat. No. 6,696,645 describing a coplanar waveguide (CPW)-to-CPW transition. The transition needs to be as broadband as possible, with minimum insertion losses and no parasitic resonance up to 50 GHz.
It is an important design consideration for a broadband microstrip-to-microstrip transition to maintain a characteristic impedance of the transition at 50Ω, especially at high frequency (>5 GHz). The 50Ω characteristic impedance through the transition is necessary to minimize signal reflections that would otherwise provide signal loss and degrade device performance. The design problem occurs because of the need for a wider microstrip line, which provides a lower impedance, in order to accommodate for the anisotropic etching of the vias through a semiconductor silicon wafer. When silicon is etched in potassium hydroxide or tetramethyl ammonia hydroxide, the etch rate of the <100> crystal plane is much higher than the etch rate of the <111> plane. This means that the final etched structure has a pyramidal shape found in the <111> planes of the silicon crystal. The angle between the <111> and the <100> planes is 54.74°. Other semiconductor wafer materials, such as GaAs, InP, GaN, etc., have similar anisotropic etching profiles. Therefore, in order to get a 20×20 μm square at the bottom of the via, a 160×160 μm square at the top of the via is required. This means that the width of the microstrip line needs to be at least 200 μm at the top of the via to accommodate for the size of the top of the vias. The wider microstrip line has a decreased characteristic impedance (approximately 25-30Ω). This mismatch increases the return loss of a back-to-back transition, thus reducing the overall bandwidth of the structure.
A signal via 20 is formed through the top semiconductor wafer and is in electrical contact with the microstrip lines 12 and 14. Two ground vias 22 and 24 are formed through the bottom semiconductor wafer and provide an electrical contact between the upper ground plane 16 and the lower ground plane 18. The vias 20, 22 and 24 have a “pyrmidical shape” from top to bottom because of the anisotropic etch rates through the crystal planes of silicon when the opening for the vias 20, 22 and 24 are formed, as discussed above. The microstrip lines 12 and 14 and the vias 20, 22 and 24 would be made of a suitable metal, as would be well understood to those skilled in the art.
Typically, the thickness of the semiconductor wafers is about 100 μm because this is the minimum wafer thickness for current wafer fabrication processes. It is desirable that the semiconductor wafers be as thin as possible so that the parasitic inductances generated by the vias 20, 22 and 24 is as minimal as possible. When the openings for the vias 20, 22 and 24 are etched for a wafer of this thickness, the timing of the etch produces about a 160×160 μm metallized square at the top end of the vias 20, 22 and 24 so that the etch produces about a 20×20 μm square at the bottom end of the vias 20, 22 and 24. The size of the top end of the vias 20, 22 and 24 ensures that the openings for the vias 20, 22 and 24 will be formed all the way through the thickness of the wafer.
The width of the microstrip line 12 is about 80 μm to provide the desired 50Ω. However, a widened portion 26 of the microstrip line 20 that makes electrical contact with the top end of the via 20 is wider than the metallized square at the top of the via 20 to provide a suitable electrical contact and the proper orientation and alignment. For the dimensions being discussed herein, the width of the widened portion 26 would be between 200 and 220 μm. Because the wider portion 26 is wider than the rest of the microstrip line 12, it has a different characteristic impedance, typically 25-30Ω. A tapered transition 28 between the widened portion 26 and the rest of the microstrip line 12 minimizes reflections provided by the change in the characteristic impedance, but does not eliminate them. Thus, significant signal loss occurs at the transition between the microstrip line 12 and the via 20, especially at high frequencies. The microstrip line 14 includes the same size transition to a widened portion 46 at the bottom end of the via 20 so as to maintain the 25-30Ω characteristic impedance.
In accordance with the teachings of the present invention, micro-machined microstrip-to-CPW transitions for vertically integrated RF systems on chip are disclosed. In one embodiment, a microstrip line is formed on one surface of a semiconductor wafer and a coplanar waveguide is formed on an opposite surface of the wafer, where the microstrip line and the coplanar waveguide are electrically coupled by vias extending through the wafer. In another embodiment, a semiconductor device is provided that includes a first wafer and a second wafer. The first wafer includes a microstrip line formed on one side that is electrically coupled to a coplanar waveguide formed on an opposite side of the first wafer. The second wafer includes a coplanar waveguide that is electrically coupled to the coplanar waveguide on the first wafer by electrical bumps.
Additional features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.
FIGS. 6(a) and 6(b) are a top view and bottom view, respectively, of a wafer showing a microstrip-to-CPW transition, according to another embodiment of the present invention; and
The following discussion of the embodiments of the invention directed to micromachined microstrip-to-CPW transitions for vertically integrated RF systems on chip is merely exemplary in nature and is in no way intended to limit the invention or its applications or uses.
The following discussion of the embodiments of the invention includes various signal lines, ground planes and semiconductor wafers. The various signal lines and ground planes are metallized layers formed on the substrate, and can be deposited and patterned by any suitable process known to those skilled in the art. Further, the various signal lines and ground planes can have any suitable thickness and be made of any suitable electrical material, such as copper and gold. Further, the various substrates and wafers can be any suitable substrate or wafer for the purposes described herein, including silicon and group III-V semiconductor materials.
The combination of the waveguide portions 40 and 48 of the ground plane 38, the widened portion 34 of the microstrip line 32 and the slots 44 and 52 define a short CPW that has a certain characteristic impedance. The narrow portion of the microstrip line 32 has a characteristic impedance defined by the width of the microstrip line 32. The characteristic impedance of the CPW is defined by the width of the widened portion 34 and the width of the slots 44 and 52. The width of the widened portion 34 is defined by the diameter of the top end of the signal via 36, and the width of the slots 44 and 52 are selected so that the CPW has a characteristic impedance that matches the characteristic impedance of the narrow part of the microstrip line 32 for the width of the widened portion 34.
The CPW is wide enough to accommodate the anisotropic etching of the vias 36, 42 and 50. By utilizing this approach, the RF signal sees the minimum mismatch, and therefore the return loss can be kept below −10 dB for a wider bandwidth of operation.
After the via holes are etched, the coplanar waveguide ground planes are connected forming the microstrip ground plane, while the signal line transitions at the backside of the semiconductor wafer. This design can also be used for a microstrip line-to-coplanar waveguide transition because for some integrated RF circuits it is preferable to use a different type of interconnect on the inside and outside of the package.
The circuit 60 further includes a first CPW 80 defined by the widened portion 64 of the microstrip transition line 62 and two extended portions 82 and 84 of the ground plane 70, and the slots therebetween. Likewise, the transition circuit 60 includes a second CPW 90 defined by the widened portion 68, two extended portions 92 and 94 of the ground plane 72, and the slots therebetween. The CPW 80 and the CPW 90 have an effective characteristic impedance that matches the characteristic impedance of the narrow portion of the microstrip lines 62 and 66. Therefore, signals propagating on the microstrip lines 62 and 66 and through the wafer have a minimal return loss. In one embodiment, the characteristic impedance is 50Ω.
One advantage of the design of the present invention is that in the case of an on-wafer packaging architecture, the ground plane of the microstrip can be used for forming a sealing ring. This means that the ring will always be connected to the RF line, and therefore the parasitic resonance due to its length will be reduced or even eliminated. Moreover, because most of the developed RF MEMS are suspended over microstrip lines, this proposed packaging architecture can be of great interest in the industry. In order to illustrate such a configuration, a MEMS 132 is shown formed to the bottom surface of the wafer 106 and electrically coupled to the microstrip line 118.
Silicon micro-machining is being developed in the art for creating miniaturized multi-chip packaged modules. Mature bulk and surface micro-machining processes allow the fabrication of complex three-dimensional structures, which can replace traditional RF transceiver front-end components. Miniaturized cavity filters, including both resonant and evanescent mode filters, three-dimensional interconnects, RF MEMS and wafer-scale packaging architectures can be monolithically integrated on a single chip creating a multi-functional, tunable system. However, low-loss, manufacturable RF vertical transitions are critical components for a successful three-dimensional circuit integration. While most RF transitions reported in the literature are planar, a small number of architectures have been demonstrated that have the potential to allow successful three-dimensional integration. Integration of three-dimensional RF transitions onto a group III-V semiconductor or silicon substrate using an industry-manufacturable process is one step toward manufacturable, multi-layer integration of packaged active and passive components including FETs and RF MEMS.
A first input ground plane 260 and a second input ground plane 262 are formed on the top surface 244 of the wafer 240 on opposite sides of the extended portion 252, as shown. A ground via 264 extending through the wafer 240 is electrically coupled to the ground plane 260 and a ground via 266 extending through the wafer 240 is electrically coupled to the ground plane 262. Likewise, a first output ground plane 268 and a second output ground plane 270 are formed on the top surface 244 of the wafer 240 on opposite sides of the extended portion 256 of the microstrip line 250, as shown. A ground via 272 extending through the wafer 240 is electrically coupled to the ground plane 268 and a ground via 274 extending through the wafer 240 is electrically coupled to the ground plane 270.
An input CPW 280 and an output 282 are formed on the bottom surface 246 of the wafer 240. The input CPW 280 and the output CPW 282 include a common signal line 284, where the signal line 284 includes a widened portion 286 that forms part of the input CPW 280 and a widened portion 288 that forms part of the output CPW 282. The widened portion 286 is electrically coupled to the signal via 254 and includes a flared portion for impedance matching purpose. Likewise, the widened portion 288 is electrically coupled to the signal via 258 and includes a flared portion for impedance matching purposes. The input CPW 280 includes a ground plane 290 having opposing waveguide portions 292 and 294 on opposite sides of the widened portion 286. The waveguide portion 292 is electrically coupled to the ground via 266 and the waveguide portion 294 is electrically coupled to the ground via 264. Likewise, the output CPW 282 includes a ground plane 296 having opposing waveguide portions 298 and 300 on opposite sides of the widened portion 288. The waveguide portion 298 is electrically coupled to the ground via 274 and the waveguide portion 300 is electrically coupled to the ground via 272.
A short finite output CPW 460 is formed on a top surface 462 of the bottom wafer 424, and includes a signal line 464 and opposing ground planes 466 and 468, where the signal line 464 includes a widened portion 470. A metallized bump 472 provides an electrical connection between the signal line 442 and the signal line 464, a metallized bump 474 provides an electrical connection between the ground plane 444 and the ground plane 466, and a metallized bump 476 provides an electrical connection between the ground plane 446 and the ground plane 468, where the bumps 472, 474 and 476 are provided between the wafers 422 and 424.
The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion, and from the accompanying drawings and claims, that various changes, modifications and variations can be made therein without departing from the spirit and scope of the invention as defined in the following claims.
This application is a Continuation-in-Part application of U.S. patent application Ser. No. 11/171,628, titled Microstrip-to-Microstrip RF Transition Including Co-Planar Waveguide, filed Jun. 30, 2005, which claims priority to U.S. Provisional Patent Application No. 60/584,328, titled Microstrip-to-Microstrip RF Transition Including Co-Planar Waveguide, filed Jun. 30, 2004.
| Number | Date | Country | |
|---|---|---|---|
| 60584328 | Jun 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11171628 | Jun 2005 | US |
| Child | 11940843 | Nov 2007 | US |
