Migrating Data Between Storage Tiers in a Dispersed Storage Network

Abstract

A method for a distributed storage network begins by selecting a plurality of memory elements for utilization analysis, where the memory elements are configured to store a data object that is dispersed error encoded to produce sets of encoded data slices. The method continues by determining, based on the utilization analysis, a relative utilization for each memory element and in response to the relative utilization for each memory element, determining whether to migrate encoded data slices from a first memory element to a second memory element. In response to a determination to migrate the encoded data slices from the first memory element to the second memory element, the method continues by providing a monitoring structure to track migration of the one or more encoded data slices and migrating the encoded data slices from the first memory element to the second memory element and updating a lookup table associated with the one or more encoded data slices.

Description

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC

Not applicable.

BACKGROUND OF THE INVENTION

Technical Field of the Invention

This invention relates generally to computer networks and more particularly to dispersing error encoded data.

Description of Related Art

Computing devices are known to communicate data, process data, and/or store data. Such computing devices range from wireless smart phones, laptops, tablets, personal computers (PC), work stations, and video game devices, to data centers that support millions of web searches, stock trades, or on-line purchases every day. In general, a computing device includes a central processing unit (CPU), a memory system, user input/output interfaces, peripheral device interfaces, and an interconnecting bus structure.

As is further known, a computer may effectively extend its CPU by using “cloud computing” to perform one or more computing functions (e.g., a service, an application, an algorithm, an arithmetic logic function, etc.) on behalf of the computer. Further, for large services, applications, and/or functions, cloud computing may be performed by multiple cloud computing resources in a distributed manner to improve the response time for completion of the service, application, and/or function. For example, Hadoop is an open source software framework that supports distributed applications enabling application execution by thousands of computers.

In addition to cloud computing, a computer may use “cloud storage” as part of its memory system. As is known, cloud storage enables a user, via its computer, to store files, applications, etc. on an Internet storage system. Inherent in cloud storage-based systems, as in other storage systems, is a need for security mechanisms, therefore authentication mechanisms are also needed for access requests for data distributed in cloud storage memory. Additionally, authorization lists can also be distributed as data in cloud storage-based storage networks.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 is a schematic block diagram of an embodiment of a dispersed or distributed storage network (DSN) in accordance with the present invention;

FIG. 2 is a schematic block diagram of an embodiment of a computing core in accordance with the present invention;

FIG. 3 is a schematic block diagram of an example of dispersed storage error encoding of data in accordance with the present invention;

FIG. 4 is a schematic block diagram of a generic example of an error encoding function in accordance with the present invention;

FIG. 5 is a schematic block diagram of a specific example of an error encoding function in accordance with the present invention;

FIG. 6 is a schematic block diagram of an example of a slice name of an encoded data slice (EDS) in accordance with the present invention;

FIG. 7 is a schematic block diagram of an example of dispersed storage error decoding of data in accordance with the present invention;

FIG. 8 is a schematic block diagram of a generic example of an error decoding function in accordance with the present invention;

FIG. 9A is a flowchart illustrating an example of authorizing an access request in accordance with the present invention; and

FIG. 9B is a diagram illustrating an example of an authorization table in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of an embodiment of a dispersed, or distributed, storage network (DSN) 10 that includes a plurality of computing devices 12-16, a managing unit 18, an integrity processing unit 20, and a DSN memory 22. The components of the DSN 10 are coupled to a network 24, which may include one or more wireless and/or wire lined communication systems; one or more non-public intranet systems and/or public internet systems; and/or one or more local area networks (LAN) and/or wide area networks (WAN).

The DSN memory 22 includes a plurality of storage units 36 that may be located at geographically different sites (e.g., one in Chicago, one in Milwaukee, etc.), at a common site, or a combination thereof. For example, if the DSN memory 22 includes eight storage units 36, each storage unit is located at a different site. As another example, if the DSN memory 22 includes eight storage units 36, all eight storage units are located at the same site. As yet another example, if the DSN memory 22 includes eight storage units 36, a first pair of storage units are at a first common site, a second pair of storage units are at a second common site, a third pair of storage units are at a third common site, and a fourth pair of storage units are at a fourth common site. Note that a DSN memory 22 may include more or less than eight storage units 36. Further note that each storage unit 36 includes a computing core (as shown in FIG. 2, or components thereof) and a plurality of memory devices for storing dispersed error encoded data.

Each of the computing devices 12-16, the managing unit 18, and the integrity processing unit 20 include a computing core 26, which includes network interfaces 30-33. Computing devices 12-16 may each be a portable computing device and/or a fixed computing device. A portable computing device may be a social networking device, a gaming device, a cell phone, a smart phone, a digital assistant, a digital music player, a digital video player, a laptop computer, a handheld computer, a tablet, a video game controller, and/or any other portable device that includes a computing core. A fixed computing device may be a computer (PC), a computer server, a cable set-top box, a satellite receiver, a television set, a printer, a fax machine, home entertainment equipment, a video game console, and/or any type of home or office computing equipment. Note that each of the managing unit 18 and the integrity processing unit 20 may be separate computing devices, may be a common computing device, and/or may be integrated into one or more of the computing devices 12-16 and/or into one or more of the storage units 36.

Each interface 30, 32, and 33 includes software and hardware to support one or more communication links via the network 24 indirectly and/or directly. For example, interface 30 supports a communication link (e.g., wired, wireless, direct, via a LAN, via the network 24, etc.) between computing devices 14 and 16. As another example, interface 32 supports communication links (e.g., a wired connection, a wireless connection, a LAN connection, and/or any other type of connection to/from the network 24) between computing devices 12 & 16 and the DSN memory 22. As yet another example, interface 33 supports a communication link for each of the managing unit 18 and the integrity processing unit 20 to the network 24.

Computing devices 12 and 16 include a dispersed storage (DS) client module 34, which enables the computing device to dispersed storage error encode and decode data as subsequently described with reference to one or more of FIGS. 3-8. In this example embodiment, computing device 16 functions as a dispersed storage processing agent for computing device 14. In this role, computing device 16 dispersed storage error encodes and decodes data on behalf of computing device 14. With the use of dispersed storage error encoding and decoding, the DSN 10 is tolerant of a significant number of storage unit failures (the number of failures is based on parameters of the dispersed storage error encoding function) without loss of data and without the need for a redundant or backup copies of the data. Further, the DSN 10 stores data for an indefinite period of time without data loss and in a secure manner (e.g., the system is very resistant to unauthorized attempts at accessing the data).

In operation, the managing unit 18 performs DS management services. For example, the managing unit 18 establishes distributed data storage parameters (e.g., vault creation, distributed storage parameters, security parameters, billing information, user profile information, etc.) for computing devices 12-14 individually or as part of a group of user devices. As a specific example, the managing unit 18 coordinates creation of a vault (e.g., a virtual memory block associated with a portion of an overall namespace of the DSN) within the DSN memory 22 for a user device, a group of devices, or for public access and establishes per vault dispersed storage (DS) error encoding parameters for a vault. The managing unit 18 facilitates storage of DS error encoding parameters for each vault by updating registry information of the DSN 10, where the registry information may be stored in the DSN memory 22, a computing device 12-16, the managing unit 18, and/or the integrity processing unit 20.

The DSN managing unit 18 creates and stores user profile information (e.g., an access control list (ACL)) in local memory and/or within memory of the DSN module 22. The user profile information includes authentication information, permissions, and/or the security parameters. The security parameters may include encryption/decryption scheme, one or more encryption keys, key generation scheme, and/or data encoding/decoding scheme.

The DSN managing unit 18 creates billing information for a particular user, a user group, a vault access, public vault access, etc. For instance, the DSN managing unit 18 tracks the number of times a user accesses a non-public vault and/or public vaults, which can be used to generate a per-access billing information. In another instance, the DSN managing unit 18 tracks the amount of data stored and/or retrieved by a user device and/or a user group, which can be used to generate a per-data-amount billing information.

As another example, the managing unit 18 performs network operations, network administration, and/or network maintenance. Network operations includes authenticating user data allocation requests (e.g., read and/or write requests), managing creation of vaults, establishing authentication credentials for user devices, adding/deleting components (e.g., user devices, storage units, and/or computing devices with a DS client module 34) to/from the DSN 10, and/or establishing authentication credentials for the storage units 36. Network administration includes monitoring devices and/or units for failures, maintaining vault information, determining device and/or unit activation status, determining device and/or unit loading, and/or determining any other system level operation that affects the performance level of the DSN 10. Network maintenance includes facilitating replacing, upgrading, repairing, and/or expanding a device and/or unit of the DSN 10.

The integrity processing unit 20 performs rebuilding of ‘bad’ or missing encoded data slices. At a high level, the integrity processing unit 20 performs rebuilding by periodically attempting to retrieve/list encoded data slices, and/or slice names of the encoded data slices, from the DSN memory 22. For retrieved encoded slices, they are checked for errors due to data corruption, outdated version, etc. If a slice includes an error, it is flagged as a ‘bad’ slice. For encoded data slices that were not received and/or not listed, they are flagged as missing slices. Bad and/or missing slices are subsequently rebuilt using other retrieved encoded data slices that are deemed to be good slices to produce rebuilt slices. The rebuilt slices are stored in the DSN memory 22.

FIG. 2 is a schematic block diagram of an embodiment of a computing core 26 that includes a processing module 50, a memory controller 52, main memory 54, a video graphics processing unit 55, an input/output (IO) controller 56, a peripheral component interconnect (PCI) interface 58, an IO interface module 60, at least one IO device interface module 62, a read only memory (ROM) basic input output system (BIOS) 64, and one or more memory interface modules. The one or more memory interface module(s) includes one or more of a universal serial bus (USB) interface module 66, a host bus adapter (HBA) interface module 68, a network interface module 70, a flash interface module 72, a hard drive interface module 74, and a DSN interface module 76.

The DSN interface module 76 functions to mimic a conventional operating system (OS) file system interface (e.g., network file system (NFS), flash file system (FFS), disk file system (DFS), file transfer protocol (FTP), web-based distributed authoring and versioning (WebDAV), etc.) and/or a block memory interface (e.g., small computer system interface (SCSI), internet small computer system interface (iSCSI), etc.). The DSN interface module 76 and/or the network interface module 70 may function as one or more of the interface 30-33 of FIG. 1. Note that the IO device interface module 62 and/or the memory interface modules 66-76 may be collectively or individually referred to as IO ports.

FIG. 3 is a schematic block diagram of an example of dispersed storage error encoding of data. When a computing device 12 or 16 has data to store it disperse storage error encodes the data in accordance with a dispersed storage error encoding process based on dispersed storage error encoding parameters. The dispersed storage error encoding parameters include an encoding function (e.g., information dispersal algorithm, Reed-Solomon, Cauchy Reed-Solomon, systematic encoding, non-systematic encoding, on-line codes, etc.), a data segmenting protocol (e.g., data segment size, fixed, variable, etc.), and per data segment encoding values. The per data segment encoding values include a total, or pillar width, number (T) of encoded data slices per encoding of a data segment i.e., in a set of encoded data slices); a decode threshold number (D) of encoded data slices of a set of encoded data slices that are needed to recover the data segment; a read threshold number (R) of encoded data slices to indicate a number of encoded data slices per set to be read from storage for decoding of the data segment; and/or a write threshold number (W) to indicate a number of encoded data slices per set that must be accurately stored before the encoded data segment is deemed to have been properly stored. The dispersed storage error encoding parameters may further include slicing information (e.g., the number of encoded data slices that will be created for each data segment) and/or slice security information (e.g., per encoded data slice encryption, compression, integrity checksum, etc.).

In the present example, Cauchy Reed-Solomon has been selected as the encoding function (a generic example is shown in FIG. 4 and a specific example is shown in FIG. 5); the data segmenting protocol is to divide the data object into fixed sized data segments; and the per data segment encoding values include: a pillar width of 5, a decode threshold of 3, a read threshold of 4, and a write threshold of 4. In accordance with the data segmenting protocol, the computing device 12 or 16 divides the data (e.g., a file (e.g., text, video, audio, etc.), a data object, or other data arrangement) into a plurality of fixed sized data segments (e.g., 1 through Y of a fixed size in range of Kilo-bytes to Tera-bytes or more). The number of data segments created is dependent of the size of the data and the data segmenting protocol.

The computing device 12 or 16 then disperse storage error encodes a data segment using the selected encoding function (e.g., Cauchy Reed-Solomon) to produce a set of encoded data slices. FIG. 4 illustrates a generic Cauchy Reed-Solomon encoding function, which includes an encoding matrix (EM), a data matrix (DM), and a coded matrix (CM). The size of the encoding matrix (EM) is dependent on the pillar width number (T) and the decode threshold number (D) of selected per data segment encoding values. To produce the data matrix (DM), the data segment is divided into a plurality of data blocks and the data blocks are arranged into D number of rows with Z data blocks per row. Note that Z is a function of the number of data blocks created from the data segment and the decode threshold number (D). The coded matrix is produced by matrix multiplying the data matrix by the encoding matrix.

FIG. 5 illustrates a specific example of Cauchy Reed-Solomon encoding with a pillar number (T) of five and decode threshold number of three. In this example, a first data segment is divided into twelve data blocks (D1-D12). The coded matrix includes five rows of coded data blocks, where the first row of X11-X14 corresponds to a first encoded data slice (EDS 1_1), the second row of X21-X24 corresponds to a second encoded data slice (EDS 2_1), the third row of X31-X34 corresponds to a third encoded data slice (EDS 3_1), the fourth row of X41-X44 corresponds to a fourth encoded data slice (EDS 4_1), and the fifth row of X51-X54 corresponds to a fifth encoded data slice (EDS 5_1). Note that the second number of the EDS designation corresponds to the data segment number.

Returning to the discussion of FIG. 3, the computing device also creates a slice name (SN) for each encoded data slice (EDS) in the set of encoded data slices. A typical format for a slice name 60 is shown in FIG. 6. As shown, the slice name (SN) 60 includes a pillar number of the encoded data slice (e.g., one of 1-T), a data segment number (e.g., one of 1-Y), a vault identifier (ID), a data object identifier (ID), and may further include revision level information of the encoded data slices. The slice name functions as, at least part of, a DSN address for the encoded data slice for storage and retrieval from the DSN memory 22. In some examples, the slice name includes universal DSN memory addressing routing information (e.g., virtual memory addresses in the DSN memory 22) and user-specific information (e.g., user ID, file name, data block identifier, etc.).

As a result of encoding, the computing device 12 or 16 produces a plurality of sets of encoded data slices, which are provided with their respective slice names to the storage units for storage. As shown, the first set of encoded data slices includes EDS 1_1 through EDS 5_1 and the first set of slice names includes SN 1_1 through SN 5_1 and the last set of encoded data slices includes EDS 1_Y through EDS 5_Y and the last set of slice names includes SN 1_Y through SN 5_Y.

FIG. 7 is a schematic block diagram of an example of dispersed storage error decoding of a data object that was dispersed storage error encoded and stored in the example of FIG. 4. In this example, the computing device 12 or 16 retrieves from the storage units at least the decode threshold number of encoded data slices per data segment. As a specific example, the computing device retrieves a read threshold number of encoded data slices.

To recover a data segment from a decode threshold number of encoded data slices, the computing device uses a decoding function as shown in FIG. 8. As shown, the decoding function is essentially an inverse of the encoding function of FIG. 4. The coded matrix includes a decode threshold number of rows (e.g., three in this example) and the decoding matrix in an inversion of the encoding matrix that includes the corresponding rows of the coded matrix. For example, if the coded matrix includes rows 1, 2, and 4, the encoding matrix is reduced to rows 1, 2, and 4, and then inverted to produce the decoding matrix.

FIG. 9A is a flowchart illustrating an example of authorizing an access request. The method begins with step 136 where a processing module receives an access request. Such an access request may include one or more of a user identifier (ID), an access type (e.g., read, write, delete, list, list range, check, etc.), a user password, a user realm indicator, a command, a data object name, a data object, a virtual dispersed storage network (DSN) address, a performance indicator, a priority indicator, a security indicator, access request requirements, a vault ID, a DSN system element access request, a DSN resource request, a vault access request, and a record access request. The processing module may receive the access request from one or more of a user device, the dispersed storage (DS) processing unit, a storage integrity processing unit, a DS managing unit, and a DS unit.

The method continues at step 138 where the processing module determines the realm. Such a realm indicates an affiliation of one or more user devices/users. For example, the realm indicates a group associated with a particular organization (e.g., a company, a team, a family, a work group, a social group, a community, a geographic region, etc.). Such a determination of the realm may be based on one or more of user information, realm information, an authorization table lookup, a received realm indicator, a user ID, a user password, a vault lookup, a table lookup, and any other information from the access request.

The method continues at step 140 where the processing module determines an authorization service. Such an authorization service indicates an identity and/or address to provide subsequent authorization of the access request. For example, the processing module identifies the authorization service to include a third-party, which may or may not be part of the DSN computing system. Such a third-party may provide authorization information (e.g., if a user or group is allowed to perform a particular type of DSN computing system access). Such a determination of the authorization service may be based on one or more of information associated with the realm, an authorization table lookup, a vault lookup, a user ID, a user password, and information received in the access request.

The method continues at step 142 where the processing module generates an authorization request and sends the authorization request to the authorization service. Such an authorization request may include one or more of the user ID, a user password, user information, the user realm information, a command, the data object name, a virtual DSN address, and a DS processing module ID. The method continues at step 144 where the processing module receives an authorization request response from the authorization service. The method continues at step 146 where the processing module determines whether the request is authorized based on the authorization request response. The method ends at step 148 where the processing module sends a reject message when the processing module determines that the request is not authorized. The processing module may send the reject message to the requester and/or the DS managing unit. The method continues to step 150 when the processing module determines that the request is authorized. The method continues at step 150 where the processing module processes the access request (e.g., processes a command including store, retrieve, delete, list, etc.).

FIG. 9B is a diagram illustrating an example of an authorization table 152. Such an authorization table 152 may be utilized by a processing module to determine an authorization service based on user information as discussed with reference to the method of FIG. 7 A. Such an authorization table 152 may be stored in one or more of a dispersed storage (DS) unit, a DS managing unit, a storage integrity processing unit, a user device, and a DS processing unit. In an example, the DS managing unit generates the authorization table 152 and sends the information of the authorization table 152 to the DS unit for storage and ongoing use to authorize access requests.

The authorization table 152 includes a user information field 154, a realm field 156, and an authorization service field 158. The user information field 154 includes identities of one or more users and/or user devices associated, wherein each user is associated with a particular realm. For example, an e-mail address may be utilized to uniquely identify a user and/or user device. The realm field 156 includes group identities associated with the one or more users. For example, a realm entry identifies a domain of an e-mail address such that a shared affiliation is a common e-mail domain (e.g., a company, an organization, etc.). The authorization service field 158 includes an identity and address of an associated authorization service corresponding to a realm. For example, an entry of the authorization service field 158 indicates an Internet address that may be utilized to send an authorization request to and receive a corresponding authorization request response.

In an example of operation, an e-mail address of joew@cleversafe.com is utilized to index into the authorization table 152 by matching e-mail address to an entry of the user information field 154. An associated realm of cleversafe.com is extracted from the realm field 156 based on a corresponding e-mail address entry matched to an entry of the associated realm. Next, an authorization service address of ldaps.cleversafe.com is extracted from the authorization service field 158 based on the corresponding e-mail address entry matched to an entry of the associated authorization service. An access request authorization message is sent to the ldaps.cleversafe.com address to determine whether an associated access request is authorized.

It is noted that terminologies as may be used herein such as bit stream, stream, signal sequence, etc. (or their equivalents) have been used interchangeably to describe digital information whose content corresponds to any of a number of desired types (e.g., data, video, speech, text, graphics, audio, etc. any of which may generally be referred to as ‘data’).

As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. For some industries, an industry-accepted tolerance is less than one percent and, for other industries, the industry-accepted tolerance is 10 percent or more. Other examples of industry-accepted tolerance range from less than one percent to fifty percent. Industry-accepted tolerances correspond to, but are not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, thermal noise, dimensions, signaling errors, dropped packets, temperatures, pressures, material compositions, and/or performance metrics. Within an industry, tolerance variances of accepted tolerances may be more or less than a percentage level (e.g., dimension tolerance of less than +/−1%). Some relativity between items may range from a difference of less than a percentage level to a few percent. Other relativity between items may range from a difference of a few percent to magnitude of differences.

As may also be used herein, the term(s) “configured to”, “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for an example of indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”.

As may even further be used herein, the term “configured to”, “operable to”, “coupled to”, or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item.

As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1. As may be used herein, the term “compares unfavorably”, indicates that a comparison between two or more items, signals, etc., fails to provide the desired relationship.

As may be used herein, one or more claims may include, in a specific form of this generic form, the phrase “at least one of a, b, and c” or of this generic form “at least one of a, b, or c”, with more or less elements than “a”, “b”, and “c”. In either phrasing, the phrases are to be interpreted identically. In particular, “at least one of a, b, and c” is equivalent to “at least one of a, b, or c” and shall mean a, b, and/or c. As an example, it means: “a” only, “b” only, “c” only, “a” and “b”, “a” and “c”, “b” and “c”, and/or “a”, “b”, and “c”.

As may also be used herein, the terms “processing module”, “processing circuit”, “processor”, “processing circuitry”, and/or “processing unit” may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, processing circuitry, and/or processing unit may be, or further include, memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processing module, module, processing circuit, processing circuitry, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, processing circuitry, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, processing circuitry and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, processing circuitry and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture.

One or more embodiments have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality.

To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claims. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.

In addition, a flow diagram may include a “start” and/or “continue” indication. The “start” and “continue” indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with one or more other routines. In addition, a flow diagram may include an “end” and/or “continue” indication. The “end” and/or “continue” indications reflect that the steps presented can end as described and shown or optionally be incorporated in or otherwise used in conjunction with one or more other routines. In this context, “start” indicates the beginning of the first step presented and may be preceded by other activities not specifically shown. Further, the “continue” indication reflects that the steps presented may be performed multiple times and/or may be succeeded by other activities not specifically shown. Further, while a flow diagram indicates a particular ordering of steps, other orderings are likewise possible provided that the principles of causality are maintained.

The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from figure to figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones.

Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art.

The term “module” is used in the description of one or more of the embodiments. A module implements one or more functions via a device such as a processor or other processing device or other hardware that may include or operate in association with a memory that stores operational instructions. A module may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules.

As may further be used herein, a computer readable memory includes one or more memory elements. A memory element may be a separate memory device, multiple memory devices, or a set of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, a quantum register or other quantum memory and/or any other device that stores data in a non-transitory manner. Furthermore, the memory device may be in a form of a solid-state memory, a hard drive memory or other disk storage, cloud memory, thumb drive, server memory, computing device memory, and/or other non-transitory medium for storing data. The storage of data includes temporary storage (i.e., data is lost when power is removed from the memory element) and/or persistent storage (i.e., data is retained when power is removed from the memory element). As used herein, a transitory medium shall mean one or more of: (a) a wired or wireless medium for the transportation of data as a signal from one computing device to another computing device for temporary storage or persistent storage; (b) a wired or wireless medium for the transportation of data as a signal within a computing device from one element of the computing device to another element of the computing device for temporary storage or persistent storage; (c) a wired or wireless medium for the transportation of data as a signal from one computing device to another computing device for processing the data by the other computing device; and (d) a wired or wireless medium for the transportation of data as a signal within a computing device from one element of the computing device to another element of the computing device for processing the data by the other element of the computing device. As may be used herein, a non-transitory computer readable memory is substantially equivalent to a computer readable memory. A non-transitory computer readable memory can also be referred to as a non-transitory computer readable storage medium.

While particular combinations of various functions and features of the one or more embodiments have been expressly described herein, other combinations of these features and functions are likewise possible. The present disclosure is not limited by the particular examples disclosed herein and expressly incorporates these other combinations.

Claims

1. A method for execution by a storage network comprises: selecting a plurality of memory elements for utilization analysis, wherein the plurality of memory elements are configured to store one or more data objects, wherein a data object is dispersed error encoded to produce one or more sets of encoded data slices;determining, based on the utilization analysis, a relative utilization for each memory element of the plurality of memory elements;in response to the relative utilization for each memory element, determining whether to migrate one or more encoded data slices of the one or more sets of encoded data slices from a first memory element of the plurality of memory elements to a second memory element of the plurality of memory elements;in response to a determination to migrate one or more encoded data slices from the first memory element to the second memory element, providing a monitoring structure to track migration of the one or more encoded data slices;migrating the one or more encoded data slices from the first memory element to the second memory element; andupdating metadata associated with the one or more encoded data slices.

2. The method of claim 1, further comprising: validating the one or more encoded data slices after migration from the first memory element to the second memory element.

3. The method of claim 1, wherein the plurality of memory elements are selected from a group comprising: 1) a solid state memory device;2) a storage unit;3) a storage network memory element;4) a group of memory devices; and5) hard drive memory.

4. The method of claim 1, wherein the first memory element and the second memory element are in a same storage unit.

5. The method of claim 1, wherein the first memory element and the second memory element are in different storage units.

6. The method of claim 1, wherein the determining whether to migrate the one or more encoded data slices is based on at least one of an impact on ongoing operations, an amount of data currently stored on each memory element, an estimated number of encoded data slices to be migrated, an estimated time for completion of migrating the one or more encoded data slices, an estimated performance degradation of the storage network due to the migration, or a storage tier for the first memory element and the second memory element.

7. The method of claim 1, wherein the determining whether to migrate the one or more encoded data slices is based on an impact to the storage network, wherein the impact is at least one of: a monetary cost of migrating the one or more encoded data slices, a time required to migrate the one or more encoded data slices, an estimated downtime required for migrating the one or more encoded data slices, an estimated network bandwidth utilization from migrating the one or more encoded data slices, or an estimated performance degradation from migrating the one or more encoded data slices.

8. The method of claim 1, further comprising: in response to a determination not to migrate the one or more encoded data slices from the first memory element to the second memory element, determining to delay the migration to an off-peak time period, wherein an off-peak time period is a time period during which storage network traffic is statistically lower than another time period.

9. The method of claim 1, wherein the determining whether to migrate the one or more encoded data slices is based on at least one of: an aggregate number of encoded data slices stored in the plurality of memory elements, an estimated number of encoded data slices subject to migration, a cost difference between the first memory element and the second element, or a cost difference between a storage unit associated with the first memory element and a cost difference between a storage unit associated with the second element.

10. The method of claim 1, wherein the selecting a plurality of memory elements for utilization analysis is based on at least one of an error message, a command, a predetermination, an automated instruction, a list or a schedule.

11. The method of claim 1, wherein selecting a plurality of memory elements for utilization analysis is based on a predetermined schedule, wherein the predetermined schedule is a schedule adapted to chronologically select substantially all memory elements of the storage network elements over a finite time period.

12. A computing device for a storage network comprises: one or more network interfaces;memory including operational instructions; anda processing module operably coupled to the memory and the one or more network interfaces, the processing module configured to execute the operational instructions to: select a plurality of storage network memory elements for utilization analysis, wherein the plurality of memory elements are configured to store one or more data objects, wherein a data object is dispersed error encoded to produce one or more sets of encoded data slices;determine, based on the utilization analysis, a relative utilization for each memory element of the plurality of storage network memory elements;in response to the relative utilization for each memory element, determine whether to migrate one or more encoded data slices of the one or more sets of encoded data slices from a first memory element of the plurality of storage network memory elements to a second memory element of the plurality of storage network memory elements;in response to a determination to migrate one or more encoded data slices from the first memory element to the second memory element, provide a monitoring structure to track migration of the one or more encoded data slices;migrate the one or more encoded data slices from the first memory element to the second memory element; andupdate metadata associated with the one or more encoded data slices.

13. The computing device of claim 12, further comprising: validating the one or more encoded data slices after migration from the first memory element to the second memory element.

14. The computing device of claim 12, wherein the plurality of memory elements are selected from a group comprising: 1) a solid state memory device;2) a storage unit;3) a storage network memory element;4) a group of memory devices; and5) hard drive memory.

15. The computing device of claim 12, wherein the determining whether to migrate the one or more encoded data slices is based on at least one of an impact on ongoing operations, an amount of data currently stored on each memory element, an estimated number of encoded data slices to be migrated, an estimated time for completion of migrating the one or more encoded data slices, an estimated performance degradation of the storage network due to the migration, or the relative storage tier for the first memory element and the second memory element.

16. The computing device of claim 12, wherein the determining whether to migrate the one or more encoded data slices is based on an impact to the storage network, wherein the impact is at least one of: a monetary cost of migrating the one or more encoded data slices, a time required to migrate the one or more encoded data slices, an estimated downtime required for migrating the one or more encoded data slices, an estimated network bandwidth utilization from migrating the one or more encoded data slices, or an estimated performance degradation from migrating the one or more encoded data slices.

17. The computing device of claim 12, further comprising: in response to a determination not to migrate the one or more encoded data slices from the first memory element to the second memory element, determining to delay the migration to an off-peak time period, wherein an off-peak time period is a time period during which storage network traffic is statistically lower than another time period.

18. The computing device of claim 12, wherein the determining whether to migrate the one or more encoded data slices is based on at least one of: an aggregate number of encoded data slices stored in the plurality of memory elements, an estimated number of encoded data slices subject to migration, a cost difference between the first memory element and the second element, or a cost difference between a storage unit associated with the first memory element and a cost difference between a storage unit associated with the second element.

19. The computing device of claim 12, wherein the plurality of memory elements are selected for utilization analysis based on at least one of an error message, a command, an automated instruction, a list or a schedule, a predetermined schedule, wherein the predetermined schedule is a schedule adapted to chronologically select substantially all memory elements of the storage network elements over a finite time period.

20. A system for managing data storage in a storage network comprises: one or more modules of one or more processing devices; anda plurality of storage network memory elements configured to store one or more data objects, wherein a data object is dispersed error encoded to produce one or more sets of encoded data slices, wherein the one or more modules of one or more processing devices are adapted to: select a subset of the plurality of storage network memory elements for utilization analysis;determine, based on the utilization analysis, a relative utilization for each storage network memory element of the subset of storage network memory elements;in response to the relative utilization for each memory element, determine whether to migrate one or more encoded data slices of the one or more sets of encoded data slices from a first memory element of the subset of memory elements to a second memory element of the subset of memory elements;in response to a determination to migrate one or more encoded data slices from the first memory element to the second memory element, migrate the one or more encoded data slices from the first memory element to the second memory element;monitor the migration of the one or more encoded data slices; andupdate metadata associated with the one or more encoded data slices.