Patent Application
20090219981
The present invention relates to the field of communication devices, e.g. wireless communication devices. More particularly, the present invention relates to the field of signal equalisation, especially minimum mean square error equalisation. The present invention especially relates to an equaliser for a communication device, a method of equalising one or more received signals and a software program product for carrying out the method.
Minimum Mean Square Error (MMSE) equalisers are well known means to improve the performance of a communication system. MMSE equalisers are known to minimize the error power which is due to inter-symbol interference (ISI) and noise.
Equalisers are employed in the frequency domain and in the time domain and may be accordingly classified as frequency domain equalisers (FDE) or time domain equalisers (TDE). Single tap equalisers are directly applicable for equalisation in the frequency domain. Multi tap equalisers are directly applicable in the time domain. However, equalisation in the time domain may also be based on a single tap equaliser and equalisation in the frequency domain may also be based on a multi tap equaliser.
Single-carrier (SC) and multi-carrier (MC) communication systems are well known. MC systems can be implemented using, for example, but not exclusively, orthogonal frequency division multiplexing (OFDM), multi-carrier code division multiple access (CDMA), wavelet based multi-carrier techniques, OFDM-CDMA and other combinations and variations thereof. In MC systems, traditionally, but not necessarily, equalisation is performed in the frequency domain.
Traditionally, communication channels with a single input and a single output (SISO communication systems) were employed, in recent times however, communication channels with multi inputs and/or multiple output have enjoyed a widespread use, which leads the notion of MISO, SIMO and MIMO communication systems.
To implement a conventional MMSE equaliser, a division (or inversion) operation is required. Given for example the conventional single tap, SISO, MMSE equaliser, which performs equalisation of a received signal by multiplying the received signal with a factor g which is defined by
whereby σn2 represent the noise variance, h represents the channel response and * denotes complex conjugation, the dividend h* has to be divided by the divisor |h|2+σn2. In order to reduce the computational complexity, the division operation may be implemented deploying a look-up table (LUT). Hereby, the inverse of the divisor is taken from the LUT and the division operation is replaced by the (computationally less complex) multiplication of the dividend with the inverse of the divisor. This, however, introduces the problem that the look-up table has to be very large in order to cope with the large dynamic range of the channel responses and the noise variances.
S. Kaiser, “On the performance of Different Detection Schemes for OFDM-CDMA in fading channels”, IEEE International Conference on Communications (ICC '1995), vol. 3, pp. 1722-1726, Seattle, USA June 1995 discloses a plurality of OFDM-CDMA equaliser structures including a controlled equalisation and a MMSE equalisation. In the controlled equalisation according to Kaiser, one of two equaliser structures is selected depending on the received signal power, which results improved zero forcing (ZF) equaliser. In the MMSE equalisation according to Kaiser, the signal-to-noise ratio (SNR) parameter is set to a fixed value, which results in a suboptimal MMSE equaliser.
The problem to be solved by the present invention is to provide for an equaliser, communication device and method for equalising one or more received signal with reduced complexity and a corresponding software program product.
This problem is solved by an equaliser for a communication device comprising a filter calculator for determining a channel power value based on one or more channel response values and selecting one of two or more equaliser structures based on said channel power value and based on at least one threshold value for separating the channel power values into at least two ranges; and a filter for equalising one or more received signals according to the selected equaliser structure.
Advantageously, said filter calculator is adapted to select a first equaliser structure in case said channel power value is below a first threshold value and to select a second equalising structure in case said channel power value is above said first threshold value.
In a first embodiment of the equaliser, said filter calculator, in accordance with said first equaliser structure, is advantageously adapted to calculate a first product of the conjugate complex of a channel response value with the inverse value of a noise variance value. Advantageously, said filter calculator, in accordance with said second equaliser structure, is adapted to calculate a second product of the conjugate complex of a channel response value with the inverse value of the sum of said channel power value and said noise variance value. Advantageously, said filter calculator is adapted to calculate said first product based on a first look-up table and said second product based on a second look-up table, said first and second look-up tables having different quantisations.
In a second embodiment of the equaliser, the equaliser advantageously comprises a memory for storing a predetermined value and said filter calculator, in accordance with said first equaliser structure, is adapted to calculate a first product of the conjugate complex of a channel response value with either said predetermined value or the inverse value of said predetermined value. Advantageously, said filter calculator, in accordance with said second equaliser structure, is adapted to calculate the sum of said channel power value with either said predetermined value or the inverse of said predetermined value and to calculate a second product of the conjugate complex of a channel response value with the inverse of said sum. Said predetermined value or its inverse may, for example, correspond to a maximum value of a SNR or a minimum value of a noise variance.
Advantageously, said filter calculator is adapted to select a third equaliser structure in case said channel power value is above a second threshold value that is larger than said first threshold value and to select said second filter structure in case said channel power value is above said first threshold value and below said second threshold value. In this case, said filter calculator, in accordance with said third equaliser structure, is advantageously adapted to calculate a third product of the conjugate complex of a channel response value with the inverse value of said channel power value based on a look-up table.
The equaliser according to the present invention may be employed in a MIMO communication device. Advantageously in this case, said channel power value is the largest element of a channel power matrix. Advantageously, said filter calculator is adapted to calculate said channel power matrix by multiplying the Hermitian transpose of a channel matrix with the channel matrix, whereby said channel matrix comprises said one or more channel response values.
In a fourth embodiment of the equaliser, said filter calculator, in accordance with said first equaliser structure, is advantageously adapted to calculate a first matrix corresponding to the Hermitian transpose of said channel matrix multiplied by the inverse of a noise variance value. Advantageously, said filter calculator is adapted to calculate the inverse value of said noise variance value using a look-up table.
In a fifth embodiment of the equaliser, the equaliser advantageously comprises a memory for storing a predetermined value, whereby said filter calculator, in accordance with said first equaliser structure, is adapted to calculate a first filter matrix corresponding to the Hermitian transpose of said channel matrix multiplied by either said predetermined value or the inverse of said predetermined value. Advantageously, said filter calculator, in accordance with said second equaliser structure, is adapted to calculate a second matrix corresponding to a conventional minimum mean square error equaliser matrix whereby the value of a noise power parameter required for calculating said second filter matrix is set to said predetermined value.
In an embodiment, the equaliser advantageously comprises at least two look-up tables for implementing corresponding at least two division or inversion operations, said at least two look-up tables having a different quantization. Advantageously, each of said division or inversion operations corresponds to a different one of said equaliser structures.
Advantageously in case of said second and fifth embodiment of the equaliser, said first threshold value is given by the product of a first factor with said noise variance value.
Advantageously, at least one of said equaliser structures corresponds to an, at least approximated, minimum mean square error equaliser structure or to an, at least approximated, suboptimal minimum mean square error equaliser structure.
The problem is further solved by a communication device comprising an equaliser according to the present invention.
The problem is further solved by a method of equalising one or more received signals comprising the steps of determining a channel power value based on one or more channel response values; selecting one of two or more equaliser structures based on said channel power value; and equalising said one or more received signals according to the selected equaliser structure. Hereby, at least one of said equaliser structures corresponds to an, at least approximated, minimum mean square error equaliser structure or to an, at least approximated, suboptimal minimum mean square error equaliser structure; According to the method a first equaliser structure is selected in case said channel power value is below a first threshold; and a second equaliser structure is selected in case said channel power value above said second threshold.
The problem is further solved by a software program product which, when executed in a processing device, is adapted to carry out the method of equalising one or more received signals according to the present invention.
Same reference numerals, even when used in different Figures or in relation to different embodiments, relate to the same elements.
The present invention proposes new and inventive implementations of the MMSE equalisation principle which reduce the size of the LUT needed for the division operation and, generally, provides for a reduced complexity of the equaliser and receiver. In the embodiments described in the following, various MMSE and sub-optimal MMSE equaliser implementations are provided in which one from two or three equaliser structures is selected depending on the power of a received signal.
The receiver 1 comprises a radio frequency (RF) part 2 and a baseband part 3. The RF part has an antenna 4 connected to a low noise amplifier/downconversion unit 5. A signal received by the antenna 4 is amplified and downconverted. The downconverted signal is forwarded to a filter 6 of the baseband circuit 3. After filtering, the signal is digitized using an analogue-to-digital converter (ADC) 7 and is provided to a channel estimator 8 and an FDE 9. Based on the digitized signal (e.g. based on a preamble section including training sequences) a channel estimation and synchronisation/timing information is obtained by the channel estimator 8. Signals from the channel estimator 8 are applied to an FDE 9. The FDE 9 comprises a fast Fourier transformator (FFT) 10 for transforming the digitized signal into the frequency domain. The transformed signal is then equalised by an equaliser 11, of which the constitution and operation will be described in detail later on. The equalised signal is then transformed back into the time domain by an inverse fast Fourier transformator (IFFT) 12 and provided to a demodulator 13, which may, but need not, be implemented as a soft demodulator. The demodulator 13 performs a demodulation operation (known also as ‘symbol demapping’) and may be implemented e.g. as a soft demodulator. After being deinterleaved by an deinterleaver 14, the signal is decoded (channel decoding) by a channel decoder 15 whereby received data is obtained which is put out as a bit stream.
The transmitter 20 comprises a baseband part 21 and an RF part 22. In the baseband part, a transmit data bit stream is encoded (channel encoding, e.g. based on a forward error correction code) by a channel encoder 23 and subsequently interleaved by an interleaver 24. A modulator 25 applies a modulation operation (known also as “symbol mapping” or “constellation mapping”) to the interleaved data which is further converted into an analogue signal by a DAC 26 and filtered by a filter 27. The analogue, filtered signal is then forwarded to an upconversion/power amplifier unit 28 and the upconverted and amplified signal is emitted using an antenna 29.
It is stressed that the communication system shown in
The receiver 41 comprises the RF part 2 and a baseband part 43. After downconversion in the RF part 2, a received signal is transformed by a fast Fourier transformator 46 and is provided to a channel estimator 47 and the equaliser 11 of the baseband part 43. Based on the signal (e.g. based on a preamble section including training sequences) a channel estimation and synchronisation/timing information is obtained by the channel estimator 47. A signal from the channel estimator 47 is applied to the equaliser 11, of which the configuration and the operation will be described in detail later on. The equalised signal is provided to a channel decoding/demodulating unit 49, which comprises the chain of demodulator 13, deinterleaver 14 and channel decoder 15 as described above, and from which the received data is put out as a bit stream.
The transmitter 50 comprises a baseband part 51 and the RF part 22. A transmit data bit stream is input in a channel coding/modulation unit 53 comprising the chain of channel coder 23, interleaver 24 and modulator 25 described above. The thus encoded data is transformed by an IFFT 54. The (inverse) Fourier transformed data is further processed by a DAC/filtering unit 55, comprising the chain of DAC 26 and filter 27 before it is emitted by the RF part 22.
Before the operation of the equaliser 11 is explained, the operation of a conventional single tap MMSE equaliser is described. This equaliser equalises the received signal by multiplying the received signal by a complex number g. In a multi-carrier system, like the one of
whereby hl represents the channel response, an σn,l2 represents the noise variance, * represents complex conjugation and |.| represents the absolute value. The channel response hl is determined by the channel estimator 8, 47 and corresponds to (or is at least part of) the channel estimation mentioned above. |hl|2 is the channel power and corresponds to the power (“signal power”) of the received signal (without noise components). The noise variance corresponds to the power (“noise power”) of noise in the received signal. There may be determined only one noise variance for all frequencies l. The noise variance is equivalent to the inverse value of the signal-to-noise ratio (SNR) (σn,l2=1/SNRl). As was described above, a LUT is used to determine the inverse of the divisor |hl|2+σn,l2 in order replace the division by a multiplication and reduce the complexity of calculation. However, because the dynamic range of (|hl|2+σn,l2)−1 for a wide range of noise variance and channel powers can be very large, a big LUT is needed.
The present invention proposes new and inventive implementations of the MMSE equalisation principle which reduces the size of the LUT and, generally, provides for a reduced complexity of the equaliser and receiver.
For the sake of brevity, the subscript l, denoting the carrier or frequency number, will be dropped in the following, but it must be understood that a separate equaliser is required and separate equalisation is carried out for each carrier or frequency l also in case of the present invention.
According to the present invention, the equaliser has a plurality of equaliser structures. In the following, embodiments with two or three equaliser structures are provided. According to the present invention, an equaliser structure is selected depending upon a channel power value. Hereby, at least one threshold value is used. The channel power value is an element of a range of possible channel power values. The one or more threshold values divide (separate) the range of possible channel power values into at least two (sub-)ranges. The one or more threshold values correspond to boundaries of the subranges. To each subrange corresponds one equaliser structure.
(2)
(3)
(4)
In Table 1, a three structure MMSE Equaliser according to a first embodiment of the equaliser according present invention is defined. The two threshold values (lower limit×σr2) and (upper limit×σn2) divide the possible range of channel power values |h|2 into the three ranges |h|2<(lower limit×σn2), (upper limit×σn2)≧|h|2≧(lower limit×σn2) and |h|2>(upper limit×σn2). In this first embodiment, a division operation is needed for each equaliser structure and, therefore, a LUT is required for each of the structures. The parameters lower limit and upper limit can be used to trade off performance with complexity.
An advantage of this three structure equaliser is that three smaller LUTs are needed rather than one large LUT.
When plotting the function y=l/x one sees that the graph is steep near the y-axis (x=0) and flat far from the y-axis. Thus, a small change in x amounts to a large variation in y when being close to the y-axis. Therefore, it is advantageous to provide LUTs with different quantization. A LUT has an input variable and an output variable. The LUT maps an input value to an output value. The input variable corresponds to the divisor of which the inverse value is to be looked-up. The inverse value corresponds to the output value. The term quantization as used in here refers to the quantization of the input variable. Of course, the quantization of the input variable influences the quantization (average step size) of the output variable. That is, a finer quantization of the input variable corresponds to a finer quantization (average step size) of the output variable. Advantageously, a LUT that corresponds to a smaller divisor has finer quantization (of the input variable) than a LUT that corresponds to a greater divisor. Hence, in the first embodiment of the equaliser 11, the LUT corresponding to equation (2) is quantized fine, the LUT corresponding to equation (4) is quantized coarse and the LUT corresponding to equation (3) has a quantization in between (middle quantization).
The number and size of the LUTs can be further reduced by setting σn2 to a fixed value denoted by NP. The fixed value may be chosen to be the minimum value, σn,min2, of the noise variance, that will presumably be encountered when operating the equaliser/receiver according to the present invention. This is equivalent to saying that the fixed value may be chosen to be the inverse of the maximum value, SNRmax, of the SNR that will presumably be encountered during the operation of the equaliser/receiver according to the present invention. Thus, for example, NP=σn,min2=1/SNRmax. The fixed value NP may be determined at the stage of development of the equaliser 11 or receiver 1, 41 and be preset (stored) in the equaliser 11 during production. Because, in this case, σn2 has not to be determined by the receiver 1, 41, the complexity of the receiver is reduced so that it can be produced at lower cost. At the time of the determination and storage of the fixed value NP also its inverse INP=1/NP may be determined and stored. Alternatively, the inverse value INP may be calculated from NP e.g. at start up or in an initialisation phase. Alternatively, INP may be stored and NP may be calculated from it. Applying this to the first embodiment, a second embodiment of the equaliser according to the present invention, corresponding to a sub-optimal three structure MMSE equaliser, is obtained. The suboptimal three structure MMSE equaliser is summarized in the following Table 2.
(6)
(7)
In this second embodiment of the equaliser 11, for the equalising structure described by equation (5) no division operation is needed and therefore no LUT is necessary. Furthermore, since NP is fixed, the dynamic range of the LUT needed for the evaluation of equation (6) is lower than the dynamic range of the LUT needed for the evaluation of equation (3), so the size of the LUT is reduced. Advantageously, the LUT used for evaluating the equation (6) has a different (finer) quantization than the LUT used for evaluating the equation (7).
For some applications it may be beneficial to merge the LUT tables needed for equations (6) and (7). This alternative two structure approach, corresponding to a third embodiment of the equaliser according to the present invention, is defined in the following Table 3.
(9)
The concepts described above can also be extended to MIMO, SIMO and MISO systems (MISO, SIMO and SISO systems may be seen as special cases of a general MIMO system).
The receiver 61 comprises an RF part 62 and a baseband part 63. The RF part 62 comprises two parallel RF parts 2 (as shown in
The transmitter 80 comprises a baseband part 81 and an RF part 82. An input data bit stream is split into two parallel data streams by a serial-to-parallel converter 83 of the baseband part 83. Each data stream is processed by a corresponding chain of a channel coding/modulation unit 53, IFFT 54, DAC/filtering unit 55 and up-conversion/PA unit 28 and, finally, is emitted (as a signal) by a corresponding antenna 29.
A conventional MMSE equaliser for a MIMO system with nR=1, 2, 3, . . . receive paths (e.g. receive antennas) and nT=1, 2, 3, . . . transmit paths (e.g. transmit antennas) (for true MIMO nR, nT≧2 holds) multiplies the equaliser matrix G (of size nR×nT) by the received symbol vector r (of size nR×1) for each carrier or frequency l. The equaliser matrix G is given by
G=(HhH+σn2I)−1HH, (10)
where H is a nR×nT matrix whose elements represent the channel response from the different transmit paths to the different receive paths, I is the nT×nT identity matrix, σn2 represents the noise variance, (·)H denotes the Hermitian transpose and (·)−1 denotes the inverse (inverse matrix). The channel matrix H (one for each carrier or frequency l) is determined by the channel estimator 67 as (at least part of) the channel estimation. HHH is a nT×nT channel power matrix HHH having elements corresponding to channel powers.
A two structure MIMO MMSE equaliser, corresponding to a fourth embodiment of equaliser according to the present invention, is defined in the following Table 4.
(11)
In the fourth embodiment, when all elements (channel powers) of the channel power matrix HHH are lower than lower limit×σn2 (e.g. lower than ⅕×σn2), the structure according to equation (11) is selected. This is equivalent to saying that, when the largest element of the channel power matrix is smaller than lower limit×σn2, the structure according to equation (11) is selected. For the evaluation of equation (11) only a LUT (for determining the inverse of σn2) but no matrix inversion is required. Forming the inverse matrix is a computationally very complex operation. Therefore a big advantage is gained.
A further reduction in complexity is obtained by using the suboptimal MMSE approach described above. A two structure suboptimal MMSE MIMO equaliser, corresponding to a fifth embodiment of the equaliser according to the present invention, is defined the following Table 5.
In this embodiment, there is neither required a matrix inversion nor a LUT for the evaluation of the equation (13).
The present invention can likewise be seen in a corresponding method of equalising 30 one or more received signals.
In step S2 a channel power value is determined based on one or more channel response values.
In a step S4, one of two or more equaliser structures is selected based on the channel power value. At least one of said equaliser structures corresponds to a minimum mean square error equaliser structure or a suboptimal minimum mean square error equaliser structure. In case the channel power value is below a first threshold, a first equaliser structure is selected in step S4 and in case the channel power value above said first threshold a second equaliser structure is selected in step S4.
In a step S6, a filter (i.e. filter defining information) is calculated according to the selected equaliser structure based on channel state information.
In a step S8, one or more received signals are filtered (equalised) according to the calculated filter. Since in step S6 the filter is calculated according to the selected equaliser structure, the one or more received signals are equalised according to the selected equaliser structure.
The steps of the method are carried out according to the principles described above in relation with said first to third embodiment of the communication device and said first to fifth embodiment of the equaliser.
The present invention has been described with reference to an OFDM multi-carrier communication system. The present invention, may however also be employed in relation with other MC communication techniques and variants of OFDM including, as a non limiting example, multi-carrier code division multiple access (CDMA), wavelet based multi-carrier techniques, OFDM-CDMA and other combinations and variations thereof.
The present invention has been described based on embodiments using single tap equalisers. Multiple tap equalisers however suffer from the same problems of high computational complexity due to divisions and matrix inversions (even a plurality of divisions and matrix inversions has to be carried out). Therefore, the present invention may be equally applied to multiple tap equalisers. For example, a multi tap SC/TDE equaliser/receiver may be realized using the present invention.
To implement the conventional MMSE equaliser, an estimate of the SNR is required. Using the suboptimal approach described above in relation with the second, third and fifth embodiment of the equaliser according to the present invention, only the communication channel has to be estimated but no estimate of the SNR is required, so that a SNR evaluation circuit/algorithm can be dispensed with.
It is noted, that for some receiver implementations (e.g. some OFDM receiver implementations) the division operations of equations 1-4, 6, 7, 9 and 11 can be performed as in internal scaling in the demodulator (e.g. the demodulator 13, 49) and, therefore, can be ignored in the equaliser block. In this case, the division operations performed in the demodulator can be implemented using a LUT in the same way as if they had been implemented in the equaliser. Such splitting of equaliser processing between the equaliser block and the demodulator is however not possible for an SC/FDE receiver (like e.g. the receiver 1 depicted in
It is noted that each of the receivers 1, 41, 61 can, for example, be part of a pure receiving device or can be part of a receiving and transmitting device. In the later case, the antenna 4 can be a receiving as well as a transmitting antenna. Also, each of the transmitters 20, 50, 80 can be part of a pure transmitting device or can be part of a transmitting and receiving device (e.g. said receiving and transmitting device). In the latter case, the antenna 29 may be a transmitting and receiving antenna (e.g. the antennas 4 and 29 may be the same entity).
| Number | Date | Country | Kind |
|---|---|---|---|
| 08 152 159.3 | Feb 2008 | EP | regional |
