Patent Application
20150161001
1. Field
This disclosure relates to data storage systems. More particularly, the disclosure relates to systems and methods for programming solid-state memory.
2. Description of Related Art
Certain solid-state memory devices, such as flash drives, store information in an array of memory cells constructed with floating gate transistors. Misprogramming of data in a solid-state memory cell may adversely affect device performance.
[3] Various embodiments are depicted in the accompanying drawings for illustrative purposes, and should in no way be interpreted as limiting the scope of this disclosure. In addition, various features of different disclosed embodiments can be combined to form additional embodiments, which are part of this disclosure.
While certain embodiments are described, these embodiments are presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the scope of protection. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.
As used in this application, “non-volatile solid-state memory,” “non-volatile memory,” “NVM,” or variations thereof may refer to solid-state memory such as NAND flash. However, the systems and methods of this disclosure may also be useful in more conventional hard drives and hybrid drives including both solid-state and hard drive components. Solid-state memory may comprise a wide variety of technologies, such as flash integrated circuits, Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory, NOR memory, EEPROM, Ferroelectric Memory (FeRAM), MRAM, or other discrete NVM (non-volatile solid-state memory) chips. The non-volatile solid-state memory arrays or storage devices may be physically divided into planes, blocks, pages, and sectors, as is known in the art. Other forms of storage (e.g., battery backed-up volatile DRAM or SRAM devices, magnetic disk drives, etc.) may additionally or alternatively be used.
The terms “page,” “target page,” or variations thereof are used herein according to their broad and ordinary meaning. For example, “page” may refer to a block of a physical memory cells, or to the physical memory cells themselves. Furthermore, within a multi-level cell (MLC), “page” may refer to either of upper or lower pages, which may in tern be associated with most significant bits (MSB), least significant bits (LSB), or other programming mechanism or scheme.
The terms “proto page,” “intermediate page,” “intermediate state,” “intermediate programming page,” “LSB proto page,” or variations/combinations thereof may refer to a voltage state or distribution corresponding to a partial programming of a cell, such as a lower page, or LSB, programming of a cell, wherein further programming of the cell(s) may be performed to program upper page, or MSB, data.
The present disclosure provides systems and methods for programming solid-state memory devices, wherein data associated with memory cells programmed to an intermediate programming state (e.g., an LSB proto state) is subjected to error correction in order to reduce occurrences of upper page misprogramming. In MLC solid-state memory, such as MLC NAND flash, as program/erase (P/E) cycles increase, misprogramming errors may increasingly occur when programming MSB pages. Such misprogramming errors may be caused by, for example, distribution widening of cells in a lowest state (e.g., erased state) after LSB page programming.
Certain MLC programming schemes involve multi-stage programming, wherein a first page, such as a lower page corresponding to a least significant bit (LSB), is programmed first, followed by programming of a second page, such as an upper page corresponding to a most significant bit (MSB). When executing the MSB page programming, it may be necessary or desirable to read out the programmed LSB page values to determine the final value at which the cells are to be programmed to achieve the correct MSB distribution. With increased P/E cycles, the upper side of the programmed LSB page corresponding to a lower or erased state can overlap the read level used to distinguish lower page values, thereby resulting in level misprogramming. For example, where states in an MLC distribution are defined from lowest voltage to highest voltage as L0-L3, L0 may be misprogrammed to L3 and L1 to L2. In certain embodiments, misprogrammed cells may increase with increased P/E cycles, and may reach up to 10% of the total errors, or more.
Misprogrammed cells can increase Raw Bit Error Rate (RBER) values, thereby adversely affecting device performance. Furthermore, it may not be possible or trivial to correct misprogrammed cells with read level adjustment or through multi-read soft decision input generation, which can further worsen the ability to perform error correction. Certain embodiments disclosed herein provide systems and methods for reducing misprogramming occurrences by performing error correction on LSB page data before using LSB values to program MSB pages. Systems and methods disclosed herein may be applicable in any multi-level NVM memory, such as MLC, three-level cell (TLC), or other multi-level programming scheme.
The data storage device 120 can store data received from the host system 110 such that the data storage device 120 acts as data storage for the host system 110. To facilitate this function, the controller 130 may implement a logical interface. The logical interface can present to the host system memory as a set of logical addresses (e.g., sequential/contiguous addresses) where data can be stored. Internally, the controller 130 can map logical addresses to various physical memory addresses in the non-volatile solid-state memory array 140 and/or other memory module(s). Mapping data indicating the mapping of logical addresses to physical memory addresses may be maintained in the data storage device. For example, mapping table data may be stored in non-volatile memory array(s) 140 in order to allow for recreation of mapping tables following a power cycle.
The controller 130 may include one or more memory modules (not shown), such as non-volatile memory (e.g., ROM) and/or volatile memory (e.g., RAM, such as DRAM). In certain embodiments, the controller 130 may be configured to store information, including, for example, operating system(s) code, application code, system tables and/or other data, in the non-volatile solid state memory array 140. On power-up, the controller 130 may be configured to load such data for use in operation of the data storage device.
The controller 130 may receive memory access commands from the host system, including programming commands, and implement such programming commands in the non-volatile memory array using a programming module 136. For example, the programming module 136 may implement a desirable programming scheme suitable for the non-volatile memory array. In certain embodiments, the programming module 136 is configured to implement a MLC programming scheme in which cells of solid-state memory are programmed to store a charge level representative of two or more bits of data. Such a programming scheme is described in further detail below with reference to
The controller 130 further includes an error correction (ECC) module 134 for controlling errors when decoding data read from the non-volatile memory array 140. The error correction module 134 may be configured to processes data read from the non-volatile memory array 140 including redundancy data and/or various quality metrics in order to increase the likelihood of accurately recovering the read data. The error correction module 134 may be configured to decode the read data using hard decoding and/or soft decoding. For example, the error correction module 134 may be configured to generate and/or receive soft-decision input, wherein the soft-decision input represents a probability that the detected data symbol was accurately detected. Such soft-decision data may include, for example, log likelihood ratio (LLR) values. The error correction module 134 may comprises a low-density parity-check (LDPC) decoder configured to correct data read from the non-volatile memory array based on LLR values.
In decoding memory cells, one or more reference voltage levels may be used to read the cells to determine what charge state the cells belong to.
Programming in an MLC programming scheme may be performed in multiple stages.
In certain embodiments, MLC programming comprises two steps: in a first step, as illustrated in
Following LSB programming, the MSB page may be programmed, as illustrated in
The programming scheme illustrated in
In order to determine how MSB programming is to be implemented on the programmed LSB page, it may be necessary or desirable for the programmed LSB data to be read out from the non-volatile memory array. For example, LSB data may be decoded by reading the LSB proto page at a reference voltage level (R-Low) positioned between the two LSB states. Details associated with the read-out of LSB data are described below in connection with
Because the programming of MSB pages can depend on the read-out LSB values, corrupted LSB values can lead to misprogramming of the MSB page.
As shown in
Certain embodiments disclosed herein provide for prevention of misprogramming in an MLC programming scheme based on performance of error correction with respect to programmed LSB data prior to MSB programming.
The process 600 may further include writing corrected LSB data to the non-volatile memory, such as to a reference buffer of the non-volatile memory for use in programming MSB page data. Performing error correction on LSB proto page data as shown in
When executing a write command in the non-volatile memory 745, the programming module 736 may be configured to write LSB data associated with the command to the non-volatile memory array. For example, the LSB data may be provided to, or otherwise received by, a data buffer 747 of the non-volatile memory 745. The non-volatile memory 745 may be configured to program the buffered data to a memory array 740 of the non-volatile memory. For example, the LSB data may be provided to programming hardware 748 of the non-volatile memory 745, which may be configured to write the data to the memory array 740. The programming module 736 may further provide MSB data associated with the programming command to the non-volatile memory 745 for programming therein.
In programming the MSB data, the non-volatile memory 745 may be configured to read out the previously-programmed LSB data from the array 740 to a data buffer 749 for reference in programming the MSB data. The buffer 749 may be separate from, or integrated with, the data buffer 747. The non-volatile memory 745 may be configured to use the buffered LSB data in combination with the MSB data from the controller 730 to program the MSB data to the array, as described above.
In certain embodiments, the error correction module may receive from the LSB data buffer 749 the read-out LSB data prior to programming of the MSB data in the array 740. For example, the non-volatile memory 745 may provide the LSB data to the controller 730, or the controller 730 may otherwise receive the LSB data. In certain embodiments, the error correction module 734 performs error correction on the LSB data and provides the corrected data to the non-volatile memory 745. For example, the corrected LSB data may be written to the buffer 749. In certain embodiments, the corrected data overwrites the read-out LSB data in the buffer 749. The non-volatile memory 745 may access the corrected LSB data as a reference for programming the MSB data in the array 740. In an embodiment, the MSB data and the corrected LSB proto page data may be combined and provided to the programming module 748.
The system 700 may provide for improved device performance based on reduced misprogramming errors, which may increase device lifetime and/or drive-writing capability. In certain embodiments, the LSB data error correction functionality described herein is performed by the non-volatile memory 745. For example, the non-volatile memory 745 may include an error correction module for performing LSB proto page error correction internally instead of, or in addition to, external LSB error correction.
Those skilled in the art will appreciate that in some embodiments, other types of data storage systems and/or programming schemes can be implemented. In addition, the actual steps taken in the processes discussed herein may differ from those described or shown in the figures. Depending on the embodiment, certain of the steps described above may be removed, others may be added. Furthermore, the steps of the various methods described herein may be performed in any suitable or desirable sequence.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the protection. For example, the various components illustrated in the figures may be implemented as software and/or firmware on a processor, ASIC/FPGA, or dedicated hardware. Also, the features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. Although the present disclosure provides certain preferred embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.
