Time interleaved (TI) analog-to-digital converters (ADC) sample input signals using multiple ADC units in a time-multiplexed fashion. TI ADCs are used in a broad variety of applications, including in high-end instrumentations, Radar and Lidar, and wireless infrastructure (e.g., 5G cellular towers).
Some embodiments relate to a time-interleaved (TI) analog-to-digital converter (ADC), comprising: an input terminal; a set of N paths electrically coupled to the input terminal, each path comprising a sampler configured to sample an input signal appearing at the input terminal, wherein N is a positive integer, wherein the N paths result in a phase oscillation of the input signal as appearing at the samplers, wherein the phase oscillation presents at most N phase values, and wherein the phase oscillation oscillates in accordance with a first periodicity; and control circuitry configured to control at least some of the N samplers to modify the phase oscillation of the input signal so that the modified phase oscillation presents more than N phase values, and the modified phase oscillation oscillates in accordance with a second periodicity greater than the first periodicity.
In some embodiments, controlling the at least some of the N samplers to modify the phase oscillation of the input signal comprises controlling the at least some of the N samplers so that: at a first oscillation cycle, the input signal as appearing at a first sampler of the N samplers presents a first phase value, and at a second oscillation cycle subsequent to the first oscillation cycle, the input signal as appearing at the first sampler of the N samplers presents a second phase value different from the first phase value.
In some embodiments, controlling at least some of the N samplers to modify the phase oscillation of the input signal further comprises controlling the at least some of the N samplers so that: at the first oscillation cycle, the input signal as appearing at a second sampler of the N samplers presents a third phase value, and at the second oscillation cycle, the input signal as appearing at the second sampler of the N samplers presents a fourth phase value different from the third phase value.
In some embodiments, a first sampler of the N samplers comprises P switches, wherein P is a positive integer, and wherein controlling the at least some of the N samplers to modify the phase oscillation of the input signal further comprises: at the first oscillation cycle, controlling the first sampler to maintain a first subset of the P switches active.
In some embodiments, controlling at least some of the N samplers to modify the phase oscillation of the input signal further comprises: at the second oscillation cycle, controlling the first sampler to maintain a second subset of the P switches active, the second subset being different from the first subset.
In some embodiments, the second periodicity is at least twice the first periodicity.
In some embodiments, controlling at least some of the N samplers to modify the phase oscillation of the input signal comprises performing a phase permutation of the phase oscillation.
In some embodiments, performing the phase permutation of the phase oscillation comprises performing the phase permutation of the phase oscillation in accordance with a prime number.
In some embodiments, performing the phase permutation of the phase oscillation comprises performing the phase permutation of the phase oscillation in accordance with a random or pseudo-random cadence.
In some embodiments, the control circuitry is configured to clock the N samplers so that each sampler samples the input signal appearing at the input terminal within a different time interval.
Some embodiments relate to a method for controlling a time-interleaved (TI) analog-to-digital converter (ADC), comprising: receiving an input signal at each path of a set of N paths electrically coupled to an input terminal, wherein N is a positive integer, each path comprising a sampler configured to sample the input signal, wherein the N paths result in a phase oscillation of the input signal as appearing at the samplers, wherein the phase oscillation presents at most N phase values, and wherein the phase oscillation oscillates in accordance with a first periodicity; sampling the input signal with each sampler of the N samplers; and controlling at least some of the N samplers to modify the phase oscillation of the input signal so that the modified phase oscillation presents more than N phase values, and the modified phase oscillation oscillates in accordance with a second periodicity greater than the first periodicity.
In some embodiments, controlling the at least some of the N samplers to modify the phase oscillation of the input signal comprises controlling the N samplers so that: at a first oscillation cycle, the input signal as appearing at a first sampler of the N samplers presents a first phase value, and at a second oscillation cycle subsequent to the first oscillation cycle, the input signal as appearing at the first sampler of the N samplers presents a second phase value different from the first phase value.
In some embodiments, controlling the at least some of the N samplers to modify the phase oscillation of the input signal further comprises controlling the N samplers so that: at the first oscillation cycle, the input signal as appearing at a second sampler of the N samplers presents a third phase value, and at the second oscillation cycle, the input signal as appearing at the second sampler of the N samplers presents a fourth phase value different from the third phase value.
In some embodiments, a first sampler of the N samplers comprises P switches, wherein P is a positive integer, and wherein controlling the at least some of the N samplers to modify the phase oscillation of the input signal further comprises: at the first oscillation cycle, controlling the first sampler to maintain a first subset of the P switches active.
In some embodiments, controlling the at least some of the N samplers to modify the phase oscillation of the input signal further comprises: at the second oscillation cycle, controlling the first sampler to maintain a second subset of the P switches active, the second subset being different from the first subset.
In some embodiments, the second periodicity is at least twice the first periodicity.
In some embodiments, controlling the at least some of the N samplers to modify the phase oscillation of the input signal comprises performing a phase permutation of the phase oscillation.
In some embodiments, performing the phase permutation of the phase oscillation comprises performing the phase permutation of the phase oscillation in accordance with a prime number.
In some embodiments, performing the phase permutation of the phase oscillation comprises performing the phase permutation of the phase oscillation in accordance with a random or pseudo-random cadence.
In some embodiments, sampling the input signal with each sampler of the N samplers comprises clocking the N samplers so that each sampler samples the input signal within a different time interval.
The foregoing summary is provided by way of illustration and is not intended to be limiting.
The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing.
The inventor has recognized and appreciated that time interleaved (TI) analog-to-digital converters (ADC) suffer from four types of mismatch—offset mismatch, gain mismatch, time skew mismatch and bandwidth mismatch. Collectively, these phenomena degrade the integrity of the output signal, and as a result, the performance of the TI ADC. The inventor has developed techniques for mitigating bandwidth mismatch, the type of mismatch that affects the integrity of the output signal the most in most circumstances.
Bandwidth mismatch occurs because the paths that connect the input terminal of a TI ADC to the various samplers present different time constants (e.g., RC). In some circumstances, the major contributor is the fact that the sampling switches present different values of resistance and/or capacitance. Bandwidth mismatch results in a phase oscillation across the input terminals of the samplers. The phase oscillation, in turn, gives rise to spurious tones in the spectral response of the converter that are substantially above the noise floor. The presence of these tones may be unacceptable in some contexts (e.g., in high-end instrumentations, Radar and Lidar, and wireless infrastructure).
The techniques developed by the inventor and described herein involve spreading the energy associated with the spurious tones across the frequency spectrum, thereby reducing the overall impact of individual tones. In some embodiments, for example, the tones may disappear under the noise floor. Spreading the energy associated with the spurious tones can be achieved by increasing the periodicity of the phase oscillation. This, in turn, can be achieved by introducing, in the phase oscillation, artificial phase shifts in addition to the phase shifts arising due to bandwidth mismatch. In one example, increasing the periodicity of a phase oscillation from 4 phase samples to 8 phase samples can result in a reduction in the power of a tone as high as 7 dB.
Bandwidth mismatch is a result of the fact that the paths that connect the input terminal of a TI ADC to the various samplers inevitably present different time constants.
Referring back to
The variations in resistance and capacitance described above are what causes bandwidth mismatch. As a result, each path exhibits a different frequency response to input signals.
The mismatch in the amplitude and phase responses associated with the different paths gives rise to a phase oscillation.
Described herein are techniques for mitigating bandwidth mismatch in TI ADCs. In some embodiments, this may be accomplished by spreading the energy associated with the spurious tones across the frequency spectrum. In this way, the overall impact of each individual tone is reduced substantially. In some embodiments, for example, the tones may disappear under the noise floor. Spreading the energy associated with the spurious tones can be achieved by increasing the periodicity of the phase oscillation discussed above. This, in turn, can be achieved by introducing artificial phase shifts in addition to the phase shifts arising due to bandwidth mismatch.
In one example, a TI ADC has a set of N paths electrically coupled to the input terminal (e.g., four paths in the example of
In some embodiments, increasing the periodicity of the phase oscillation from the first periodicity to the second periodicity can be accomplished by introducing additional capacitors in parallel to the capacitors Cs, and by varying the capacitances of these additional capacitors in accordance with random or pseudo random codes (thereby changing the time constant RC).
In some embodiments, the total sampling capacitance can be realized by shunting a main sampling capacitor (having capacitance of Cs−δC/2 (slightly smaller than the original Cs), with an additional small capacitor Cr the value of which is varied by the random digital code PN. Here, δC determines the desired range of capacitance variation. The nominal value of Cr can be made adjustable from 0 to δC. As result, the total value of the sampling capacitance can be varied between Cs−δC/2 and CS+δC/2.
In some embodiments, varying the capacitance of a sampler may involve providing a sampler with multiple capacitors, and activating only sub-sets of these capacitors in a randomized (or pseudo-randomized) fashion.
In some embodiments, varying the sampling capacitors results in an increase of the periodicity of the phase oscillation. An example of this result is depicted in
In another example, the sequence of phase values appearing at the samplers may be varied in accordance with permutations of prime numbers. For instance, the sequence may be altered every five samples (five is a prime number). The inventor has appreciated that by varying the phase sequence in accordance with permutations of prime numbers leads to larger periodicities. The result is that the energy of a spurious tone is spread to an even greater extent.
In yet another example, the sequence of phase values appearing at the samplers may be varied in accordance with a random or pseudo-random cadence. For instance, the sequence may be altered every five samples at one cycle, every three samples at the following cycle, every four samples at the following cycles, etc. The inventor has appreciated that by varying the phase sequence in accordance with a random or pseudo-random cadence leads to even larger periodicities than what is shown in the previous examples. The result is that the energy of a spurious tone is spread to an even greater extent.
Accordingly, some embodiments relate to a TI ADC including a set of N paths electrically coupled to an input terminal (e.g., terminal 104). Each path includes a sampler (e.g., sampler 106) configured to sample an input signal (e.g., Vin) appearing at the input terminal. Due to bandwidth mismatch, the N paths result in a phase oscillation of the input signal as appearing at the samplers, where the phase oscillation presents at most N phase values. For example, the phase oscillation may present four phase values or less where the TI ADC includes four paths as illustrated in the example of
In some embodiments, at a first oscillation cycle, the input signal as appearing at a first sampler of the N samplers presents a first phase value (e.g., Φ1 as shown at the bottom panel of
Further, in some embodiments, at the first oscillation cycle, the input signal as appearing at a second sampler of the N samplers presents a third phase value (e.g., Φ2 as shown at the bottom panel of
Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including”, “comprising”, “having”, “containing” or “involving” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
The use of “coupled” or “connected” is meant to refer to circuit elements, or signals, that are either directly linked to one another or through intermediate components.
The terms “approximately”, “substantially,” and “about” may be used to mean within ±10% of a target value in some embodiments. The terms “approximately” and “about” may include the target value.
This Application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 63/320,748, entitled “MITIGATION OF UNDESIRED SPECTRAL IMAGES DUE TO BANDWIDTH MISMATCH IN TIME-INTERLEAVED A/DS BY SAMPLING CAPACITANCE RANDOMIZATION” filed on Mar. 17, 2022, which is herein incorporated by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
6720900 | Matsumoto | Apr 2004 | B2 |
7015842 | Gupta | Mar 2006 | B1 |
7292170 | Kinyua | Nov 2007 | B2 |
8810442 | Zortea | Aug 2014 | B1 |
9680489 | Zortea | Jun 2017 | B2 |
9692436 | Zortea | Jun 2017 | B2 |
10341145 | Musah | Jul 2019 | B2 |
11082054 | Cascio | Aug 2021 | B1 |
20100226330 | Haque | Sep 2010 | A1 |
20120069884 | Sakurai | Mar 2012 | A1 |
20140152477 | Lewis | Jun 2014 | A1 |
20150349794 | Lin | Dec 2015 | A1 |
20170237419 | Clara | Aug 2017 | A1 |
20190131990 | Ali | May 2019 | A1 |
20210281271 | Bales | Sep 2021 | A1 |
20210359694 | Chen | Nov 2021 | A1 |
20210409035 | Lindholm | Dec 2021 | A1 |
20220131549 | Huang | Apr 2022 | A1 |
Number | Date | Country |
---|---|---|
I605688 | Nov 2017 | TW |
I672005 | Sep 2019 | TW |
202110100 | Mar 2021 | TW |
Entry |
---|
EP 23159788.1, Aug. 21, 2023, Extended European Search Report. |
Ali et al., A 12-b 18-GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration. IEEE Journal of Solid-State Circuits. Sep. 30, 2020;55(12):3210-24. |
Devarajan et al., A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology. IEEE Journal of Solid-State Circuits. Nov. 9, 2017;52(12):3204-18. |
Kurosawa et al., Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. Mar. 2001;48(3):261-71. |
Vogel et al., A review on low-complexity structures and algorithms for the correction of mismatch errors in time-interleaved ADCs. Invited Paper. 10th IEEE International NEWCAS Conference Jun. 17, 2012:349-52. |
Vogel et al., A flexible and scalable structure to compensate frequency response mismatches in time-interleaved ADCs. IEEE Transactions on Circuits and Systems I: Regular Papers. Feb. 18, 2009;56(11):2463-75. |
Extended European Search Report for European Application No. 23159788.1 dated Aug. 21, 2023. |
Park et al., A scalable bandwidth mismatch calibration technique for time-interleaved ADCs. IEEE Transactions on Circuits and Systems I: Regular Papers. Nov. 2016;63(11):1889-97. |
Number | Date | Country | |
---|---|---|---|
20230299784 A1 | Sep 2023 | US |
Number | Date | Country | |
---|---|---|---|
63320748 | Mar 2022 | US |