Patent Application
20070233955
This invention relates to bootable computer systems, and more particularly to booting from multiple types of memories.
Computers once required a complex series of steps to initialize and make them ready to run programs. Instructions for bootstrapping the computer were loaded into the computer after power-on, such as by manually toggling switches representing the 1's and 0's of bootstrap instructions on the front panel. The computer was brought from a dead state into a useful state, like lifting the computer up by its own bootstraps.
More recently, computers still execute a complex sequence of instructions after power-on to boot the computer and load its operating system (OS). The initial instructions may reside in a read-only memory (ROM), along with a personal computer's Basic Input-Output System (BIOS). The operating system such as Windows may be loaded from the hard disk, and when booting is complete the OS can execute user programs. Various system checks such as peripheral device and memory detection and sizing can be performed during booting.
Mass storage devices such as hard disks are being replaced or supplemented with solid-state mass storage such as flash memories. Flash memories use non-volatile memory cells such as electrically-erasable programmable read-only memory, (EEPROM), but are not randomly accessible at the byte level. Instead, whole pages or sectors of 512 bytes or more are read or written together as a single page. NAND flash memory is commonly used for data storage of blocks. Pages in the same block may have to be erased together, and limitations on writing may exist, such as only being allowed to write each page once between erases.
Program code is often stored in randomly-accessible memory such as a ROM or NOR flash memory. Since NOR flash memory is byte-addressable, NOR flash can store code that can be executed. Byte-addressing is needed to execute code, since branch and jump instructions may have a target that is at a random location that must be fetched next. The target may be byte-addressable. Since boot routines execute instructions one at a time, rather than a whole page at a time, randomly-accessible memory is needed for boot-code execution.
Small portable devices such as personal digital assistants (PDA), multi-function cell phones, digital cameras, music players, etc. have a central processing unit (CPU) or microcontroller that must be booted just as a PC or host CPU must be booted. These small devices are often quite cost and size sensitive. Having a NOR flash or ROM may increase the size and cost of these portable devices.
NAND flash memory is less expensive than NOR flash memory, and thus preferable from a cost standpoint. NAND flash memory may already be present on some devices such as cell phones or music players as the primary mass storage memory. It is thus desirable to use NAND flash memory to store boot code.
What is desired is a multi-bus-interface device that can access several different types of memory. It is desired to boot a processor inside the device using boot code that is stored in several of these different types of memory.
FIGS. 11A-B is a flowchart of booting a SD flash microcontroller from flash, SRAM, and DRAM.
The present invention relates to an improvement in multi-memory booting. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Boot code can reside in NOR flash memory 35 since memory interface 24 can read individual bytes or words from NOR flash memory 35. Words can be a few bytes, such as 4 bytes, 8 bytes, or 16 bytes. Words are much smaller than the 512-byte sectors or pages that are accessed by a mass-storage device.
SD flash microcontroller 100 can also read pages of data from flash memory 38. Flash interface 28 generates commands and transfers 512-byte blocks of data over flash bus 18 to flash memory 38.
SD flash microcontroller 100 may also connect to one or more removable Secure Digital (SD) cards or to a SD host on a SD bus. SD interface 26 generates and receives commands or clock signals on SD command bus 17, and transfers data packets over SD bus 16 to SD card 36.
A host such as a PC may connect to SD flash microcontroller 100 over SD bus 16, or over a separate host bus. Host interface 22 can connect directly to a host over a host bus. Host interface 22 is optional and not needed when the host connects over SD bus 16.
Memory interface 24 may have both a SRAM and a DRAM interface. Additional pulsed control signals such as RAS, CAS (not shown) may be used by memory interface 24 for accessing DRAM 39, and addresses may be multiplexed for row and column addresses. DRAM 39 allows for a much larger memory size at a lower cost than RAM 34. However, memory interface 24 must generate the additional DRAM control signals and ensure that DRAM 39 is refreshed, either using external refresh, or an internal refresh controller within DRAM 39.
Flash memory 38 can reside on flash bus 18 and connect directly to flash interface 28, or may reside on SD bus 16 as shown in
Internal bus 96 connects CPU 82 with RAM 86, FIFO data buffer 94, direct-memory access (DMA) engine 88, and flash-memory controller 90. CPU 82 executes instructions read from external RAM over memory data bus 14 through RAM interface 86, using cache 79 to cache instructions and/or data.
DMA engine 88 can be programmed to transfer data between FIFO data buffer 94 and flash-memory controller 90. CPU 82 can operate on or modify the data by reading the data over bus 96. Cache 79 and external RAM can store instructions for execution by the CPU and data operated on by the CPU.
SD transceiver 84 connects to the clock CLK and parallel data lines D0:3 of SD bus 16 and contains both a clocked receiver and a transmitter. An interrupt to CPU 82 can be generated when a new command is detected on SD bus 16. CPU 82 can then execute a routine to handle the interrupt and process the new command.
SD operating registers 80 include the protocol registers required by the SD specification. Registers may include a data-port, write-protect, flash select, flash status, interrupt, and identifier registers. Other extension registers may also be present.
Command decode and validator 89 detects, decodes, and validates commands received over SD bus 16. Valid commands may alter bus-cycle sequencing by bus state machine 83, and may cause response generator 87 to generate a response, such as an acknowledgement or other reply. Different routines can be executed by CPU 82 or different transfer lengths can be performed by DMA engine 88 in response to the byte or sector capacity detected by command decode and validator 89.
The transmit and receive data from SD engine 81 is stored in FIFO data buffer 94, perhaps before or after passing through a data-port register in SD operating registers 80. Commands and addresses from the SD transactions can also be stored in FIFO data buffer 94, to be read by CPU 82 to determine what operation to perform.
Flash-memory controller 90 includes flash data buffer 98, which may contain the commands, addresses, and data sent over internal flash bus 18 to one or more flash mass-storage chips. Data can be arranged in flash data buffer 98 to match the bus width of internal flash bus 18, such as in 32 or 94-bit words. DMA engine 88 can be programmed by CPU 82 to transfer a block of data between flash data buffer 98 and FIFO data buffer 94.
Flash control registers 93 may be used in conjunction with flash data buffer 98, or may be a part of flash memory buffer 98. Flash-specific registers in flash control registers 93 may include a data port register, interrupt, flash command and selection registers, flash-address and block-length registers, and cycle registers.
Error-corrector 92 can read parity or error-correction code (ECC) from flash mass storage chips and perform data corrections. The parity or ECC bits for data in flash data buffer 98 that is being written to flash mass storage chips can be generated by error-corrector 92.
Flash programming engine 97 can be a state machine that is activated on power-up reset. Flash programming engine 97 programs DMA engine 88 with the address of the boot loader code in the first page of the external flash mass-storage chip, and the first address in cache 79 or in another local RAM, or in external RAM through RAM interface 86. Then flash programming engine 97 commands DMA engine 88 to transfer the boot loader from the flash mass storage chip to cache 79 or the other small RAM, or to the external RAM. CPU 82 is then brought out of reset, executing the boot loader program starting from the first address in cache 79 or the small RAM. The boot loader program can contain instructions to move a larger control program from the flash mass storage chip to external RAM through RAM interface 86. Thus SD flash microcontroller 100 is booted without an internal ROM on internal bus 96.
The initial instructions from ROM 44 include a boot loader program that reads pages of data from flash memory 38. Firmware code 45 is read from flash memory 38 by flash interface 28 and sent over path B to be written into RAM 34, which can be the external RAM accessed through RAM interface 86 (
Once firmware code 45 is copied to RAM 34, the initial boot loader program executing on CPU 82 writes a control register in bus logic and registers 42 that toggles to a RAM_BASE mode. In the RAM_BASE mode, bus logic and registers 42 controls mux 40 to connect RAM 34 to CPU 82, rather than ROM 44. Instructions from the copy of firmware code 45 that was written to RAM 34 are now read directly by CPU 82 over path C. Further data can be read from flash memory 38 by CPU 82 until the OS is installed and can execute user programs.
In some embodiments, CPU 82 can read directly from either ROM 44 or from RAM 34 by changing the controls to mux 40. For example, a control register in bus logic and registers 42 can be written by CPU 82 to toggle between reading ROM 44 and RAM 34.
When the search of the flash was not successful and boot code was not found in flash, step 354, then the RAM_BASE bit is cleared. Mux 40 or other bus logic connects ROM 44 to CPU 82, and boot code is read from ROM 44 and executed, step 366.
When the search of the flash was successful and found boot code, step 354, then boot code is read from flash memory, step 356. This boot code is written to external RAM 34 through external RAM interface 86, or to a small boot RAM inside SD flash microcontroller 100. When this load from flash memory is not successful, step 358, then the RAM_BASE bit is cleared. Mux 40 or other bus logic connects ROM 44 to CPU 82, and boot code is read from ROM 44 and executed, step 366.
When this load from flash memory is successful, step 358, then the RAM_BASE bit is set to 1, step 360. This causes bus logic and registers 42 to control mux 40 to connect RAM 34 to CPU 82, rather than ROM 44. Bus logic and registers 42 generates a reset pulse, step 362, and after reset CPU 82 reads instructions from the first address in RAM 34, which is the boot loader code earlier read from flash memory in step 356. Boot code is read from RAM and executed, step 364. Once the OS is loaded, user programs or other applications can be executed.
NAND flash memory 50 stores initial boot loader 60 at the first page of the first block. Extended boot sequence 62 is stored after initial boot loader 60 in the other pages of the first block. Complete boot sequence 64 is stored in the next block. OS image 66 is stored next, after complete boot sequence 64.
User data 54 is the main user or application data stored by flash memory 50. Unused user storage 52 is available for new data.
Small RAM 70 is also volatile, losing data when power is lost. Flash memory 50 is non-volatile, retaining data such as boot code. However, code cannot be executed directly from flash memory 50, since flash memory 50 is block-addressable. A whole page must be read from flash memory 50, rather than individual cache lines or instructions.
After reset, a state machine or other hardware in SD flash microcontroller 100 reads the first page of the first block of flash memory 50. This first page contains initial boot loader 60, which is written by the hardware state machine into small RAM 70. Initial boot loader 60 may occupy the entire 512-byte first page, or just part of the first page, or multiple pages.
After loading initial boot loader 60 into small RAM 70, the CPU exits reset and begins fetching instructions from the first address in small RAM 70. Initial boot loader copy 60′ is located there, causing initial boot loader copy 60′ to be executed directly by the CPU. Initial boot loader copy 60′ contains CPU instructions that cause the CPU to read the remaining pages in the first block of flash memory 50. These pages contain extended boot sequence 62. The remaining area of small RAM 70 is used as temporary buffer 71 to store pages of extended boot sequence 62 as they are copied to DRAM 72 and stored as extended boot sequence copy 62′.
Once all pages of extended boot sequence 62 have been copied to DRAM 72, then the CPU writes to registers in bus logic and registers 42 to alter bus muxing. Rather than read instructions from small RAM 70, the CPU reads instructions from DRAM 72, such as through a DRAM interface. The CPU may be reset to cause it to again fetch instructions from address 0, which is now the first address in DRAM 72.
Instructions from extended boot sequence copy 62′ are now read and executed by the CPU. These instructions include routines to read complete boot sequence 64 from the next block of flash memory 50, and to write these instructions to DRAM 72 as complete boot sequence copy 64′. As the last instruction of extended boot sequence copy 62′ is executed, the next instruction fetched is from complete boot sequence copy 64′, either fetching sequentially or by a jump or branch.
Complete boot sequence copy 64′ is then executed by the CPU. Complete boot sequence 64 includes instructions to read OS image 66 from flash memory 50, and to write it to DRAM 72 as OS image copy 66′. As the last instruction of Complete boot sequence copy 64′ is executed, the next instruction fetched is from OS image copy 66′, either fetching sequentially or by a jump or branch. After the OS starts, user or application programs may be loaded and executed.
FIGS. 11A-B is a flowchart of booting a SD flash microcontroller from flash, SRAM, and DRAM. In
This first page in flash contains initial boot loader 60. Initial boot loader 60 is written into small RAM 70, step 304. The CPU is then activated, such as by bringing the CPU out of reset, and begins fetching and executing instructions from address 0 in the small RAM. The initial boot loader was written to these first addresses in the small RAM in step 304, so the initial boot loader is executed from the small RAM, step 306.
As the initial boot loader is executed by the CPU from the small RAM, the next page in the flash memory is read and this next page is written to a buffer area of the small RAM, step 310. The small RAM can be 2 or more pages in size, such as 1K bytes. The next page from flash is then copied from the buffer area of the small RAM to the DRAM, starting at address 0 in the DRAM, step 312.
Steps 310, 312 are repeated when there are more pages of extended boot sequence 62 to fetch from the flash memory, step 314. When all pages of extended boot sequence 62 have been copied, step 314, then extended boot sequence 62 is executed from the first address in the DRAM, step 316. The CPU may write a register in bus logic and registers 42 such as a RAM_BASE bit to cause the CPU to fetch from DRAM rather than the small RAM. Then the CPU may be reset to begin fetching from DRAM.
In
Pages in the buffer area of the small RAM may be over-written with new pages once the older pages have been copied to DRAM. A verification process may also be performed after each page is copied, or a checksum may be calculated and compared to a stored checksum.
When more pages of complete boot sequence 64 still remain to be fetched, step 324, then steps 320, 322 are repeated until all pages in complete boot sequence 64 have been copied to DRAM. Then the complete boot sequence can be executed from DRAM, such as by jumping from an instruction in the extended boot sequence to an instruction in the complete boot sequence, or by fetching sequentially across the boundary in DRAM between extended boot sequence 62 and complete boot sequence 64. Since both are in DRAM, a reset is not needed.
As complete boot sequence 64 is executed from DRAM, step 326, pages in flash memory continue to be read that contain OS image 66. These pages may be in several consecutive blocks of flash memory. Each page of OS image 66 is read from the flash memory and written to the buffer area of the small RAM, step 330, and then copied from the buffer area to the next available page in DRAM, step 332. Additional pages are fetched by repeating steps 330, 332, until all pages of OS image 66 have been copied to DRAM, step 334. Then execution transfers from complete boot sequence 64 to OS image 66, such as by a jump instruction being executed by complete boot sequence 64 that has a target in OS image 66, step 336. Application and user programs may then be loaded and executed by the OS.
The buffer area of the small RAM could be expanded to include the area in small RAM 70 that was occupied by initial boot loader 60 after initial boot loader 60 has finished execution. This can allow 2 or more pages to be transferred in each step rather than just one page. Also, the size of the buffer area may be large enough for several pages to be transferred together, possibly improving performance.
Several other embodiments are contemplated by the inventors. For example different numbers and arrangements of flash, RAM, and SD cards or SD hosts can connect to the controller. Rather than use SD buses, other buses may be used such as Memory Stick, PCI Express bus, Compact Flash (CF), IDE bus, Serial ATA (SATA) bus, etc. Additional pins can be added or substituted for the SD data pins. A multi-bus-protocol chip could have an additional personality pin to select which bus interface to use, or could have programmable registers. Rather than have a SD microcontroller, a Memory Stick microcontroller could be substituted, for use with a memory-stick interface, etc.
Rather than write extended boot sequence 62 to address 0 in the DRAM, it can be written to another address in DRAM when the CPU can be configured to execute from an address other than address 0. Likewise, the first address fetched and executed in small RAM 70 may not be address 0.
While a page size of 512 bytes has been described, other pages sizes could be substituted, such as 1K, 2K, 4K, etc. Flash blocks may have 4 pages, 8 pages, 64 pages, or some other number, depending on the physical flash chips and arrangement used.
While the invention has been described using an SD controller, a MMC controller may be substituted. A combined controller that can function for both MMC and SD may also be substituted. SD may be considered an extension of MMC, or a particular type of MMC, rather than a separate type of bus.
While the invention has been described as not requiring ROM for booting, some ROM may still be present on the chip. For example, a revision number may be included in a small ROM. Hard-wired gates that are tied to power or ground may also function as a read-only memory. While such ROM may be present, ROM is not required for storing boot code or booting instructions. A few bytes or more of ROM may be thus present for other purposes.
Mode logic could sense the state of a pin only at power-on rather than sense the state of a dedicated pin. A certain combination or sequence of states of pins could be used to initiate a mode change, or an internal register such as a configuration register could set the mode.
The microcontroller and SD components such as the bus interface, DMA, flash-memory controller, transaction manager, and other controllers and functions can be implemented in a variety of ways. Functions can be programmed and executed by the CPU or other processor, or can be implemented in dedicated hardware, firmware, or in some combination. Many partitioning of the functions can be substituted.
Data and commands may be routed in a variety of ways, such as through data-port registers, FIFO or other buffers, the CPU's registers and buffers, DMA registers and buffers, and flash registers and buffers. Some buffers may be bypassed or eliminated while others are used or present. Virtual or logical buffers rather than physical ones may also be used. Data may be formatted in a wide variety of ways.
The host can transfer standard SD commands and data transactions to the SD transceiver during a transaction. Other transaction types or variations of these types can be defined for special purposes. These transactions may include a flash-controller-request, a flash-controller-reply, a boot-loader-request, a boot-loader-reply, a control-program-request, a control-program-reply, a flash-memory-request, and a flash-memory-reply. The flash-memory request/reply may further include the following request/reply pairs: flash ID, read, write, erase, copy-back, reset, page-write, cache-write and read-status.
The host may be a personal computer (PC), a portable computing device, a digital camera, a phone, a personal digital assistant (PDA), or other electronic device. The small RAM could be internal to SD flash microcontroller 100 or could be external. ROM 44 in
Wider or narrower data buses and flash-memory blocks could be substituted, such as 4, 5, 8, 16, 32, 64, 128, 256-bit, or some other width data channels. Alternate bus architectures with nested or segmented buses could be used internal or external to the microcontroller. Two or more internal and flash buses can be used in the SD flash microcontroller to increase throughput. More complex switch fabrics can be substituted for the internal buses.
The flash mass storage chips or blocks can be constructed from any flash technology including multi-level-logic (MLC) memory cells. Data striping could be used with the flash mass storage blocks in a variety of ways, as can parity and error-correction code (ECC). Data re-ordering can be adjusted depending on the data arrangement used to prevent re-ordering for overlapping memory locations. An SD/MMC switch could be integrated with other components or could be a stand-alone chip. The SD/MMC switch could also be integrated with the SD single-chip flash device. While a single-chip device has been described, separate packaged chips or die may be stacked together while sharing I/O pins, or modules may be used.
Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
This application is a continuation-in-part of the co-pending application for “Electronic Data Storage Medium with Fingerprint Verification Capability”, U.S. Ser. No. 09/478,720, filed Jan. 6, 2000. This application is also a CIP of “Flash Memory Controller for Electronic Data Flash Card”, U.S. Ser. No. 11/466,759, filed Aug. 23, 2006, which is a CIP of “System and Method for Controlling Flash Memory”, U.S. Ser. No. 10/789,333, filed Feb. 26, 2004, now abandoned. This application is related to “Flash drive/reader with serial-port controller and flash-memory controller mastering a second RAM-buffer bus parallel to a CPU bus”, U.S. Ser. No. 10/605,140, filed Sep. 10, 2003, now U.S. Pat. No. 6,874,044.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09478720 | Jan 2000 | US |
| Child | 11679716 | Feb 2007 | US |
| Parent | 11466759 | Aug 2006 | US |
| Child | 11679716 | Feb 2007 | US |
| Parent | 10789333 | Feb 2004 | US |
| Child | 11679716 | Feb 2007 | US |
