The present invention generally relates to integrated circuits, and more particularly to a mixer having up/down phase control, and systems and methods utilizing such a mixer. In one embodiment, the present invention provides a system and method for clock extraction from serial data.
A mixer is generally used to combine two or more input signals to form a single output signal. These input signals can differ in frequency and phase, or in phase only. By selectively weighting the combination of these input signals, and in some cases varying those weights in time, a useful and complex output signal can be generated. A mixer with multiple inputs of equal frequency and distributed phase can generate an output signal of a similar frequency and of any phase through the selective weighting of each mixer input. To form a clock recovery system, it is desirable to have a mixer where the selective weighting of the mixer inputs can be directly controlled by a traditional data phase detector and its UP/DOWN logic outputs.
According to one aspect of the invention, a phase control circuit includes a signal generator sub-circuit that generates a set of phase reference signals having phase angles generally distributed over a phase angle adjustment range. A mixer sub-circuit is coupled to the set of phase reference signals and to weighting signals that collectively control a mix of the phase reference signals. The mixer sub-circuit is adapted to produce an output signal having a phase angle that is based on the mix of the phase reference signals. The phase control circuit further includes a controller sub-circuit that produces the weighting signals, and includes at least one adjustment input. The controller sub-circuit is adapted to maintain the weighing signals in a generally steady state when receiving signaling on the adjustment input that represents no adjustment, and to adjust relative intensities of the weighting signals based on stimulation of the adjustment input.
According to another aspect of the invention, a mixer control circuit includes an arrayed set of control signal driver elements, each element having a set of at least one UP/DOWN input that receives UPI/DOWN signaling common to all array elements, a feedback loop that receives a feedback signal common to all array elements representing at least an aggregation of control signal outputs of the array elements, a set of at least one control signal input that receives control signal outputs from other elements of the array, and a set of at least one control signal output that produces at least one control signal. The at least one control signal is produced such that an aggregation of the control signals of the array is proportional to a reference amplitude signal according to a first ratio. Also, a control signal having the highest amplitude among the control signals of the array is proportional to the reference amplitude signal according to a second ratio. Furthermore, a signal pulse on the at least one UP/DOWN input affects relative amplitudes of the control signals driven by the array elements.
A method of recovering a clock from a high-speed serial data transmission according to another aspect of the invention includes generating a plurality of phase reference signals, and controlling an amplitude of each of the phase reference signals to assign a relative weight to each of the phase reference signals. The controlling includes generating a plurality of amplitude control signals corresponding to the plurality of phase reference signals; stabilizing relative and absolute amplitudes of the amplitude control signals to maintain steady state in an absence of a change in input signal; inter-relating the amplitude control signals such that a change in any one amplitude control signal propagates to effect changes in the other amplitude control signals; mixing the weighted phase reference signals to produce a local clock signal having a desired phase angle; and providing an input signal representing a comparison between the local clock signal and the serial data transmission.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
One aspect of the present invention is directed to a signal mixer in which the selective weighting of each mixer input is controlled by incremental up/down adjustment. To form a clock recovery loop in one application, the mixer output can be coupled to the clock input of a data phase detector, while the data phase detector output is coupled to the up and down inputs of the mixer. The clock recovery loop controls the phase and therefore the frequency of the mixer output such that these are matched, or locked, to the incoming serial data.
In a related embodiment, the selective weights applied to each mixer input are controlled by multiple up inputs and multiple down inputs. Certain specialized data phase detectors use multiple phase sampling methods and will generate multiple up and down output signals. This embodiment is intended to couple to this specialized type of data phase detector.
One embodiment of the invention is a mixer comprising multiple mixer buffer cells whose outputs are coupled together; a common-mode feedback loop, ensuring that the net strength of the mixer buffer cells results in a mixer bandwidth that substantially matches the frequency of the signal being mixed; and a control loop which in steady-state results in a specific subset of the mixer buffer cells having a substantially high drive strength, with the remainder having a substantially low drive strength. The mixer buffer cell may further comprise a signal input, a signal output, and one or more additional inputs for controlling its output drive strength. Likewise, in the common-mode feedback loop the frequency of the signal being mixed may be converted to a voltage by means of a delay-locked loop, and this voltage may be used to control the mixer bandwidth. The control loop may further comprise control inputs
In another embodiment, the invention includes a mixer comprising a mixer similar to the mixer described above and additional
Another embodiment of the invention comprises a single-phase clock recovery system including: a data phase detector; a multi-phase clock generator; and a mixer similar to that described above coupled to the data phase detector and the multi-phase clock generator. One embodiment is a multi-phase clock recovery system comprising a multi-phase data phase detector; a multi-phase clock generator; a second multi-phase clock generator; and a mixer similar to that set forth above, coupled to the data phase detector and the multi-phase clock generators.
Also shown in
Referring again to
In addition to the conmon-mode feedback loop, there is a second loop which controls the voltage relationship between each element in BIASN[0:4]. The BIASPUP and BIASPDOWN inputs of each mixer control subcircuit are connected to the BIASP outputs of an adjacent mixer control subcircuit as follows: BIASPUP[N] is coupled to BIASP[N−1], and BIASPDOWN[N] is coupled to BLASP[N+1], for N=0, 1, 2, 3, 4 (where N+1=5, use 0). With both loops operational,
b illustrates the state of VBIASN[0:4] after pulsing
Note that each of the 3 states in
Also note that this disclosure shows the mixing of P phases where P=5, though any number P≧3 can be used.
Also note that a reset or startup circuit is helpful to pull the circuit out of the undesirable state when VBIASN[0:4] all equal 0. The RESET circuit in
This new mixer is used in an alternate clock recovery system, illustrated in
Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. Those with skill in the chemical, mechanical, electro-mechanical, electrical, and computer arts will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein.
Number | Name | Date | Kind |
---|---|---|---|
4277754 | Minakuchi | Jul 1981 | A |
4922141 | Lofgren et al. | May 1990 | A |
5638014 | Kurita | Jun 1997 | A |
5815041 | Lee et al. | Sep 1998 | A |
5825210 | Oh | Oct 1998 | A |
5901184 | Ben-Efraim et al. | May 1999 | A |
5999793 | Ben-Efraim et al. | Dec 1999 | A |
6078200 | Miyano | Jun 2000 | A |
6091931 | Ben-Efraim et al. | Jul 2000 | A |
6194929 | Drost et al. | Feb 2001 | B1 |
6259295 | Kriz et al. | Jul 2001 | B1 |
6504438 | Chang et al. | Jan 2003 | B1 |
6586977 | Yang et al. | Jul 2003 | B2 |
6657466 | Sudjian | Dec 2003 | B1 |
6670833 | Kurd et al. | Dec 2003 | B2 |
6774689 | Sudjian | Aug 2004 | B1 |
6961546 | Rofougaran et al. | Nov 2005 | B1 |
6965259 | Saeki | Nov 2005 | B2 |
7009441 | Fiedler | Mar 2006 | B2 |
7075353 | Wan et al. | Jul 2006 | B1 |
7437137 | Fiedler | Oct 2008 | B2 |
20040160265 | Fiedler | Aug 2004 | A1 |
20050073369 | Balboni et al. | Apr 2005 | A1 |
20050221785 | Fiedler | Oct 2005 | A1 |
20060014510 | Yamamoto et al. | Jan 2006 | A1 |
20060084386 | Irie et al. | Apr 2006 | A1 |
Number | Date | Country |
---|---|---|
WO 2005034356 | Apr 2005 | WO |
Number | Date | Country | |
---|---|---|---|
20070230618 A1 | Oct 2007 | US |