(i) Technical Field
The present invention relates to mixers.
(ii) Related Art
Recently, mobile communication devices such as cellular phones have been utilized. In radio communications, an intermediate frequency (IF) signal and a local (LO) signal are mixed with each other to generate a radio frequency (RF) signal. Japanese Patent Application Publication No. 2007-251989 discloses an art of mixing two signals to eliminate unwanted frequency components.
According to an aspect of the present invention, there is provided a mixer including: a first node to which an intermediate frequency (IF) signal is input; first and second transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the first node; a first filter that is connected between the output terminal of the second transistor and the first node and suppresses passage of the IF signal; a second node to which the IF signal is input; third and fourth transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the second node; a second filter that is connected between the output terminal of the fourth transistor and the second node and suppresses passage of the IF signal; and a combiner combining a signal output from the first node and a signal output from the second node.
According to another aspect of the present invention, there is provided a mixer including: a node to which an intermediate frequency (IF) signal is input; first and second transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the node; and a filter that is connected between the output terminal of the second transistor and the node and suppresses passage of the IF signal.
Exemplary embodiments of the present invention are now described.
A received signal is input to the input terminal RFIn1, and a LO signal is input to the input terminal LOIn1, and an IF signal is input to the input terminal IFIn1. The LO signal is output from a local oscillator (not illustrated). The mixer 10 mixes the received signal with the LO signal for down-conversion of the received signal. The received signal is output via the output terminal IFOut1. The mixer 20 mixes the IF signal with the LO signal for up-conversion of the IF signal, and thus generates a transmitted signal. The transmitted signal thus generated is output via the output terminal RFOut1. The mixer 20, the amplifier 22, the attenuator 24, the LPF 32, the frequency multiplier 34 and the amplifier 36 form an RF integrated circuit (RFIC) 11 including an up-converter (mixer 20).
A circuit 41 includes a balun 40, a pair of field effect transistors (FETs) 44 and 46 (first and second transistors), capacitors C1˜C3 and an inductor L1. The input terminal LOIn2 is electrically connected to the input terminals of baluns 40 and 42 (unbalanced terminals). One of the two output terminals of the balun 40 (balanced terminals) is electrically connected to a gate (control terminal) of FET 44, and the other is electrically connected to the gate of FET 46. The sources of FETs 44 and 46 are grounded. The drain (output terminal) of FET 44 and the drain of FET 46 are electrically interconnected. A capacitor C1 (first filter) is connected in series between the drains of FETs 44 and 46. One end of a capacitor C2 is electrically connected to a node N1 (first node) interposed between one end of the capacitor C1 and the drain of FET 44. The other end of the capacitor C2 is electrically connected to one of two input terminals of a 90° coupler 48. One end of the inductor L1 is electrically connected to a node at which the node N1 and the capacitor C2 are interconnected. The other end of the inductor L1 is electrically connected to one end of the capacitor C3, and the other end thereof is grounded. A node N2 between the inductor L1 and the capacitor C3 is electrically connected to one of two output terminals of a 90° coupler 50.
A circuit 43 includes the balun 42, a pair of FETs 52 and 54 (third and fourth transistors), capacitors C4˜C6, and an inductor L2. The circuit 43 is connected in a manner similar to that of the circuit 41. A node N3 (second node) is defined as a node at which the drain of the FET 52 and one end of the capacitor C4 (second filter) are interconnected. The capacitor C5 is connected to the other input terminal of the 90° coupler 48. A node N4 between the inductor L2 and the capacitor C6 is connected to the other output terminal of the 90° coupler 50. One of the two output terminals of the 90° coupler 48 is connected to the output terminal RFOut2, and the other output terminal is grounded through a resistor R1. One of the two input terminals of the coupler 50 is connected to the input terminal IFIn2, and the other input terminal is grounded through a resistor R2. A circuit composed of the inductor L1 and the capacitor C3, and a circuit composed of the inductor L2 and the capacitor C6 function as filters (third and fourth filters) that introduce the generated RF signals to the output terminal RFOut2 and suppress passage of the IF signals. The input terminal LOIn2 branches into two lines at a node N10. The branch at the node N10 is a simple branch, and the impedance viewed from the LOIn2 side is equal to the impedances of the control terminals of the pair of FETs 44 and 46 and those of the control terminals of the pair of FETs 52 and 54. Thus, the LO signal does not have any considerable difficulty in inputting.
The input and output signals of the mixer 20 are now described. The LO signal is input to the baluns 40 and 42, and the IF signal is input to the nodes N2 and N4. The baluns 40 and 42 output the respective LO signals that are 180° out of phase. The LO signals input to FETs 46 and 54 are 180° out of phase with the LO signals input to FETs 44 and 52. The 90° coupler 50 outputs the IF signals that are 90° out of phase with each other. The IF signal input to the node N4 is 90° out of phase with the IF signal input to the node N2. The 90° coupler 48 functions as a combiner, which makes a 90° phase difference between the output signal of the node N1 and that of the node N3 and combines the output signals with each other. More specifically, the 90° coupler 48 delays the phase of the signal from the node N3 by 90°, and combines the delayed signal with the output signal of the node N1. The output of the 90° coupler 48 is an RF signal. The term “combine” means adding the signals together.
The frequency characteristics of the capacitors C1 and C4 illustrated in
As illustrated in
Table 1 describes exemplary signals in the mixer 20.
In Table 1, the signals related to the transistors are those at the drains thereof. The parameters in parentheses express the phases at the same time. For example, LO(ωLO) denotes the LO signal having a phase of ωLO, and LO(ωLO+π) denotes the LO signal having a phase of ωLO+π.
The signals LO(ωLO), IF(ωIF), RF(ωLO−ωIF), Im(ωLO+ωIF) are output from the drain of FET 44. The signal LO (ωLO+π) is output from the drain of FET 46. As described above, since the capacitor C1 suppress passage of the IF signal, the RF signal and Im signal are not output. Since the balun 40 delays the phase of the LO signal by 180° (π), the LO signal input to the control terminal of FET 46 is 180° out of phase with the LO signal input to the control terminal of FET 44. Similarly, the LO signal that leaks to the drain terminal from the control terminal of FET 46 is 180° out of phase with the LO signal that leaks to the drain terminal of FET 44 from the control terminal thereof. The output signals from FETs 44 and 46 are combined at the node N1. The LO signals that have opposite phases (180° out of phase with each other) are mutually canceled at the common drain terminals of FETs 44 and 46 and parts of the RF signal, Im signal and IF signal are output.
From the drain of FET 52, outputs are the LO signal LO(ωLO), IF(ωIF+π/2), RF(ωLO−ωIF−π/2) and Im(ωLO+ωIF+π/2). The LO signal LO(ωLO+π) is output from the drain of FET 54. At the node N3, the LO signals are mutually canceled and parts of the RF signal, the Im signal and the IF signal are output. The 90° coupler 50 delays the phase of the IF signal by π/2. Thus, the phases of the IF signal, the RF signal and the Im signal are π/2 out of phase with the corresponding signals at the node N1.
The 90° coupler 48 delays the phases of the signals output from the node N3 by π/2. At the node N3, the phase of the IF signal has a phase of ωIF+π, the RF signal has a phase of ωLO−ωIF, and the Im signal has a phase of ωLO+ωIF+π. Further, the 90° coupler 48 combines the output signals of the node N1 and the output signals of the node N3. The Im signal Im(ωLO+ωIF) and the Im signal Im(ωLO+ωIF+π) are 180° out of phase with each other, and are mutually canceled. In contrast, the two RF signals are in phase, and are added. Thus, as illustrated in
According to the first embodiment, the RF signals and the Im signals are generated at FETs 44 and 52. The LO signals that are 180° out of phase with each other are mutually canceled at the nodes N1 and N3. The 90° coupler 50 makes a phase difference of π/2 between the two IF signals. The 90° coupler 48 makes a 90° phase difference between the two output signals and combines these signals with each other. Thus, the leakage of the LO signal is suppressed, and the passage of the Im signal is suppressed, while only the RF signal is output.
The frequency characteristic of the mixer 20 is simulated. In the simulation, calculated are the RF signal, the Im signal, the LO signal that leaks to the output terminal RFOut2 (LO leakage on the RF side), the IF signal (IF leakage on the RF side), and the LO signal that leaks to the input terminal IFIn2 (LO leakage on the IF side). The FETs 44, 46, 52 and 54 are HEMTs (High Electron Mobility Transistors) having electron supply layers of aluminum gallium arsenide (AlGaAs) and channel layers of indium gallium arsenide (InGaAs). The frequency ωIF of the IF signal is 1 GHz, and the frequency ωLO of the LO signal is 8˜32 GHz.
Comparative examples are now described. A first comparative example uses a pair of transistors.
As illustrated in
The LO signal is input to one of the two inputs of the 90° coupler 60. The 90° coupler 60 shifts the phase of the LO signal by 90°, and then applies the LO signal to the gate of FET 44. Further, the 90° coupler 60 outputs the LO signal to the gate of FET 46 without any phase shift. The balun 62 applies the IF signal that has been phase-shifted by 90° to the FET 44, and applies the IF signal to FET 46 without any phase shift. As shown in Table 2, FET 44 outputs the LO signal LO(ωLO+π/2), the IF signal IF(ωIF+π), the RF signal RF(ωLO−ωIF−π/2), and the Im signal Im(ωLO+ωIF+3π/2). Further, FET 46 outputs the LO signal LO(ωLO), the IF signal IF(ωIF), the RF signal RF(ωLO−ωIF), and the Im signal Im(ωLO+ωIF). The 90° coupler 48 shifts the phase of the output signal of FET 44 by 90°, and combines it with the output signal of the FET 46. The two LO signals are 180° out of phase with each other, and are mutually canceled. The RF signal and the Im signal are in phase with each other, and are added. Thus, as illustrated in
A second comparative example uses two pairs of transistors.
Table 3 describes exemplary signals in the mixer 20R2.
As described in Table 3, the FET 44 outputs the LO signal LO(ωLO), the IF signal IF(ωIF), the RF signal RF(ωLO−ωIF), and the Im signal Im(ωLO+ωIF). The FET 46 outputs the LO signal LO(ωLO+π), the IF signal IF(ωIF), the RF signal RF(ωLO−ωIF+π), the Im signal Im(ωLO+ωIF+π). The LO signals are 180° out of phase with each other, and are mutually canceled. The RF signals are 180° out of phase with each other, and are mutually canceled. The Im signals are 180° out of phase with each other, and are mutually canceled. The IF signal IF (ωIF) are output from the node N1. Similarly, out of the signals output from FETs 52 and 54, the LO signals, the RF signals and the Im signals are 180° out of phase and are mutually canceled. Thus, only the IF signal IF(ωIF+π/2) are output. The passage of the IF signal is suppressed by the capacitors C2 and C5. Further, the IF signal is out of the band of the 90° coupler 48 and is not output. As illustrated in
A mixer chip 21 is now described. The mixer chip 21 is used to form the mixer 20.
As illustrated in
A second embodiment 2 has an exemplary structure in which a changed number of baluns is used.
Referring to
A third embodiment has an exemplary structure in which the position of the capacitor C4 is changed.
Table 4 describes exemplary signals in the mixer 20B. In the third embodiment, it is assumed that the frequency of the RF signal is the sum of the frequency of the LO signal and that of the IF signal, and the frequency of the Im signal is the result of subtracting the frequency of the Im signal from that of the LO signal.
As described in Table 4, the IF signal IF(ωIF), the RF signal RF(ωLO+ωIF), and the Im signal Im(ωLO−ωIF) are output from the node N1. The LO signal LO(ωLO) is output from the drain of FET 52. From the drain of FET 54, output are the LO signal LO (ωLO+π), the IF signal IF (ωIF+π/2), the RF signal RF (ωLO+ωIF+3π/2), and the Im signal Im(ωLO−ωIF+π/2). The 90° coupler 48 shifts the output signal of the node N3 by π/2. Thus, the RF signals at the nodes N1 and N3 are in phase with each other, and the Im signals at the nodes N1 and N3 are 180° out of phase with each other. The RF signal RF(ωLO+ωIF is output from the output terminal RFOut2.
As described above, the third embodiment is capable of suppressing passage of the Im signal and extracting the RF signal as in the case of the first and second embodiments. The positional change of the capacitor C4 makes it possible to set the frequency of the RF signal equal to ωLO+ωIF.
A fourth embodiment has an exemplary structure in which both the RF signal and the Im signal are output.
As illustrated in
Table 5 describes exemplary signals in the mixer 20C.
The signals of FETs 44 and 46 and node N1 are the same as those described in Table 1. The LO signal LO(ωLO) is output from the drain of FET 52. From the drain of FET 54, output are the LO signal LO(ωLO+π), the IF signal IF(ωIF+π), the RF signal RF(ωLO−ωIF), and the Im signal Im(ωLO+ωIF+2π). The phase ωLO+ωIF+2π of the Im signal is equal to ωLO+ωIF. At the node N3, the LO signals are canceled and the IF signal, the RF signal and the Im signal are output.
The output signal of the node N1 and that of the node N3 are combined with each other. The RF signal RF(ωLO−ωIF), and the Im signal Im(ωLO+ωIF) are in phase with each other, and are added. Thus, the RF signal and the Im signal are output as illustrated in
A fifth embodiment has another exemplary structure in which both the RF signal and the Im signal are output.
As illustrated in
Table 6 describes signal outputs in the mixer 20D.
The output signals of FETs 44, 46 and 52 and node N1 are the same as those described in Table 5. From the drain of FET 54, output are the LO signal LO(ωLO+π), the IF signal IF(ωIF), the RF signal RF(ωLO−ωIF+π), and the Im signal Im(ωLO+ωIF+π). From the node 3, output are the IF signal IF(ωIF), the RF signal RF(ωLO−ωIF+π), and the Im signal Im(ωLO+ωIF+π). The balun 70 shifts the phase of the output signal of the node N3 by π. Thus, the RF signal and the Im signal are in phase with each other. The RF signal RF(ωLO−ωIF) and the Im signal Im(ωLO+ωIF) are output from the output terminal RFOut2. The passage of the IF signal is suppressed by the capacitors C2 and C5. The IF signal is suppressed by the balun 70 because the IF signal is out of the band of the balun 70. The fifth embodiment is capable of extracting the RF signal and the Im signal as in the case of the fourth embodiment. According to the first through fifth embodiments, it is possible to output at least one desired signal, which is only the RF signal or the Im signal in addition to the RF signal.
As described above, the capacitors C1 and C4 function as filters that suppress passage of the LO signals.
The filters may be formed by elements other than the capacitors.
The passage of the IF signal may be suppressed by a filter that includes at least one of a capacitor and an inductor, while the passage of the LO signal is allowed. Such filters may be connected between the drains of two pairs of FETs (a pair of FETs 44 and 46 and another pair of FETs 52 and 54). The inductors L1 and L2 and the capacitors C3 and C6 may be replaced with filters including either capacitors or inductors. The FETs may be replaced with another type of transistors such as bipolar transistors.
The present invention is not limited to the exemplary embodiments and variations described above but may include other embodiments and variations without departing from the scope of the claimed invention.
Number | Date | Country | Kind |
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2012-267624 | Dec 2012 | JP | national |
This application is a Continuation of U.S. patent application Ser. No. 14/099,148, filed Dec. 6, 2013, which claims the benefit of Japanese Patent Application No. 2012-267624, filed on Dec. 6, 2012, all of which are incorporated by reference in their entirety.
Number | Date | Country | |
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Parent | 14099148 | Dec 2013 | US |
Child | 14608421 | US |