This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0090744 filed on Jul. 22, 2022 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.
Example embodiments relate generally to semiconductor integrated circuits, and more particularly to modeling methods of neural networks for simulation in semiconductor design process, simulation methods in semiconductor design process using the modeling methods, manufacturing methods of semiconductor devices using the modeling methods, and semiconductor design systems performing the modeling methods and/or the simulation methods.
As higher integration and/or miniaturization of semiconductors have progressed, factors in each operation of designing and manufacturing semiconductor devices may interact in a complex manner, which may cause various unintended electrical characteristics of the semiconductor devices. In order to overcome limitations of semiconductor processes and devices, to understand phenomena, and/or to reduce experimental costs, demand for a technology computer aided design (TCAD) process-device simulation environment based on a physical simulation has been increasing. Further, in order to provide more precise product specifications of a semiconductor device, it may be advantageous to predict and/or simulate the characteristics of the semiconductor device. The TCAD may be used to simulate a semiconductor device, may be used to perform a simulation method in a semiconductor design process, and may be used to simulate a circuit of a semiconductor device.
At least one example embodiment of the present disclosure provides a modeling method of a neural network capable of more efficiently and/or automatically training the neural network for simulation in a semiconductor design process.
At least one example embodiment of the present disclosure provides a simulation method in a semiconductor design process using the modeling method, and a manufacturing method of a semiconductor device using the modeling method.
At least one example embodiment of the present disclosure provides a semiconductor design system performing the modeling method and/or the simulation method.
According to example embodiments, in a modeling method of a neural network, the modeling method is performed by executing program code by at least one processor. The program code is stored in a non-transitory computer readable medium. A first regression model is trained based on first sample data and first simulation result data. The first regression model is used to predict the first simulation result data from the first sample data. The first sample data represent at least one of conditions of a manufacturing process of a semiconductor device and characteristics of the semiconductor device. The first simulation result data are obtained by performing a simulation on the first sample data. In response to a consistency of the first regression model being lower than a target consistency, the first regression model is re-trained based on second sample data different from the first sample data. The second sample data are associated with a consistency reduction factor of the first regression model that is responsible for a prediction failure of the first regression model.
According to example embodiments, in a simulation method performed by executing program code by at least one processor, the program code is stored in a non-transitory computer readable medium. A data collection operation and a training operation are performed to generate a first regression model used in a semiconductor design process. An inference operation is performed based on the generated first regression model. When performing the data collection operation and the training operation, the first regression model is trained based on first sample data and first simulation result data. The first regression model is used to predict the first simulation result data from the first sample data. The first sample data represent at least one of conditions of a manufacturing process of a semiconductor device and characteristics of the semiconductor device. The first simulation result data are obtained by performing a simulation on the first sample data. In response to a consistency of the first regression model being lower than a target consistency, the first regression model is re-trained based on second sample data different from the first sample data. The second sample data are associated with a consistency reduction factor of the first regression model that is responsible for a prediction failure of the first regression model.
According to example embodiments, a semiconductor design system includes at least one processor and a non-transitory computer readable medium. The non-transitory computer readable medium stores program code executed by the at least one processor to generate a first regression model used in a semiconductor design process. The at least one processor, by executing the program code, trains the first regression model based on first sample data and first simulation result data, and re-trains the first regression model based on second sample data different from the first sample data in response to a consistency of the first regression model being lower than a target consistency. The first regression model is used to predict the first simulation result data from the first sample data. The first sample data represent at least one of conditions of a manufacturing process of a semiconductor device and characteristics of the semiconductor device. The first simulation result data are obtained by performing a simulation on the first sample data. The second sample data are associated with a consistency reduction factor of the first regression model that is responsible for a prediction failure of the first regression model.
According to example embodiments, in a modeling method of a neural network, the modeling method is performed by executing program code by at least one processor. The program code is stored in a non-transitory computer readable medium. A simulation target and an analysis range associated with a semiconductor device are set. First sample data are generated within the analysis range. The first sample data represent at least one of conditions of a manufacturing process of the semiconductor device and characteristics of the semiconductor device. First simulation result data are obtained by performing a simulation on the first sample data based on a technology computer aided design (TCAD). A first regression model is trained based on the first sample data and the first simulation result data. The first regression model is used to predict the first simulation result data from the first sample data. A consistency of the first regression model is checked by obtaining first prediction data based on the first regression model and the first sample data, by calculating the consistency of the first regression model based on the first prediction data and the first simulation result data, and by comparing the consistency of the first regression model with a target consistency. In response to the consistency of the first regression model being lower than the target consistency, second sample data different from the first sample data are obtained. The second sample data are associated with a consistency reduction factor of the first regression model that is responsible for a prediction failure of the first regression model. Second simulation result data are obtained by performing a simulation on the second sample data based on the TCAD. The first regression model is re-trained such that the first and second simulation result data are predicted from the first and second sample data. The second sample data are obtained by performing at least one of an active sampling and a balanced sampling. The active sampling is performed using a second regression model different from the first regression model. The second regression model is used to predict first error data representing errors between the first simulation result data and the first prediction data. The balanced sampling is performed using a sparse interval in a first histogram of the first simulation result data. The sparse interval represents an interval in which a number of simulation result data is less than a reference number.
According to example embodiments, in a manufacturing method of a semiconductor device, a simulation is performed on the semiconductor device by executing program code by at least one processor. The program code is stored in a non-transitory computer readable medium. The semiconductor device is fabricated based on a result of the simulation on the semiconductor device. When performing the simulation, a data collection operation and a training operation are performed to generate a first regression model used in a semiconductor design process. An inference operation is performed based on the generated first regression model. When performing the data collection operation and the training operation, the first regression model is trained based on first sample data and first simulation result data. The first regression model is used to predict the first simulation result data from the first sample data. The first sample data represent at least one of conditions of a manufacturing process of the semiconductor device and characteristics of the semiconductor device. The first simulation result data are obtained by performing a simulation on the first sample data. In response to a consistency of the first regression model being lower than a target consistency, the first regression model is re-trained based on second sample data different from the first sample data. The second sample data are associated with a consistency reduction factor of the first regression model that is responsible for a prediction failure of the first regression model.
In the modeling method, the simulation method, the manufacturing method and the semiconductor design system according to example embodiments, a consistency improvement process for updating the first regression model may be implemented by actively obtaining samples associated with regions where a prediction has failed, and thus factors that cause a reduction in the consistency of the first regression model may be handled or managed. For example, the first regression model may be re-trained based on the second sample data corresponding to the prediction failure by the first regression model. Accordingly, only the regions where the prediction has failed may be selectively trained, time required for the data collection operation may be saved, and the consistency of the first regression model may be improved or enhanced, thereby achieving the efficiency of the training operation. In addition, the consistency of the first regression model may be improved or enhanced by the automation of the consistency improvement process without an engineer's intervention, thereby achieving the automation of the training operation.
Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to example embodiments set forth herein. Like reference numerals refer to like elements throughout this application.
Referring to
In the modeling method according to example embodiments, a first regression model is trained or learned based on first sample data and first simulation result data (operation S100). The first regression model is used to predict the first simulation result data from the first sample data. The first sample data represents at least one of the conditions of the manufacturing process of the semiconductor device and the characteristics of the semiconductor device, which are the target of the simulation. The first simulation result data may be obtained by performing a simulation on the first sample data. For example, the first sample data may include a plurality of sample data, and the first simulation result data may include a plurality of simulation result data. The first regression model may be referred to as an artificial intelligence (AI) model, a surrogate model, a machine learning model, a neural network model, or the like. Operation S100 will be described with reference to
In some example embodiments, the simulation on the first sample data may be performed based on a technology computer aided design (TCAD). TCAD simulation is a technique that reproduces a three-dimensional (3D) structure of a transistor by simulating a semiconductor process or semiconductor device, and that predicts the performance and defect rate of semiconductor devices in a layout design stage to reduce development time and cost.
When a consistency of the first regression model does not reach a target consistency, e.g., when the consistency of the first regression model is lower than the target consistency, the first regression model is re-trained or re-learned based on second sample data different from the first sample data (operation S200). The second sample data is associated with or related to a consistency reduction factor of the first regression model that is responsible for or causes a prediction failure of the first regression model. Operation S200 will be described with reference to
In some example embodiments, a reduction or decrease in the consistency of the first regression model may be caused by a discontinuity of the first simulation result data. In this example, the second sample data may be obtained by performing an active sampling. The active sampling may be performed using a second regression model different from the first regression model. The second regression model may be used to predict first error data representing errors between the first simulation result data and first prediction data, and the first prediction data may be obtained based on the first regression model and the first sample data. The active sampling will be described with reference to
In other example embodiments, a reduction or decrease in the consistency of the first regression model may be caused by a non-uniformity of the first simulation result data. In this example, the second sample data may be obtained by performing a balanced sampling. The balanced sampling may be performed using a sparse interval in a first histogram of the first simulation result data. The sparse interval may represent an interval in which the number of simulation result data is less than a reference number. The balanced sampling will be described with reference to
In still other example embodiments, the second sample data may be obtained by performing both the active sampling and the balanced sampling.
Although
Referring to
When re-training the first regression model (operation S200), it may be checked or determined whether the consistency of the first regression model becomes higher than or equal to the target consistency (operation S201).
When the consistency of the first regression model does not reach the target consistency (operation S201: NO), e.g., when a current consistency value representing the consistency of the first regression model is smaller than a target consistency value representing the target consistency, the first regression model may be re-trained based on the second sample data (operation S203). When the consistency of the first regression model reaches the target consistency (operation S201: YES), e.g., when the current consistency value is greater than or equal to the target consistency value, the process may terminated without re-training the first regression model. In other words, the operation of re-training the first regression model may be repeatedly performed until the consistency of the first regression model becomes higher than or equal to the target consistency.
Recently, as higher integration and/or miniaturization of semiconductors have progressed, an influence of process variation or distribution on defects or failures is increasing. To reflect the process variation in a simulation, a massive amount of simulations corresponding to the number of target patterns (e.g., a pattern count) existing on a semiconductor device or chip may be required. However, considering the number of hundreds to billions of pattern counts and the simulation time of about several minutes to several hours per simulation, such analysis may be very difficult.
The above-described limitations may be overcome using an AI model or a surrogate model that simulates simulation results, and the process may be performed as follows: 1) data collection operation—simulation results may be collected for thousands of random process conditions within a scope of a design of experiment (DOE); 2) training or learning operation—an AI model that simulates the collected simulation results may be trained; and 3) inference operation—conditions associated with an occurrence of defects may be analyzed by applying the trained AI model to the DOE reflecting the process variation. For example, operations S100 and S200 described with reference to
To accurately analyze the process variation in the inference operation, it may be advantageous to obtain the AI model with higher consistency. However, it may be difficult to obtain the AI model with higher consistency because a very large amount of samples should be collected in the data collection operation and an intervention of a skilled AI engineer is required. In addition, factors that cause a reduction in the consistency of the AI model that simulates the simulation results may be discontinuity and non-uniformity of the simulation results.
In the modeling method of the neural network according to example embodiments, a consistency improvement process for updating an AI model (e.g., the first regression model) may be implemented by actively obtaining samples associated with regions where a prediction has failed, and thus factors that cause a reduction in the consistency of the AI model may be handled or managed. For example, the first regression model may be re-trained based on the second sample data corresponding to the prediction failure by the first regression model. Accordingly, only the regions where the prediction has failed may be selectively trained, time required for the data collection operation may be saved, and the consistency of the first regression model may be improved or enhanced, thereby achieving the efficiency of the training operation. In addition, the consistency of the first regression model may be improved or enhanced by the automation of the consistency improvement process without an engineer's intervention, thereby achieving the automation of the training operation.
Referring to
Herein, the term “module” may indicate, but is not limited to, a software and/or hardware component, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), which performs certain tasks. A module may be configured to reside in a tangible addressable storage medium and be configured to execute on one or more processors. For example, a “module” may include components such as software components, object-oriented software components, class components and task components, and processes, functions, Routines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. A “module” may be divided into a plurality of “modules” that perform detailed functions.
The processor 1100 may be used when the neural network modeling and simulation module 1300 performs computations or calculations. For example, the processor 1100 may include a microprocessor, an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), a graphic processing unit (GPU), a neural processing unit (NPU), or the like. Although
The storage device 1200 may store data used for operations of the processor 1100 and the neural network modeling and simulation module 1300. In some example embodiments, the storage device (or storage medium) 1200 may include any non-transitory computer-readable storage medium used to provide commands and/or data to a computer. For example, the non-transitory computer-readable storage medium may include a volatile memory such as a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like, and a nonvolatile memory such as a flash memory, a magnetic random access memory (MRAM), a phase-change random access memory (PRAM), a resistive random access memory (RRAM), or the like. The non-transitory computer-readable storage medium may be inserted into the computer, may be integrated in the computer, or may be coupled to the computer through a communication medium such as a network and/or a wireless link.
The neural network modeling and simulation module 1300 may perform the modeling method of the neural network according to example embodiments described with reference to
The data collection module 1310 may perform a data collection operation for performing the modeling method and/or the simulation method according to example embodiments. For example, the data collection module 1310 may collect sample data, and may collect and/or generate various other data.
The learning module 1320 may perform a training operation (or a re-training operation) for performing the modeling method and/or the simulation method according to example embodiments. For example, the learning module 1320 may perform various operations, processing, data generating and storing, etc. for training an AI model MD (e.g., the first regression model and/or the second regression model).
The inference module 1330 may perform an inference operation for performing the modeling method and/or the simulation method according to example embodiments. For example, the inference module 1330 may perform at least one of predicting a defect rate and optimizing based on the AI model MD that has been trained and generated and by reflecting the process variation and conditions.
The data collection module 1310 and the learning module 1320 may perform operations S100 and S200 described with reference to
In some example embodiments, the AI model MD, the data collection module 1310, the learning module 1320 and the inference module 1330 may be implemented as instructions or program code that may be executed by the processor 1100. For example, the instructions or program code of the AI model MD, the data collection module 1310, the learning module 1320 and the inference module 1330 may be stored in computer readable medium. For example, the processor 1100 may load the instructions or program code to a working memory (e.g., a DRAM, etc.).
In other example embodiments, the processor 1100 may be manufactured to efficiently execute instructions or program code included in the AI model MD, the data collection module 1310, the learning module 1320 and the inference module 1330. For example, the processor 1100 may efficiently execute the instructions or program code from various AI modules and/or machine learning modules. For example, the processor 1100 may receive information corresponding to the AI model MD, the data collection module 1310, the learning module 1320 and the inference module 1330 to operate the AI model MD, the data collection module 1310, the learning module 1320 and the inference module 1330.
In some example embodiments, the data collection module 1310, the learning module 1320 and the inference module 1330 may be implemented as a single integrated module. In other example embodiments, the data collection module 1310, the learning module 1320 and the inference module 1330 may be implemented as separate and different modules.
Referring to
The semiconductor design system 2000 may be a computing system. For example, the computing system may be a fixed computing system such as a desktop computer, a workstation or a server, or may be a portable computing system such as a laptop computer.
The processor 2100 may be the same or substantially the same as the processor 1100 in
In other words, the program PR may include a plurality of instructions and/or procedures executable by the processor 2100, and the plurality of instructions and/or procedures included in the program PR may allow the processor 2100 to perform the operations for the neural network modeling and/or the simulation in the semiconductor design process according to example embodiments. Each of the procedures may denote a series of instructions for performing a certain task. A procedure may be referred to as a function, a routine, a subroutine, or a subprogram. Each of the procedures may process data provided from the outside and/or data generated by another procedure.
In some example embodiments, the RAM 2400 may include any volatile memory such as an SRAM, a DRAM, or the like.
The storage device 2600 may be the same or substantially the same as the storage device 1200 in
The storage device 2600 may store data, which is to be processed by the processor 2100, or data obtained through processing by the processor 2100. The processor 2100 may process the data stored in the storage device 2600 to generate new data, based on the program PR and may store the generated data in the storage device 2600.
The I/O device 2200 may include an input device, such as a keyboard, a pointing device, or the like, and may include an output device such as a display device, a printer, or the like. For example, a user may trigger, through the I/O devices 2200, execution of the program PR by the processor 2100, and may provide or check various inputs, outputs and/or data, etc.
The network interface 2300 may provide access to a network outside the semiconductor design system 2000. For example, the network may include a plurality of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or arbitrary other type links. Various inputs may be provided to the semiconductor design system 2000 through the network interface 2300, and various outputs may be provided to another computing system through the network interface 2300.
In some example embodiments, the computer program code, the AI model MD, the data collection module 1310, the learning module 1320 and/or the inference module 1330 may be stored in a transitory or non-transitory computer readable medium. In some example embodiments, values resulting from a simulation performed by the processor or values obtained from arithmetic processing performed by the processor may be stored in a transitory or non-transitory computer readable medium. In some example embodiments, intermediate values generated during the training operation may be stored in a transitory or non-transitory computer readable medium. In some example embodiments, various data such as sample data, simulation result data, device data, prediction data, error data, error prediction data and histogram data may be stored in a transitory or non-transitory computer readable medium. However, example embodiments are not limited thereto.
Referring to
The input layer IL may include i input nodes x1, x2, . . . , xi, where i is a natural number. Input data (e.g., vector input data) IDAT whose length is i may be input to the input nodes x1, x2, . . . , xi such that each element of the input data IDAT is input to a respective one of the input nodes x1, x2, . . . , xi.
The plurality of hidden layers HL1, HL2, . . . , HLn may include n hidden layers, where n is a natural number, and may include a plurality of hidden nodes h11, h12, h13, . . . , h1m, h21, h22, h23, . . . , h2m, hn1, hn2, hn3, . . . , hnm. For example, the hidden layer HL1 may include m hidden nodes h11, h12, h13, . . . , h1m, the hidden layer HL2 may include m hidden nodes h21, h22, h23, . . . , h2m, and the hidden layer HLn may include m hidden nodes hn1, hn2, hn3, . . . , hnm, where m is a natural number.
The output layer OL may include j output nodes y1, y2, . . . , yj, where j is a natural number. The output layer OL may generate output values (e.g., numerical output such as a regression variable) and/or output data ODAT associated with the input data IDAT. In some example embodiments, the output layer OL may be a fully-connected layer and may indicate, for example, output values when the input data DAT is applied to the TCAD simulation.
A structure of the neural network illustrated in
Each node (e.g., the node h11) may receive an output of a previous node (e.g., the node x1), may perform a computing operation, computation or calculation on the received output, and may output a result of the computing operation, computation or calculation as an output to a next node (e.g., the node h21). Each node may calculate a value to be output by applying the input to a specific function, e.g., a nonlinear function.
In some example embodiments, the structure of the neural network may be set in advance, and the weighted values for the connections between the nodes may be set appropriately by using sample data having sample answer, which indicates result data corresponding to a sample input value. The data with the sample answer may be referred to as “training data”, and a process of determining the weighted value may be referred to as “training”. The neural network “learns” to associate the data with corresponding labels during the training process. A group of an independently trainable structure and the weighted value may be referred to as a “model”, and a process of predicting, by the model with the determined weighted value, which class input data belongs to, and then outputting the predicted value, may be referred to as a “testing” process.
Referring to
Based on N inputs a1, a2, a3, . . . , aN provided to the node ND, where N is a natural number greater than or equal to two, the node ND may multiply the N inputs a1 to aN and corresponding N weights w1, w2, w3, . . . , wN, respectively, may sum N values obtained by the multiplication, may add an offset “b” to a summed value, and may generate one output value (e.g., “z”) by applying a value to which the offset “b” is added to a specific function “σ”.
In some example embodiments and as illustrated in
W*A=Z [Equation 1]
In Equation 1, “W” denotes a weight set including weights for all connections included in the one layer, and may be implemented in an M*N matrix form. “A” denotes an input set including the N inputs a1 to aN received by the one layer, and may be implemented in an N*1 matrix form. “Z” denotes an output set including M outputs z1, z2, z3, . . . , zM output from the one layer, and may be implemented in an M*1 matrix form.
Referring to
Each of the plurality of general neural networks NN1 to NNK may have a structure described with reference to
The plurality of general neural networks NN1 to NNK may output a plurality of output data ODAT1, ODAT2, . . . , ODATK corresponding to the input data IDAT. An average value of the plurality of output data ODAT1 to ODATK may be output as final output data FODAT of the ensemble neural network.
In some example embodiments, in the modeling method according to example embodiments, the training of the first regression model may be performed based on the ensemble neural network. For example, the training of the first regression model may be performed based on an ensemble neural network that includes ten general neural networks each of which includes three fully-connected layers with 256 nodes.
However, example embodiments may not be limited thereto, and may be applied or employed to various other neural networks such as generative adversarial network (GAN), region with convolutional neural network (R-CNN), region proposal network (RPN), recurrent neural network (RNN), stacking-based deep neural network (S-DNN), state-space dynamic neural network (S-SDNN), deconvolution network, deep belief network (DBN), restricted Boltzman machine (RBM), fully convolutional network, long short-term memory (LSTM) network. Alternatively or additionally, the neural network may include other forms of machine learning models, such as, for example, linear and/or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and/or combinations thereof, including ensembles such as random forests.
Referring to
Sample data may be randomly generated within the analysis range (operation S120). The sample data generated in operation S120 may correspond to the first sample data in operation S100 of
In some example embodiments, Operation S120 may be performed based on a Sobol algorithm. The Sobol algorithm is an algorithm in which samples are obtained from each subspace while a coordinate space is dividing into subspaces having the same volume, and thus samples are uniformly obtained from the entire coordinate space. However, example embodiments are not limited thereto.
Simulation result data may be obtained by performing a simulation on the sample data generated in operation S120 (operation S130). When the sample data generated in operation S120 correspond to the first sample data, the simulation result data obtained based on the first sample data in operation S130 may correspond to the first simulation result data in operation S100 of
Based on the sample data (e.g., the first sample data) generated in operation S120 and the simulation result data (e.g., the first simulation result data) obtained in operation S130, The first regression model may be trained (operation S140). For example, the first regression model may be trained using the ensemble neural network described with reference to
The consistency of the first regression model trained in operation S140 may be checked (operation S150). For example, the consistency of the first regression model may be checked using an R2-score between predicted values of the first sample data in the first regression model and the first simulation result data. The predicted values of the first sample data in the first regression model may be denoted by “f(X)”. The consistency of the first regression model checked in operation S150 may be referred to as a prediction consistency, a current consistency, or the like.
When it is determined that the consistency of the first regression model reaches the target consistency based on a result of checking the consistency of the first regression model (operation S150: PASS), the process may be terminated without re-training the first regression model.
When re-training the first regression model (operation S200), when the consistency of the first regression model does not reach the target consistency based on the result of checking the consistency of the first regression model (operation S150: FAIL), additional sample data may be generated to intensively train regions where the first regression model fails to predict (operation S210). The additional sample data generated in operation S210 first time may correspond to the second sample data in operation S200 of
In some example embodiments, when operation S210 is performed, at least one of the active sampling and the balanced sampling may be performed, which will be described with reference to
Additional simulation result data may be obtained by performing a simulation on the additional sample data generated in operation S210 (operation S130). When the additional sample data generated in operation S210 first time correspond to the second sample data, the simulation result data obtained based on the second sample data in operation S130 may be referred to as second simulation result data to be distinguished from the first simulation result data.
Based on the sample data (e.g., the first sample data) generated in operation S120, the additional sample data (e.g., the second sample data) generated in operation S210, and the simulation result data (e.g., the first and second simulation result data) obtained in operation S130, the first regression model may be re-trained such that the first and second simulation result data are predicted from the first and second sample data (operation S140). Thereafter, the consistency of the first regression model re-trained in operation S140 may be checked again (operation S150).
As described above, operations S110 and S120 and operations S130, S140 and S150 that are performed first time may correspond to operation S100 in
As described with reference to
Referring to
When the consistency of the first regression model calculated in operation S153 is lower than the target consistency (operation S155: YES), operation S210 may be performed. When the consistency of the first regression model calculated in operation S153 becomes higher than or equal to the target consistency (operation S155: NO), the process may be terminated without re-training the first regression model.
Referring to
When generating the additional sample data (operation S210), the first prediction data may be obtained based on the first regression model and the first sample data (operation S221). Operation S221 may be the same or substantially the same as operation S151 in
First error data may be calculated (operation S223). The first error data may represent errors between the first simulation result data and the first predicted data. The first error data may be denoted by “e”, and e=|y−ƒ(X)|.
A second regression model may be trained (operation S225). The second regression model may be used to predict the first error data from the first sample data. For example, as with operation S140 in
In some example embodiments, the higher the value of “g(x)” increases, the lower the predictive ability of the first regression model “f” at or around “x”. In other words, as the value of “g(x)” increases, there may be a higher probability to improve the consistency of the first regression model when “x” is included in a training set. Therefore, when samples having higher values of “g(x)” are collected as the second sample data, it may be more advantageous for improving the consistency of the first regression model.
To collect the samples having the higher values of “g(x)”, a large or massive amount of first candidate sample data may be generated (operation S227). For example, the number of the first candidate sample data may be greater than the number of the first sample data. For example, when the number of the first sample data is N, the number of the first candidate sample data may be M, where M is a natural number greater than N. For example, M=N*20, but example embodiments are not limited thereto. For example, M may be designated and changed based on a user setting signal.
In some example embodiments, as with operation S120 in
The second sample data may be selected from among the first candidate sample data based on the second regression model (operation S229). For example, the number of second sample data may be N, which is equal to the number of first sample data, but example embodiments are not limited thereto.
Referring to
In some example embodiments, the number of the first candidate sample data may be M, and the number of the first error prediction data obtained based on the first candidate sample data may also be M, where M is a natural number greater than or equal to two. Each of the M first error prediction data may correspond to a respective one of the M first candidate sample data. When the number of the second sample data is equal to the number of the first sample data, N first candidate sample data may be selected from among the M first candidate sample data as the second sample data, where N is a natural number less than M. As described above, it may be advantageous for improving the consistency of the first regression model when the samples having the higher values of “g(x)” are collected as the second sample data, and thus the N first candidate sample data selected as the second sample data may correspond to N first error prediction data having higher or larger values from among the M first error prediction data.
Although the example where the second sample data are generated as the additional sample data is described with reference to
Referring to
In the simulation analysis associated with defects due to process variation, the analysis range may be increased from the adjustable range (e.g., from μ1 to μ2) of process conditions to the extended range (e.g., from (μ1−3σ) to (μ2+3σ) when a standard deviation of the process variation is σ) due to the process variation. In this situation, the unpredictable discontinuous pattern change (hereinafter referred to as discontinuity) may occur due to excessive extension of the analysis range.
For example, when a first structure to be formed in a semiconductor substrate is designed, the performance simulation for the first structure according to changes in an etch depth and an etch width of the first structure may be performed. For example, a simulation may be performed to find an optimal width and an optimal depth of the first structure between a first example of
For this optimization problem, when a range of the process conditions is set to a range from μ1 to μ2 and a standard deviation of the process variation is σ, a range to be analyzed for the first structure may be extended a range from (μ1−3σ) to (μ2+3σ), as illustrated in
When the unusual region 600 associated with the discontinuity occurs, the pattern of simulation result values may become completely different with respect to the boundary of the region where the discontinuous change occurs. The consistency of the AI model may be reduced by the unusual region 600 for the following reasons:
When an extreme lack of samples occurs as described above in 2), it may be very difficult to increase the consistency of the AI model by only improving algorithm, and additional samples for obtaining additional information on the unusual region 600 may be required. When samples to be added are selected within the unusual region 600, the consistency of the AI model may increase efficiently. Accordingly, when the active sampling described with reference to
Referring to
When generating the additional sample data (operation S210), a first histogram of the first simulation result data may be generated (operation S251). For example, the first histogram may be used to check a distribution of the first simulation result data.
To uniformly distribute the “y” values, a large or massive amount of first candidate sample data may be generated (operation S253). Operation S253 may be the same or substantially the same as operation S227 in
The second sample data may be selected from among the first candidate sample data based on the first histogram (operation S255).
Referring to
In some example embodiments, the number of the first candidate sample data may be M, and the number of the first candidate prediction data obtained based on the first candidate sample data may also be M. Each of the M first candidate prediction data may correspond to a respective one of the M first candidate sample data. When the number of the second sample data is equal to the number of the first sample data, N first candidate sample data are selected from among the M first candidate sample data as the second sample data. As described above, it may be advantageous for improving the consistency of the first regression model when the sample are collected so that “y” values are uniformly distributed, and thus the N first candidate sample data selected as the second sample data may correspond to N first candidate prediction data included in the sparse interval from among the M first candidate prediction data.
Although the example where the second sample data are generated as the additional sample data is described with reference to
Referring to
When a simulation result value “y” changes nonlinearly (e.g., exponentially) according to the change in a process variable “x”, the non-uniformity in which the distribution of “y” values is biased to a specific range may occur.
For example, a simulation may be performed to predict an input resistance of a memory cell (e.g., a DRAM cell). For example, as illustrated in
As described above, when the distribution of “y” is biased to the specific range, there may be a problem that the AI model may fail to predict for a range where “y” values are sparse.
For example, when the distribution of “y” is not uniform as illustrated in
As described above with reference to the active sampling, it may also be very difficult to increase the consistency of the AI model by only improving algorithm, and a process of supplementing information by additionally sampling for the sparse interval is necessary. The exponential relationship between “x” and “y” may frequently occur in the semiconductor design process, and thus the balanced sampling may be applied or employed so that “y” values are uniformly distributed over all intervals. In the balanced sampling described with reference to
In the modeling method of the neural network according to example embodiments, to improve the consistency of the AI model, an artificial sampling technique for a specific region may be performed. Therefore, samples of input data generated for training the AI model may be biased to the specific region, and it may be checked or determined whether the samples are concentrated in the specific region as follows. When the coordinate space of the input data is divided into V spaces with the same hyper-volume, and when one of the V spaces is Sv, an expected value of the number of samples to be included in Sv among N random samples may be λ=N/V, and a probability that k samples are included in Sv may be based on a Poisson distribution P(k)=λke−λ/k!. In addition, a probability that more than K samples are found in a specific space Sv may be calculated as a cumulative probability distribution ∫K∞P(k)dk. Accordingly, when K samples are found in the specific space Sv in the input data, and when the expected probability value for K is too small (<0.001), this may mean that the sampling technique for increasing the consistency may be applied or used according to example embodiments.
Referring to
In the simulation method according to example embodiments, a data collection operation and a training operation are performed to generate a first regression model used in the semiconductor design process (operation S1100). The data collection operation and the training operation in operation S1100 may be performed the modeling method of the neural network according to example embodiments described with reference to
An inference operation is performed based on the first regression model that has been trained and generated (operation S1200). The inference operation may represent an operation of predicting performance and defect rate of the semiconductor device by applying the trained first regression model to input data reflecting the process variation.
In some example embodiments, the semiconductor design process in which the simulation method according to example embodiments is performed may include a behavior level design (or behavior level design process) of the semiconductor device, a register transfer level (RTL) design (or RTL design process) of the semiconductor device, a gate level design (or gate level design process) of the semiconductor device, a layout level design (or layout level design process) of the semiconductor device, or the like. The simulation method according to example embodiments may be performed in the layout level design.
The behavior level design may be referred to as an architecture design or a high level design (or high level design process). The high level design may represent that a semiconductor device to be designed or as a target device is depicted at an algorithm level and is described in terms of high-level computer language (e.g., C language).
Devices and/or circuits designed by the high level design process may be more concretely described by an RTL coding or simulation. In addition, code generated by the RTL coding may be converted into a netlist, and the results may be combined with each other to realize the entire semiconductor device. The combined schematic circuit may be verified by a simulation tool. In some example embodiments, an adjusting operation may be further performed in consideration of a result of the verification. The RTL may be used for representing a coding style used in hardware description languages for effectively ensuring that code models may be synthesized in a certain hardware platform such as an FPGA or an ASIC (e.g., code models may be converted into real logic functions). A plurality of hardware description languages may be used for generating RTL modules. For example, the plurality of hardware description languages may include System Verilog, Verilog, VHSIC hardware description language (VHDL), or the like.
The gate level design may represent that a semiconductor device is depicted using basic logic gates, such as AND gates and OR gates, and is described by logical connections and timing information of the logic gates. For example, all signals may be discrete signals and may only have a logical value of zero, one, X and Z (or high-Z).
The layout level design may be referred to as a physical design (or physical design process). The layout level design may be performed to implement or realize a logically completed semiconductor device on a silicon substrate. For example, the layout level design may be performed based on the schematic circuit prepared in the high level design or the netlist corresponding thereto. The layout level design may include a routing operation of placing and connecting various standard cells that are provided from a cell library, based on a predetermined or alternatively, desired design rule.
Referring to
The sampled first input data may be inferred based on the first regression model that has been trained and generated in operation S1100 (operation S1230), and at least one of the predicting the defect rate of the semiconductor device and the optimizing the semiconductor device may be performed based on a result of inferring the sampled first input data (operation S1240).
When the data collection operation, the training operation and the inference operation as described above, the process variation for simulation targets may be efficiently managed.
Referring to
In operation S2200, the semiconductor device may be fabricated or manufactured by a mask, a wafer, a test, an assembly, packaging, and the like. For example, a corrected layout may be generated by performing optical proximity correction on the design layout, and a photo mask may be fabricated or manufactured based on the corrected layout. For example, various types of exposure and etching processes may be repeatedly performed using the photo mask, and patterns corresponding to the layout design may be sequentially formed on a substrate through these processes. Thereafter, the semiconductor device may be obtained in the form of a semiconductor chip through various additional processes.
Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc. As will be appreciated by those skilled in the art, the inventive concepts may be
embodied as a system, method, computer program product, and/or a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. The computer readable program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, the computer readable medium may be a non-transitory computer readable medium.
The inventive concepts may be applied to design various electronic devices and systems that include the semiconductor devices and the semiconductor integrated circuits. For example, the inventive concepts may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, an automotive, etc.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.
Number | Date | Country | Kind |
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10-2022-0090744 | Jul 2022 | KR | national |