Patent Application
20180314289
Embodiments relate to computer processors, and more particularly to modifying operating frequency in computer processors.
Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Further, as the density of integrated circuits has grown, the power requirements for computing systems have also grown. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits.
Some computing uses or applications may involve a waiting time period to wait for data or a resource. For example, assume that a central processing unit (CPU) core executes an application that receives graphics data from a graphics processing unit. Further, the application may include a “spin-wait” loop, or a repeated loop that waits for the graphics data to be received from the graphics processing unit. Such wait periods may consume processing cycles and electrical power while the program is waiting. The processing cycles used during these wait periods may be referred to as wasted work of the CPU.
In accordance with one or more embodiments, a throttling circuit may adjust the operating frequency of a processing engine (e.g., a processing core of a CPU). The throttling circuit may detect a pause instruction executed in the processing engine. As used herein, the term “pause instruction” refers to any instruction that does not process or change data, but delays execution of the next instruction for a defined time period. Further, the terms “pause” or “paused” refer to the state of the processing engine while executing a pause instruction. In some embodiments, the throttling circuit may determine whether the processing engine is paused for at least a minimum period. If so, the throttling circuit may reduce the operating frequency and/or voltage of the processing engine. In this manner, fewer processing cycles and/or less electrical power may be used to pause the processing engine. Accordingly, the amount of wasted work associated with a pause instruction may be reduced. Example implementations of throttling circuits are described below with reference to
Referring to
As shown in
The processor 1710 may be a general-purpose hardware processing device (e.g., a central processing unit (CPU), a System on a Chip (SoC), and so forth). As shown, the processor 1710 can include a throttling circuit 1720 and any number of processing engines 1715A-1715N (also referred to generally as processing engines 1715). Each processing engine 1715 may be a general-purpose processing core.
In one or more embodiments, the throttling circuit 1720 may be one or hardware components for modifying the operating frequency (also referred to as the clock frequency) of the processing engines 1715. For example, the throttling circuit 1720 may be implemented in microarchitecture of the processor 1710 and/or the processing engines 1715.
In some embodiments, the throttling circuit 1720 may detect a pause instruction executed in a processing engine 1715. When executing the pause instruction, the processing engine 1715 may delay execution of the next instruction for a defined time period. Thus, executing the pause instruction does not process or change any data, but pauses execution of the processing engine 1715. In some embodiments, in response to detecting the pause instruction, the throttling circuit 1720 may initiate a counter of the number of clock cycles that the processing engine 1715 is paused. If the count reaches a threshold level, the throttling circuit 1720 may reduce the operating frequency and/or voltage of the processing engine 1715. As such, some embodiments may reduce the number of clock cycles and/or electrical power required while the processing engine 1715 is paused.
Referring now to
As shown in
The instruction detector 1820 may initiate a cycle counter 1830 to count the number of clock cycles that the processing engine 1815 is paused by executing the pause instruction 1810. In one or more embodiments, the cycle counter 1830 may be implemented in hardware (e.g., a shift register including a series of flip-flops).
In some embodiments, the cycle counter 1830 may count the number of clock cycles that the processing engine 1815 is paused by executing multiple pause instructions 1810. For example, assume that the processing engine 1815 is executing program code including a spin-wait loop to wait for a resource lock, with each iteration of the spin-wait loop executing the pause instruction 1810. Thus, in this example, the processing engine 1815 may execute a series of multiple pause instructions 1810, corresponding to multiple iterations of the spin-wait loop. In some embodiments, the cycle counter 1830 may count the number of clock cycles that the processing engine 1815 is paused in the spin-wait loop by executing the series of multiple pause instructions 1810.
In one or more embodiments, a comparator 1840 may compare the count value 1835 of the cycle counter 1830 to a threshold value 1842. If the count value 1835 has not reached the threshold value 1842, then the operation may return 1844 to the cycle counter 1830 to count additional cycle(s) that the processing engine 1815 is paused. However, if the count value 1835 has reached the threshold value 1842, the comparator 1840 may send a signal 1848 to the power controller 1850. In response to the signal 1848, the power controller 1850 may reduce the operating frequency 1860 of the processing engine 1815 while paused by the pause instruction 1810. As such, the number of processing cycles used by the paused processing engine 1815 may be less than that used when the operating frequency 1860 is not reduced.
Referring now to
In one or more embodiments, the pause indicator 1916A may indicate whether the first core 1910A is executing a pause instruction. For example, the pause indicator 1916A may have a value of “1” when the first core 1910A is executing a pause instruction, and may otherwise have a value of “0.” Further, the pause indicator 1916B may indicate whether the second core 1910B is paused by executing a pause instruction.
In some embodiments, the low/idle indicator 1912A may indicate whether the first core 1910A is an idle/low state. In particular, an idle/low state may include being idle (e.g., no workload, is in a sleep state, is powered off, etc.) or having a low workload (e.g., a current workload below a given threshold). For example, the low/idle indicator 1912A may have a value of “1” when the first core 1910A is an idle/low state, and may otherwise have a value of “0.” Further, the low/idle indicator 1912B may indicate whether the second core 1910B is an idle/low state.
In one or more embodiments, the OR gate 1920 may receive values of the pause indicator 1916A and the low/idle indicator 1912A, and may thus output a positive signal (e.g., “1”) when the first core 1910A is executing a pause instruction or is an idle/low state. Further, the OR gate 1940 may receive values of the pause indicator 1916B and the low/idle indicator 1912B, may thus output a positive signal (e.g., “1”) when the second core 1910B is executing a pause instruction or is an idle/low state. Furthermore, the OR gate 1930 may receive values of the pause indicator 1916A and the pause indicator 1916B, and may thus indicate whether the first core 1910A and/or the second core 1910B are executing pause instructions.
In some embodiments, the AND gate 1950 may receive outputs of the OR gates 1920, 1930, 1940, and may output a positive signal when (1) the first core 1910A is executing a pause instruction or is an idle/low state, the second core 1910B is executing a pause instruction or is an idle/low state, and (3) one or both of the first core 1910A and the second core 1910B are executing pause instructions.
In one or more embodiments, the frequency throttle 1960 may control the operating frequency of the first core 1910A and the second core 1910B based on the output of the AND gate 1950. For example, the frequency throttle 1960 may reduce the operating frequency if the AND gate 1950 outputs a positive signal for at least a given number of clock cycles. Thus, the frequency throttle 1960 may reduce operating frequencies while at least one of the first core 1910A and the second core 1910B are executing pause instructions.
Referring now to
At block 2010, an execution of a pause instruction may be detected in a first processing engine operating at a first frequency level. For example, referring to
At block 2020, in response to the execution of the pause instruction, a cycle counter may be incremented to count the number of clock cycles that the first processing engine is paused by executing the pause instruction. For example, referring to
At block 2030, a determination may be made about whether the cycle counter has reached a first threshold level. For example, referring to
At block 2040, in response to a determination that the cycle counter has reached a first threshold level, an operating frequency of the first processing engine may be changed from the first frequency level to a second frequency level, where the second frequency level is lower than the first frequency level. For example, referring to
Referring now to
At block 2110, a pause instruction may be detected in a processing engine. For example, referring to
At block 2120, in response to the detection of the pause instruction, a counter may be adjusted to count the number of clock cycles that the processing engine is paused by the pause instruction. For example, referring to
At diamond 2130, a determination may be made about whether the counter has reached a threshold. For example, referring to
If it is determined at diamond 2130 that the counter has reached a threshold, then at block 2140, the operating frequency of the processing engine may be reduced. For example, referring to
At diamond 2150, a determination may be made about whether the processing engine is still paused by executing the pause instruction 1810. If it is determined at diamond 2150 that the processing engine is still paused, then the method 2100 may return to block 2120 to continue counting the number of clock cycles that the processing engine is paused. Note that, in some embodiments, the counter may count the number of cycles that a processing engine is paused by executing a single pause instruction, as well as by executing a sequence of multiple pause instructions.
However, if it is determined at diamond 2150 that the processing engine is not still paused, then at diamond 2160, a determination may be made about whether the operating frequency of the processing engine has already been reduced (i.e., at block 2140). If it is determined at diamond 2160 that the operating frequency of the processing engine has already been reduced, then at block 2170, the operating frequency of the processing engine may be increased. For example, referring to
After block 2170, or if it is determined at diamond 2160 that the operating frequency of the processing engine was not already reduced, then at block 2180, the counter may be reset. For example, referring to
After block 2180, the method 2100 may return to block 2110 to continue detecting pause instructions in the processing engine. In some embodiments, the method 2100 may be repeated as required during execution of program code. For example, the method 2100 may be repeated to reduce operating frequencies during multiple spin-wait loops included in an application.
In some embodiments, the method 2100 may be performed using multiple threshold levels and frequency reductions. For example, assume that block 2140 reduces the operating frequency to a first frequency level after the counter reaches a first threshold level (at diamond 2130). Further, the output of diamond 2150 (labeled “YES”) may loop back to block 2120 when the processing engine is still paused. Assume further that, at block 2120, the counter may continue to count cycles until reaching a second threshold level that is higher than the first threshold level. In response to reaching the second threshold level, at block 2140, the operating frequency may be further reduced to a second frequency level that is lower than the first frequency level. In this manner, the method 2100 may be repeated using multiple threshold levels as required.
Note that, while
Referring now to
As seen, processor 110 may be a single die processor including multiple cores 120a-120n. In addition, each core may be associated with an integrated voltage regulator (IVR) 125a-125n which receives the primary regulated voltage and generates an operating voltage to be provided to one or more agents of the processor associated with the IVR. Accordingly, an IVR implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated and supplied by the IVR to only those components in the group. During power management, a given power plane of one IVR may be powered down or off when the processor is placed into a certain low power state, while another power plane of another IVR remains active, or fully powered. Similarly, cores 120 may include or be associated with independent clock generation circuitry such as one or more phase lock loops (PLLs) to control operating frequency of each core 120 independently.
Still referring to
Also shown is a power control unit (PCU) 138, which may include circuitry including hardware, software and/or firmware to perform power management operations with regard to processor 110. As seen, PCU 138 provides control information to external voltage regulator 160 via a digital interface 162 to cause the voltage regulator to generate the appropriate regulated voltage. PCU 138 also provides control information to IVRs 125 via another digital interface 163 to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode). In various embodiments, PCU 138 may include a variety of power management logic units to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).
In
As shown in
Embodiments may be particularly suitable for a multicore processor in which each of multiple cores can operate at an independent voltage and frequency point. As used herein the term “domain” is used to mean a collection of hardware and/or logic that operates at the same voltage and frequency point. In addition, a multicore processor can further include other non-core processing engines such as fixed function units, graphics engines, and so forth. Such processor can include independent domains other than the cores, such as one or more domains associated with a graphics engine (referred to herein as a graphics domain) and one or more domains associated with non-core circuitry, referred to herein as an uncore or a system agent. Although many implementations of a multi-domain processor can be formed on a single semiconductor die, other implementations can be realized by a multi-chip package in which different domains can be present on different semiconductor die of a single package.
While not shown for ease of illustration, understand that additional components may be present within processor 110 such as uncore logic, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of
Note that the power management techniques described herein may be independent of and complementary to an operating system (OS)-based power management (OSPM) mechanism. According to one example OSPM technique, a processor can operate at various performance states or levels, so-called P-states, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic, overclocking, or turbo mode state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency. In many implementations, a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding to a maximum peak frequency of the particular processor, as fused or otherwise written into the processor during manufacture. In addition, according to one OSPM mechanism, a processor can operate at various power states or levels. With regard to power states, an OSPM mechanism may specify different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, and so forth).
Understand that many different types of power management techniques may be used individually or in combination in different embodiments. As representative examples, a power controller may control the processor to be power managed by some form of dynamic voltage frequency scaling (DVFS) in which an operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, DVFS may be performed using Enhanced Intel SpeedStep™ technology available from Intel Corporation, Santa Clara, Calif., to provide optimal performance at a lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoost™ technology to enable one or more cores or other compute engines to operate at a higher than guaranteed operating frequency based on conditions (e.g., workload and availability).
Another power management technique that may be used in certain examples is dynamic swapping of workloads between different compute engines. For example, the processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power constrained situation, one or more workloads can be dynamically switched to execute on a lower power core or other compute engine. Another exemplary power management technique is hardware duty cycling (HDC), which may cause cores and/or other compute engines to be periodically enabled and disabled according to a duty cycle, such that one or more cores may be made inactive during an inactive period of the duty cycle and made active during an active period of the duty cycle.
Power management techniques also may be used when constraints exist in an operating environment. For example, when a power and/or thermal constraint is encountered, power may be reduced by reducing operating frequency and/or voltage. Other power management techniques include throttling instruction execution rate or limiting scheduling of instructions. Still further, it is possible for instructions of a given instruction set architecture to include express or implicit direction as to power management operations. Although described with these particular examples, understand that many other power management techniques may be used in particular embodiments.
Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to
In addition, by interfaces 250a-250n, connection can be made to various off-chip components such as peripheral devices, mass storage and so forth. While shown with this particular implementation in the embodiment of
Referring now to
In general, each of the cores 310a-310n may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 340a-340n. In various embodiments, LLC 340 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 330 thus couples the cores together, and provides interconnection between the cores, graphics domain 320 and system agent domain 350. In one embodiment, interconnect 330 can be part of the core domain. However, in other embodiments the ring interconnect can be of its own domain.
As further seen, system agent domain 350 may include display controller 352 which may provide control of and an interface to an associated display. As further seen, system agent domain 350 may include a power control unit 355 which can include logic to perform the power management techniques described herein.
As further seen in
Referring to
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 400, as illustrated in
As depicted, core 401 includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 400 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 401a, a second thread is associated with architecture state registers 401b, a third thread may be associated with architecture state registers 402a, and a fourth thread may be associated with architecture state registers 402b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 401a are replicated in architecture state registers 401b, so individual architecture states/contexts are capable of being stored for logical processor 401a and logical processor 401b. In core 401, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 430 may also be replicated for threads 401a and 401b. Some resources, such as re-order buffers in reorder/retirement unit 435, branch target buffer and instruction translation lookaside buffer (BTB and I-TLB) 420, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 450, execution unit(s) 440, and portions of reorder/retirement unit 435 are potentially fully shared.
Processor 400 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In
Core 401 further includes decode module 425 coupled to a fetch unit to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Usually core 401 is associated with a first ISA, which defines/specifies instructions executable on processor 400. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode module 425 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoder module 425, in one embodiment, includes logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by the decoder module 425, the architecture or core 401 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.
In one example, allocator and renamer block 430 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, where allocator and renamer block 430 also reserves other resources, such as reorder buffers to track instruction results. The renamer block 430 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 400. Reorder/retirement unit 435 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 440, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation lookaside buffer (D-TLB) 450 are coupled to execution unit(s) 440. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 401 and 402 share access to higher-level or further-out cache 410, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache 410 is a last-level data cache—last cache in the memory hierarchy on processor 400—such as a second or third level data cache. However, higher level cache 410 is not so limited, as it may be associated with or includes an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder module 425 to store recently decoded traces.
In the depicted configuration, processor 400 also includes bus interface 405 and a power control unit 460, which may perform power management in accordance with an embodiment of the present invention. In this scenario, bus interface 405 is to communicate with devices external to processor 400, such as system memory and other components.
A memory controller 470 may interface with other devices such as one or many memories. In an example, bus interface 405 includes a ring interconnect with a memory controller for interfacing with a memory and a graphics controller for interfacing with a graphics processor. In an SoC environment, even more devices, such as a network interface, coprocessors, memory, graphics processor, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
Although not shown in
Referring now to
As seen in
Coupled between front end units 510 and execution units 520 is an out-of-order (OOO) engine 515 that may be used to receive the micro-instructions and prepare them for execution. More specifically OOO engine 515 may include various buffers to re-order micro-instruction flow and allocate various resources needed for execution, as well as to provide renaming of logical registers onto storage locations within various register files such as register file 530 and extended register file 535. Register file 530 may include separate register files for integer and floating point operations. For purposes of configuration, control, and additional operations, a set of machine specific registers (MSRs) 538 may also be present and accessible to various logic within core 500 (and external to the core).
Various resources may be present in execution units 520, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such execution units may include one or more arithmetic logic units (ALUs) 522 and one or more vector execution units 524, among other such execution units.
Results from the execution units may be provided to retirement logic, namely a reorder buffer (ROB) 540. More specifically, ROB 540 may include various arrays and logic to receive information associated with instructions that are executed. This information is then examined by ROB 540 to determine whether the instructions can be validly retired and result data committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent a proper retirement of the instructions. Of course, ROB 540 may handle other operations associated with retirement.
As shown in
Although not shown in
Referring now to
A floating point pipeline 630 includes a floating point (FP) register file 632 which may include a plurality of architectural registers of a given bit width such as 128, 256 or 512 bits. Pipeline 630 includes a floating point scheduler 634 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 635, a shuffle unit 636, and a floating point adder 638. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 632. Of course understand while shown with these few example execution units, additional or different floating point execution units may be present in another embodiment.
An integer pipeline 640 also may be provided. In the embodiment shown, pipeline 640 includes an integer (INT) register file 642 which may include a plurality of architectural registers of a given bit width such as 128 or 256 bits. Pipeline 640 includes an integer execution (IE) scheduler 644 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 645, a shifter unit 646, and a jump execution unit (JEU) 648. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 642. Of course understand while shown with these few example execution units, additional or different integer execution units may be present in another embodiment.
A memory execution (ME) scheduler 650 may schedule memory operations for execution in an address generation unit (AGU) 652, which is also coupled to a TLB 654. As seen, these structures may couple to a data cache 660, which may be a L0 and/or L1 data cache that in turn couples to additional levels of a cache memory hierarchy, including an L2 cache memory.
To provide support for out-of-order execution, an allocator/renamer 670 may be provided, in addition to a reorder buffer 680, which is configured to reorder instructions executed out of order for retirement in order. Although shown with this particular pipeline architecture in the illustration of
Although not shown in
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of
Referring to
With further reference to
Although not shown in
Referring to
Also shown in
Decoded instructions may be issued to a given one of multiple execution units. In the embodiment shown, these execution units include one or more integer units 835, a multiply unit 840, a floating point/vector unit 850, a branch unit 860, and a load/store unit 870. In an embodiment, floating point/vector unit 850 may be configured to handle SIMD or vector data of 128 or 256 bits. Still further, floating point/vector execution unit 850 may perform IEEE-754 double precision floating-point operations. The results of these different execution units may be provided to a writeback unit 880. Note that in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in
Although not shown in
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of
A processor designed using one or more cores having pipelines as in any one or more of
In the high level view shown in
Each core unit 910 may also include an interface such as a bus interface unit to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit 910 couples to a coherent fabric that may act as a primary cache coherent on-die interconnect that in turn couples to a memory controller 935. In turn, memory controller 935 controls communications with a memory such as a DRAM (not shown for ease of illustration in
In addition to core units, additional processing engines are present within the processor, including at least one graphics unit 920 which may include one or more graphics processing units (GPUs) to perform graphics processing as well as to possibly execute general purpose operations on the graphics processor (so-called GPGPU operation). In addition, at least one image signal processor 925 may be present. Signal processor 925 may be configured to process incoming image data received from one or more capture devices, either internal to the SoC or off-chip.
Other accelerators also may be present. In the illustration of
Each of the units may have its power consumption controlled via a power manager 940, which may include control logic to perform the various power management techniques described herein.
In some embodiments, processor 900 may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. One or more interfaces 960a-960d enable communication with one or more off-chip devices. Such communications may be via a variety of communication protocols such as PCIe™, GPIO, USB, I2C, UART, MIPI, SDIO, DDR, SPI, HDMI, among other types of communication protocols. Although shown at this high level in the embodiment of
Although not shown in
Referring now to
As seen in
With further reference to
As seen, the various domains couple to a coherent interconnect 1040, which in an embodiment may be a cache coherent interconnect fabric that in turn couples to an integrated memory controller 1050. Coherent interconnect 1040 may include a shared cache memory, such as an L3 cache, in some examples. In an embodiment, memory controller 1050 may be a direct memory controller to provide for multiple channels of communication with an off-chip memory, such as multiple channels of a DRAM (not shown for ease of illustration in
In different examples, the number of the core domains may vary. For example, for a low power SoC suitable for incorporation into a mobile computing device, a limited number of core domains such as shown in
In yet other embodiments, a greater number of core domains, as well as additional optional IP logic may be present, in that an SoC can be scaled to higher performance (and power) levels for incorporation into other computing devices, such as desktops, servers, high performance computing systems, base stations forth. As one such example, 4 core domains each having a given number of out-of-order cores may be provided. Still further, in addition to optional GPU support (which as an example may take the form of a GPGPU), one or more accelerators to provide optimized hardware support for particular functions (e.g. web serving, network processing, switching or so forth) also may be provided. In addition, an input/output interface may be present to couple such accelerators to off-chip components.
Although not shown in
Referring now to
In turn, a GPU domain 1120 is provided to perform advanced graphics processing in one or more GPUs to handle graphics and compute APIs. A DSP unit 1130 may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth, in addition to advanced calculations that may occur during execution of multimedia instructions. In turn, a communication unit 1140 may include various components to provide connectivity via various wireless protocols, such as cellular communications (including 3G/4G LTE), wireless local area protocols such as Bluetooth™ IEEE 802.11, and so forth.
Still further, a multimedia processor 1150 may be used to perform capture and playback of high definition video and audio content, including processing of user gestures. A sensor unit 1160 may include a plurality of sensors and/or a sensor controller to interface to various off-chip sensors present in a given platform. An image signal processor 1170 may be provided with one or more separate ISPs to perform image processing with regard to captured content from one or more cameras of a platform, including still and video cameras.
A display processor 1180 may provide support for connection to a high definition display of a given pixel density, including the ability to wirelessly communicate content for playback on such display. Still further, a location unit 1190 may include a GPS receiver with support for multiple GPS constellations to provide applications highly accurate positioning information obtained using as such GPS receiver. Understand that while shown with this particular set of components in the example of
Although not shown in
Referring now to
In turn, application processor 1210 can couple to a user interface/display 1220, e.g., a touch screen display. In addition, application processor 1210 may couple to a memory system including a non-volatile memory, namely a flash memory 1230 and a system memory, namely a dynamic random access memory (DRAM) 1235. As further seen, application processor 1210 further couples to a capture device 1240 such as one or more image capture devices that can record video and/or still images.
Still referring to
As further illustrated, a near field communication (NFC) contactless interface 1260 is provided that communicates in a NFC near field via an NFC antenna 1265. While separate antennae are shown in
A power management integrated circuit (PMIC) 1215 couples to application processor 1210 to perform platform level power management. To this end, PMIC 1215 may issue power management requests to application processor 1210 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 1215 may also control the power level of other components of system 1200.
To enable communications to be transmitted and received, various circuitry may be coupled between baseband processor 1205 and an antenna 1290. Specifically, a radio frequency (RF) transceiver 1270 and a wireless local area network (WLAN) transceiver 1275 may be present. In general, RF transceiver 1270 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 1280 may be present. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM and other signals may also be provided. In addition, via WLAN transceiver 1275, local wireless communications can also be realized.
Although not shown in
Referring now to
A variety of devices may couple to SoC 1310. In the illustration shown, a memory subsystem includes a flash memory 1340 and a DRAM 1345 coupled to SoC 1310. In addition, a touch panel 1320 is coupled to the SoC 1310 to provide display capability and user input via touch, including provision of a virtual keyboard on a display of touch panel 1320. To provide wired network connectivity, SoC 1310 couples to an Ethernet interface 1330. A peripheral hub 1325 is coupled to SoC 1310 to enable interfacing with various peripheral devices, such as may be coupled to system 1300 by any of various ports or other connectors.
In addition to internal power management circuitry and functionality within SoC 1310, a PMIC 1380 is coupled to SoC 1310 to provide platform-based power management, e.g., based on whether the system is powered by a battery 1390 or AC power via an AC adapter 1395. In addition to this power source-based power management, PMIC 1380 may further perform platform power management activities based on environmental and usage conditions. Still further, PMIC 1380 may communicate control and status information to SoC 1310 to cause various power management actions within SoC 1310.
Still referring to
As further illustrated, a plurality of sensors 1360 may couple to SoC 1310. These sensors may include various accelerometer, environmental and other sensors, including user gesture sensors. Finally, an audio codec 1365 is coupled to SoC 1310 to provide an interface to an audio output device 1370. Of course understand that while shown with this particular implementation in
Although not shown in
Referring now to
Processor 1410, in one embodiment, communicates with a system memory 1415. As an illustrative example, the system memory 1415 is implemented via multiple memory devices or modules to provide for a given amount of system memory.
To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage 1420 may also couple to processor 1410. In various embodiments, to enable a thinner and lighter system design as well as to improve system responsiveness, this mass storage may be implemented via a SSD or the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities. Also shown in
Various input/output (I/O) devices may be present within system 1400. Specifically shown in the embodiment of
For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners. Certain inertial and environmental sensors may couple to processor 1410 through a sensor hub 1440, e.g., via an I2C interconnect. In the embodiment shown in
As also seen in
System 1400 can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown in
As further seen in
In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit 1456 which in turn may couple to a subscriber identity module (SIM) 1457. In addition, to enable receipt and use of location information, a GPS module 1455 may also be present. Note that in the embodiment shown in
To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) 1460, which may couple to processor 1410 via a high definition audio (HDA) link. Similarly, DSP 1460 may communicate with an integrated coder/decoder (CODEC) and amplifier 1462 that in turn may couple to output speakers 1463 which may be implemented within the chassis. Similarly, amplifier and CODEC 1462 can be coupled to receive audio inputs from a microphone 1465 which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC 1462 to a headphone jack 1464. Although shown with these particular components in the embodiment of
Although not shown in
Embodiments may be implemented in many different system types. Referring now to
Still referring to
Furthermore, chipset 1590 includes an interface 1592 to couple chipset 1590 with a high-performance graphics engine 1538, by a P-P interconnect 1539. In turn, chipset 1590 may be coupled to a first bus 1516 via an interface 1596. As shown in
Although not shown in
One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.
The RTL design 1615 or equivalent may be further synthesized by the design facility into a hardware model 1620, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a third-party fabrication facility 1665 using non-volatile memory 1640 (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternately, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 1650 or wireless connection 1660. The fabrication facility 1665 may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.
Note that the examples shown in
Although some embodiments are described with reference to specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices. For example, the disclosed embodiments are not limited to any particular type of computer systems. That is, disclosed embodiments can be used in many different system types, ranging from server computers (e.g., tower, rack, blade, micro-server and so forth), communications systems, storage systems, desktop computers of any configuration, laptop, notebook, and tablet computers (including 2:1 tablets, phablets and so forth), and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smartphones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. More so, embodiments may be implemented in mobile terminals having standard voice functionality such as mobile phones, smartphones and phablets, and/or in non-mobile terminals without a standard wireless voice function communication capability, such as many wearables, tablets, notebooks, desktops, micro-servers, servers and so forth. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software implementations.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments also may be implemented in data and may be stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
The following clauses and/or examples pertain to further embodiments.
In Example 1, a processor for frequency throttling comprises a plurality of processing engines and a throttling circuit. The throttling circuit may be to: detect an execution of a pause instruction in a first processing engine operating at a first frequency level; in response to the execution of the pause instruction, increment a cycle counter to count a number of cycles that the first processing engine is paused by executing the pause instruction; and in response to a determination that the cycle counter has reached a first threshold level, change an operating frequency of the first processing engine from the first frequency level to a second frequency level, wherein the second frequency level is lower than the first frequency level.
In Example 2, the subject matter of Example 1 may optionally include that the throttling circuit is to: determine whether the cycle counter has reached the first threshold level; and maintain the operating frequency of the first processing engine at the first frequency level while the cycle counter has not reached the first threshold level.
In Example 3, the subject matter of Examples 1-2 may optionally include that the throttling circuit is to: determine whether the first processing engine is still paused by the pause instruction; and in response to a determination that the first processing engine is no longer paused by the pause instruction, change the operating frequency of the first processing engine from the second frequency level to the first frequency level.
In Example 4, the subject matter of Examples 1-3 may optionally include that the throttling circuit is to: determine whether the cycle counter has reached a second threshold level; and in response to a determination that the cycle counter has reached the second threshold level, change the operating frequency of the first processing engine from the second frequency level to a third frequency level, wherein the third frequency level is lower than the second frequency level.
In Example 5, the subject matter of Examples 1-4 may optionally include that the throttling circuit is to: increment the cycle counter to count the number of cycles that a second processing engine and the first processing engine are both paused by pause instructions; and in response to the determination that the cycle counter has reached the first threshold level, reduce the operating frequencies of the first processing engine and the second processing engine.
In Example 6, the subject matter of Examples 1-5 may optionally include that the pause instruction is included in a spin-wait loop of program code executed by the first processing engine.
In Example 7, the subject matter of Examples 1-6 may optionally include that the throttling circuit is included in the first processing engine.
In Example 8, the subject matter of Examples 1-7 may optionally include that the throttling circuit is included in a power control unit of the processor, where the power control unit and the first processing engine are separate components of the processor.
In Example 9, a method for frequency throttling may include: detecting, by a throttling circuit of a processor, a pause instruction in a first processing engine of the processor; in response to a detection of the pause instruction, adjusting a cycle counter to count a number of cycles that the first processing engine is paused by an execution of the pause instruction; determining that the cycle counter has reached a first threshold level; and in response to a determination that the cycle counter has reached the first threshold level, reducing, by the throttling circuit, an operating frequency of the first processing engine to a first reduced frequency level.
In Example 10, the subject matter of Example 9 may optionally include determining, by the throttling circuit, whether the first processing engine is still paused by the execution of the pause instruction; and in response to a determination that the first processing engine is no longer paused by the execution of the pause instruction: increasing the operating frequency of the first processing engine from the first reduced frequency level; and resetting the cycle counter.
In Example 11, the subject matter of Examples 9-10 may optionally include, in response to a determination that the cycle counter has not reached the first threshold level, maintaining the operating frequency of the first processing engine.
In Example 12, the subject matter of Examples 9-11 may optionally include, after reducing the operating frequency to the reduced frequency level, determining, by the throttling circuit, whether the cycle counter has reached a second threshold level; and in response to a determination that the cycle counter has reached the second threshold level, reducing the operating frequency of the first processing engine from the first reduced frequency level to a second reduced frequency level.
In Example 13, the subject matter of Examples 9-12 may optionally include: adjusting the cycle counter to count the number of cycles that the first processing engine and a second processing engine of the processor are both paused by pause instructions; and in response to a determination that the cycle counter has reached the first threshold level, reducing the operating frequencies of the first processing engine and the second processing engine.
In Example 14, the subject matter of Examples 9-13 may optionally include: executing the pause instruction by the first processing engine; and in response to an execution of the pause instruction, delaying an execution of a next instruction execution by the first processing engine for a defined time period.
In Example 15, a computing device for data selection includes one or more processors; and a memory having stored therein a plurality of instructions that when executed by the one or more processors, cause the computing device to perform the method of any of Examples 9 to 14.
In Example 16, at least one machine-readable medium having stored thereon data which, if used by at least one machine, causes the at least one machine to perform the method of any of Examples 9 to 14.
In Example 17, an electronic device for data selection comprising means for performing the method of any of Examples 9 to 14.
In Example 18, a system for frequency throttling comprises a processor, and an external memory coupled to the processor. The processor may include a plurality of processing engines and a throttling circuit. The throttling circuit may be to: detect an execution of a pause instruction in a first processing engine; in response to a detection of the execution of the pause instruction, increment a counter to count a number of cycles that the first processing engine is paused by the execution of the pause instruction; and in response to a determination that the counter has reached a first threshold level, reduce an operating frequency of the first processing engine to a first reduced frequency level; and
In Example 19, the subject matter of Example 18 may optionally include that the throttling circuit is to: determine whether the counter has reached the first threshold level; and maintain the operating frequency of the first processing engine responsive to a determination that the counter has not reached the first threshold level.
In Example 20, the subject matter of Examples 18-19 may optionally include that the throttling circuit is to: determine whether the first processing engine is still paused by the pause instruction; and in response to a determination that the first processing engine is no longer paused by the pause instruction, increase the operating frequency of the first processing engine.
In Example 21, the subject matter of Examples 18-20 may optionally include that the throttling circuit is to: determine whether the counter has reached a second threshold level; and in response to a determination that the counter has reached the second threshold level, reduce the operating frequency of the first processing engine from the first reduced frequency level to a second reduced frequency level.
In Example 22, the subject matter of Examples 18-21 may optionally include that the throttling circuit is to: increment the counter to count the number of cycles that the first processing engine and a second processing engine of the processor are both paused by pause instructions; and in response to the determination that the cycle counter has reached the first threshold level, reduce the operating frequencies of the first processing engine and the second processing engine.
In Example 23, the subject matter of Examples 18-22 may optionally include that the throttling circuit is included in a power control unit of the processor, where the power control unit and the first processing engine are separate components of the processor.
In Example 24, an apparatus for frequency throttling comprises: means for detecting a pause instruction in a first processing engine of the processor; means for, in response to a detection of the pause instruction, adjusting a cycle counter to count a number of cycles that the first processing engine is paused by an execution of the pause instruction; means for determining that the cycle counter has reached a first threshold level; and means for, in response to a determination that the cycle counter has reached the first threshold level, reducing an operating frequency of the first processing engine to a first reduced frequency level.
In Example 25, the subject matter of Example 24 may optionally include:
In Example 26, the subject matter of Examples 24-25 may optionally include means for, in response to determining that the cycle counter has not reached the first threshold level, maintaining the operating frequency of the first processing engine.
In Example 27, the subject matter of Examples 24-26 may optionally include: means for, after reducing the operating frequency to the reduced frequency level, determining whether the cycle counter has reached a second threshold level; and means for, in response to a determination that the cycle counter has reached the second threshold level, reducing the operating frequency of the first processing engine from the first reduced frequency level to a second reduced frequency level.
In Example 28, the subject matter of Examples 24-27 may optionally include: means for adjusting the cycle counter to count the number of cycles that the first processing engine and a second processing engine of the processor are both paused by pause instructions; and means for, in response to a determination that the cycle counter has reached the first threshold level, reducing the operating frequencies of the first processing engine and the second processing engine.
In Example 29, the subject matter of Examples 24-28 may optionally include: means for executing the pause instruction by the first processing engine; and means for, in response to an execution of the pause instruction, delaying an execution of a next instruction execution by the first processing engine for a defined time period.
In Example 30, the subject matter of Examples 24-29 may optionally include that the pause instruction is included in a spin-wait loop of program code executed by the first processing engine.
It is contemplated that various combinations of the above examples are possible. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application. As used herein, “in response to” refers to a direct cause-and-effect relationship.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
