Patent Application
20120260063
The present invention relates to computing systems, and more particularly, to an individual, removably detachable compute module leaf for use in the formation of 3-D replaceable compute modules.
As computers have gained processing speed and circuit count over time according to Moore's Law, computer footprints and signal paths have become smaller. Speeds have increased to the point that the distances between connection points constrain the parallel computing device, causing it to waste processing cycles while the central processing unit or units wait for responses to queries. In an interconnected multiprocessing node supercomputer, that can cause problems with the execution of the desired program. With ever increasing processing core clock cycle speeds, designers have to take into account electrical signal propagation (i.e., the speed of light) in their design of circuitry inside processing nodes in a multiprocessor supercomputer. The packaging of a multiple node supercomputer also must keep up with the density of both physical properties and electrical properties.
As computer devices have become more complex and miniaturized, the ability to repair the devices has become more complex also. The energy density and cooling capacity requirements of the current generation of high speed computing devices place great emphasis on the design for repair or replacement of the modules that make up the complete device.
A supercomputer is at the front line of current processing capacity, particularly speed of calculation. Supercomputers, introduced in the 1960s, were designed primarily by Seymour Cray at Control Data Corporation (CDC), and later at his own company, Cray Research. Today, supercomputers are typically one-of-a-kind custom designs produced by traditional companies such as Cray, IBM and Hewlett-Packard. The Cray XT5 Jaguar, located at Oak ridge National Laboratory, is the fastest supercomputer in the world currently.
The term supercomputer itself is rather fluid. Today's supercomputer tends to become tomorrow's ordinary computer. CDC's early machines were simply very fast scalar processors, some ten times the speed of the fastest machines offered by other companies. In the 1970s most supercomputers were dedicated to running a vector processor, and many of the newer companies developed their own such processors. In the early and mid-1980s, machines with a modest number of vector processors working in parallel became the standard. Typical numbers of processors were in the range of four to sixteen. In the later 1980s and 1990s, attention turned from vector processors to massive parallel processing systems with thousands of “ordinary” CPUs, some being off the shelf units and others being custom designs. Parallel designs currently are based on off the shelf server-class microprocessors. Most modern supercomputers are now highly tuned computer clusters using commodity processors combined with custom interconnects.
Massively parallel computing structures (also referred to as “ultra-scale computers”) interconnect large numbers of compute nodes, generally in the form of very regular structures, such as grids, lattices or torus configurations. The conventional approach for the most cost/effective ultra-scale computers has been to use standard processors configured in uni-processors or symmetric multiprocessor (SMP) configurations, wherein the SMPs are interconnected with a network to support message passing communications. Today, these supercomputing machines exhibit computing performance achieving teraOPS-scale.
The semiconductor devices used in computers and similar items are typically provided with a high density of electrical contacts on one surface, arranged in a patterned array with constant dimensions and a small spacing or pitch between the centers of the contacts. The contacts may consist of patterned pads or bumps.
Historically, in first level packaging the chips were mounted on a rigid carrier with matching electrical contacts, encapsulated and hermetically sealed in metal or plastic packages. The carrier redistributed the electrical contacts over a larger area and made it compatible for mounting on a printed circuit board (PCB) or printed wiring board (PWB) known as second level packaging. Conventionally, the electrical connection between the chip and carrier in the first level package has been permanent by means of solder, wirebond and similar processes, and not amenable to easy removal or reworking. The second level interconnections of the carrier to the PWB have similarly been permanent or at best difficult to rework via solder.
Using conventional interconnection methods give rise to a number of problems. The mismatch in the coefficient of thermal expansion (CTE) of the chip substrate, usually silicon, and the carrier result in stress build-up during the assembly process and during operation of the device. Rigid carriers similarly acquire and retain residual stress during second level assembly. Such stress often leads to the early failure of the electrical contacts either at the first or the second level interconnections.
Secondly, problems associated with rigid and flexible carriers can be related to testing, burn-in, and removal/reworking of interconnects. The devices require firm, reliable electrical/ohmic contacts with the carrier and PWB during testing and burn-in. However the process also demands easily detachable chip-to-carrier or carrier-to-PWB joints, should the device or the electrical interconnects be found defective. Conventional rework methods introduce additional thermal cycles on the assembly and often damage the device or the PWB.
U.S. Pat. No. 5,207,585, issued May 4, 1993 to Byrnes et al., for THIN INTERFACE PELLICLE FOR DENSE ARRAYS OF ELECTRICAL INTERCONNECTS, discloses a thin interface pellicle probe for making temporary or permanent interconnections to pads or bumps on a semiconductor device. The pads or bumps may be arranged in high-density patterns incorporating an electrode for each pad or bump. The electrode has a raised portion for penetrating the surface of the pad or bump to create sidewalls to provide a clean contact surface. The electrode has a recessed surface to limit the penetration of the raised portion. The electrodes may be affixed to a thin flexible membrane to permit each contact to have independent movement over a limited distance and of a limited rotation.
U.S. Pat. No. 6,242,282, issued Jun. 5, 2001 to Fillion et al., for CIRCUIT CHIP PACKAGE AND FABRICATION METHOD, discloses a method for packaging at least one circuit chip that includes providing an interconnect layer including insulative material. The initial metallization pattern contains at least one substrate via extending the through the material to connect metallized portions, and at least one chip via connected. Positioning at least one circuit chip on the substrate with a chip pad of the circuit chip being aligned with the chip via. Patterning the connection metallization on selected portions of the interconnect layer and in the vias so as to extend to the second metallized portion and to the chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder.
U.S. Pat. No. 6,156,484, issued Dec. 5, 2000 to Bassous et al., for GRAY SCALE ETCHING FOR THIN FLEXIBLE INTERPOSER, discloses a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer. Probe pads are used for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a fixture for holding the substrate and a mask for 1-step photolithographic exposure.
U.S. Pat. No. 6,618,941, issued Sep. 16, 2003, to Campbell et al., for METHOD OF FORMING FREESTANDING METAL DENDRITES, discloses a technique for making acicular, branched, conductive dendrites, and a technique for using the dendrites to form a conductive compressible pad-on-pad connector. To form the dendrites, a substrate is provided on which dendrites are grown, preferably on a metal film. The dendrites are then removed from the substrate, preferably by etching metal from the substrate. The so-formed dendrites are incorporated into a compressible dielectric material, which then forms a compressible pad-on-pad connector between two conducting elements, such as connector pads on electrical devices, e.g. an I/C chip mounted on a substrate, such as a chip carrier.
U.S. Pat. No. 5,137,461, issued Aug. 11, 1992, to Bindra et al., for SEPARABLE ELECTRICAL CONNECTION TECHNOLOGY, discloses a separable and reconnectable connection for electrical equipment that is suitable for miniaturization. Vertical interdigitating members are integrally attached and protrude from a planar portion. These members are accommodated in the control of damage during lateral displacement that occurs on mating with an opposite similar contact. Displacement damage is averted through accommodating lateral stresses by providing one or more of a conformal opposing contact and by strengthening through coating and base reinforcement and a deformable coating. The contacts are provided with a surrounding immobilizing material that enhances rigidity.
U.S. Pat. No. 7,555,566, issued Jun. 30, 2009 to Blumrich, et al., for MASSIVELY PARALLEL SUPERCOMPUTER, describes a massively parallel supercomputer of hundreds of teraOPS-scale that includes node architectures based upon system-on-a-chip technology. Each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit and a plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that maximize packet communications throughput and minimize latency.
It is therefore an object of the invention to provide an interconnection method for an individual processing leaf as part of a larger module to optimally achieve maximum levels of connectivity without the permanent joining of interconnections within a supercomputing architecture.
It is another object of the invention to provide an interconnection method for an individual processing leaf as part of a larger module to achieve maximum grouping flexibility of module clusters within a supercomputing architecture.
It is still yet another object of the invention to provide an interconnection method for an individual processing leaf as part of a larger module that is designed for uncomplicated upgrading/replacement within a supercomputing architecture.
The present invention is directed to a removable, modular logic leaf that is part of a scalable compute system having a midplane for interconnecting electrical components and a controller concentrator having means for communication among a plurality of modular logic leaves. The logic leaf connector is removable with no need for solder softening thermal cycles, or special tools, and permits the simple removal or replacement of an individual leaf at any time.
The objects and advantages of the present invention will become more readily apparent to those skilled in the art after reviewing the following detailed description and the accompanying drawings, wherein:
For the sake of clarity and brevity, like elements and components of each embodiment will bear the same designations throughout the description. The drawings show an embodiment that has four equal sides of a detachable compute module, therefore like elements are not individually designated throughout single figures.
Generally speaking, the present invention is a high speed and high-density computing system endowed with removable and detachable modular logic leaves that facilitate the field replacement and upgrade of individual modules, both at initial assembly and after deployment in the field.
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims.
By the term “circuitized substrate” as used herein is meant a substrate structure having at least one (and preferably more) dielectric layer and at least one external conductive layer positioned on the dielectric layer and including a plurality of conductor pads as part thereof. The conductive layers preferably serve to conduct electrical signals, including those of the high frequency type, and is preferably comprised of suitable metals such as copper, again, as this is the thrust of this application.
By the term “electroplating” as used herein is meant a process by which a metal in its ionic form is supplied with electrons to form a non-ionic coating on a desired substrate. The most common system involves: a chemical solution which contains the ionic form of the metal, an anode (positively charged) which may consist of the metal being plated (a soluble anode) or an insoluble anode (usually carbon, platinum, titanium, lead, or steel), and finally, a cathode (negatively charged) where electrons are supplied to produce a film of non-ionic metal.
By the term “electroless plating” (also known as chemical or auto-catalytic plating) as used herein is meant a non-galvanic type of plating method that involves several simultaneous reactions in an aqueous solution, which occur without the use of external electrical power. The reaction is accomplished when hydrogen is released by a reducing agent, normally sodium hypophosphite, and oxidized thus producing a negative charge on the surface of the part.
By the term “electronic package” as used herein is meant a circuitized substrate assembly as taught herein having one or more ICs (e.g., semiconductor chips) positioned thereon and electrically coupled thereto. In a multi-chip electronic package, for example, a processor, a memory device and a logic chip may be utilized and oriented in a manner designed for minimizing the limitation of system operational speed caused by long connection paths. Some examples of such packages, including those with a single chip or a plurality thereof, are also referred to in the art as chip carriers.
By the term “etch” and “etching” as used herein is meant a process by where a surface of a substrate is either selectively etched using a photoresist or covered by a mask prior to plasma treating, both methods are meant to transfer an image onto the substrate for subsequent further processing.
By the term “information handling system” as used herein is meant any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as computer servers and mainframes. Such products are well known in the art and are also known to include PCBs and other forms of circuitized substrates as part thereof, some including several such components depending on the operational requirements thereof.
By the term “laser ablation” as used herein is meant the process of removing material from a solid surface by irradiating it with a laser beam. At low laser flux, the material is heated by the absorbed laser energy and evaporates or sublimes. At high laser flux, the material is typically converted to a plasma. The term laser ablation as used herein refers to removing material with a pulsed laser as well as ablating material with a continuous wave laser beam if the laser intensity is high enough.
By the term “thru-hole” as used herein is meant to include what are also commonly referred to in the industry as blind vias which are openings typically from one surface of a substrate to a predetermined distance therein, internal vias which are vias or openings located internally of the substrate and are typically formed within one or more internal layers prior to lamination thereof to other layers to form the ultimate structure, and plated thru-holes (PTHs), which typically extend through the entire thickness of a substrate. All of these various openings form electrical paths through the substrate and often include one or more conductive layers, e.g., plated copper, thereon. Alternatively, such openings may simply include a quantity of conductive paste or, still further, the paste can be additional to plated metal on the opening sidewalls. These openings in the substrate are formed typically using mechanical drilling or laser ablation, following which the plating and/or conductive paste may be added.
The current embodiment of the invention allows for removable and detachable logic leaves to be joined to a compute module cluster interface board using a flexible, reusable, dendritic connector.
Referring now to
Memory 85 is dedicated to serving the local processors 75, of which the processor 75 can be FPGA/ASIC type, and power supplies 80 are shown arrayed on a direct chip attach (DCA)-Z Interconnect 65 such that individual detachable logic leaves 100 are similar and consistent in structure. Flex lead 110 encompasses power, signal, and ground wires for transmission of power and communications the various devices resident on DCA-Z Interconnect 65.
Computer module cluster interface board 50 has electrical and optical connectors 55 that allow the interface of the midplane 130 to compute module 70 and facilitates the installation and removal of compute module 70. The flex lead 110 connects the computer module cluster interface board 50 to the DCA-Z Interconnect 65 by means of flexible substrate that encompasses power, signal, and ground wires to allow DCA-Z Interconnect 65 and associated components to move in an upward arc to contact coolant filled heat transfer block 115 to promote the conduction of heat away from processors 75 and power supply 80.
The flex leads 110, by folding in the aforementioned manner, allow a denser packing of compute module 70 and a compact footprint, thereby enabling more processing power per unit of volume. This allows the processors 75 to run at a higher processing frequency, thereby permitting more clock cycles per unit of time to allow more throughput on processor 75. The coolant filled heat transfer block 115 removes the heat generated by the processors 75 and power supplies 80 in normal operation and allows closer physical placement within a system than would be allowable using convection cooling only. Not shown in the views is a hollow transom containing coolant inlets and outlets for the movement of a coolant to and from coolant filled heat transfer block 115.
As stated, each flexible substrate formed in accordance with the teachings herein may be utilized within a larger substrate of known type such as a PCB, chip carrier or the like.
In
This completed assembly, hidden in
Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, this invention is not considered limited to the example chosen for purposes of this disclosure, and covers all changes and modifications which does not constitute departures from the true spirit and scope of this invention.
Having thus described the invention, what is desired to be protected by Letters Patent is presented in the subsequently appended claims.
