Patent Application
20150358029
1. Field of the Invention
The present inventive concept relates to modulation circuits and modulation methods. More particularly, the inventive concept relates to modulation circuits and modulation methods with digital excess loop delay (ELD) compensation for delta-sigma modulators (DSM).
2. Description of the Related Art
Generally, DSMs are widely utilized in audio applications. As semiconductor manufacturing technology develops, digital circuits increasingly have the advantages of smaller sizes and lower power consumption. However, the size of analog circuits is still limited by stringent design considerations such as flicker noise, device matching, and additional layout rules. Furthermore, within the DSM, the later stages (such as the second stage and the third stage) and the quantizer occupy a large circuit area.
Accordingly, it is desired to replace analog circuits with equivalent digital circuits whenever possible to reduce the circuit area. However, when the later stages are implemented by digital circuits, it would need to feedback immediately without delay. A big flash quantizer would also be required. In addition, when the ELD compensation is utilized, it would be limited and cannot be utilized to compensate for the signal delay with any bits of code or any value of gain.
Therefore, there is a need in the art to address at least some of the issues associated with reduced circuit area, feedback latency, or ELD compensation.
The present invention provides a modulation circuit including a digital quantizer and a compensation circuit. The digital quantizer is utilized to receive and truncate a digital quantizing input signal for generating a digital quantizing output signal. The compensation circuit couples to the digital quantizer. The compensation circuit is utilized to compensate for a time delay of the modulation circuit and generate a compensation output signal. The digital quantizing input signal is generated by subtracting the compensation output signal from a digital integration output signal to compensate for the time delay before truncating the digital quantizing input signal.
The present invention provides a modulation circuit including an analog quantizer and a processing circuit. The analog quantizer receives a first input signal for generating a first digital input signal and receives a second input signal for generating a second digital input signal. The first input signal and the second input signal are generated in different channels. In addition, the processing circuit is coupled to the analog quantizer for compensating a time delay of the modulation circuit. The processing circuit truncates the first digital input signal to generate a first truncation signal after the time delay is compensated for, and truncates the second digital input signal to generate a second truncation signal after the time delay is compensated for.
The present invention provides modulation method utilized for a modulation circuit. The modulation method comprises compensating a time delay of the modulation circuit by receiving an output signal and generating a compensation output signal; generating a digital quantizing input signal by subtracting the compensation output signal from a digital integration output signal; truncating and quantizing the digital quantizing input signal to generate a digital quantizing output signal, and compensating the time delay is executed before truncating and quantizing the digital quantizing input signal; and adding a truncation noise to the digital quantizing output signal to generate the output signal.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
The following description is of the best-contemplated operation of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. Certain terms and figures are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. The terms “component”, “system” and “device” used in the present invention could be the entity relating to the computer which is hardware, software, or a combination of hardware and software. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
In one embodiment, the analog integrator 120 is arranged on the analog stage 100A and connected to the adder 110A to receive and integrate the signal S2 for generating the signal S3 (the analog quantizing input signal). Afterwards, the analog quantizer 122 is arranged on the analog stage 100A, connected to the analog integrator 120 and triggered by a clock signal CK for sampling, converting and quantizing the signal S3 (the analog quantizing input signal) into a signal S4 (the digital conversion signal). The analog quantizer 122 digitizes or quantizes the signal S3 at the falling edge of the clock signal CK. For example, the analog quantizer 122 is an analog-to-digital converter. More specifically, the analog quantizer 122 is a 6-bit asynchronous successive approximation register (ASAR) analog-to-digital converter.
As shown in
In one embodiment, the digital quantizer 152 is arranged on the digital stage 100B and utilized to receive and truncate the signal S7 for generating the signal S8 (the digital quantizing output signal). As shown in
Furthermore, the modulation circuit 100 includes the adder 110D (the second adder) which is arranged on the digital stage 100B and connected between the digital quantizer 152 and the compensation circuit 154. The adder 110D is utilized to add a truncation noise SN2 to the signal S8 to generate the signal SOUT (the output signal). It should be noted that the truncation noise SN2 is suppressed by the analog integrator 120, the digital integrator 150 and/or the digital quantizer 152. In addition, the digital-to-analog converter 124 is arranged on the analog stage 100A and connected between the adders 110A and 110D. The digital-to-analog converter 124 is triggered by the clock signal CK to convert the signal SOUT and generate the signal S10 (the analog output signal). Specifically, the digital-to-analog converter 124 operates or converts the signal SOUT at the rising edge of the clock signal CK.
Since the digital quantizer 152 and the compensation circuit 154 are both arranged on the digital stage 100B and the signal of the modulation circuit 100 is compensated for before being truncated by the digital quantizer 152, the modulation circuit 100 has the advantage of compensating for the signal delay with any bits of code or any value of gain. Compared with the compensation of limited gain, the compensation with any bits of code or any value of gain of the present invention provides a better compensating effect and a more stable circuit performance. In addition, another advantage of the modulation circuit 100 is that it does not need to feed back immediately. For example, in one embodiment, a delay of half of the clock period is allowed for the analog quantizer 122 and the digital stage 100B. The reason is that the time delay is lumped after the analog quantizer 122. Furthermore, an arbitrary and direct feedback gain can be derived accordingly for the ELD compensation by the compensation circuit 154. The feedback path is on the digital stage 100B, and it only takes effect in the next sample to justify the derivation. Therefore, the feedback latency is allowed in the modulation circuit 100 of the present invention.
Furthermore, on the one hand, by adopting the analog stage 100A as the first stage, it takes advantage of better anti-aliasing attenuation than a digital implementation and being more robust against interference in a system-on-chip (SoC) environment. On the other hand, the compensation circuit 154 is arranged on the digital stage 100B rather than the analog stage 100A. Therefore, the chip area can be reduced since the digital device uses a smaller area than the analog device. As a result, the modulation circuit 100 of the present invention exploits the benefits of both analog and digital circuits and also provides the advantages of a reduced circuit area, feedback latency and digital ELD compensation.
Afterwards, the analog quantizer 230 receives and quantizes the signal S1 for generating a signal S3 (the first digital input signal), and it also receives and quantizes the signal S2 for generating a signal S4 (the second digital input signal). In addition, the processing circuit 260 is arranged on the digital stage 200B and coupled to the analog quantizer 230 for compensating a time delay of the modulation circuit 200. For example, the analog quantizer 230 is an ASAR. Instead of utilizing two analog quantizers for implementing the two channels, the shared analog quantizer 230 could provide better integration and better power efficiency. In addition, the analog quantizer 230 is triggered by the first clock signal CK1 and the second clock signal CK2 which is different from the first clock signal CK1. In one embodiment, the analog quantizer 230 computes or quantizes the signal S1 with the first clock signal CK1, and it computes or quantizes the signal S2 with the second clock signal CK2. In another embodiment, the analog quantizer 230 is triggered by only one clock signal, and it quantizes the signal S1 with the rising edge of the clock signal and quantizes the signal S2 with the falling edge of the clock signal. For example, the analog quantizer 230 is a 6-bit ASAR operated at 24 MHz sampling rate to accomplish a complete conversion including sampling and computing in a clock cycle. For another example, the analog quantizer 230 is operated at a double sampling rate of 48 MHz to convert and quantize the signals S1 and S2 in a sequential manner. Specifically, the analog quantizer 230 is switched to the right channel after it completes the conversion for the left channel, and vice versa.
In one embodiment, the processing circuit 260 is utilized to truncate the signal S3 to generate a signal S5 (the first truncation signal) after the time delay is compensate for, and truncate the signal S4 to generate a signal S6 (the second truncation signal) after the time delay has been compensated for. Specifically, the processing circuit 260 includes a first digital processing unit 260A and a second digital processing unit 260B. The first digital processing unit 260A includes the first digital integrator 262 for filtering and the first digital quantizer 264 for the truncation. The second digital processing unit 260B includes the second digital integrator 266 for filtering and the second digital quantizer 268 for the truncation. As shown in
In addition, the modulation circuit 200 includes a first digital-to-analog circuit 220 and a second digital-to-analog circuit 222 which are arranged on the analog stage 200A. The first digital-to-analog circuit 220 is connected to the analog quantizer 230 and input by the first clock signal CK1 to convert the signal S5. The second digital-to-analog circuit 222 is connected to the analog quantizer 230 and input by the second clock signal CK2 to convert the signal S6. In one embodiment, the modulation circuit 200 further includes a first dynamic match circuit 250 and a second dynamic match circuit 252 which are arranged on the digital stage 200B. Specifically, the first dynamic match circuit 250 is coupled between the first digital-to-analog circuit 220 and the first digital processing circuit 260A to improve linearity of the signal S5. The second dynamic match circuit 252 is coupled between the second digital-to-analog circuit 222 and the second digital processing circuit 260B to improve linearity of the signal S6.
In one embodiment, the modulation method further includes converting the output signal to generate an analog output signal which is executed on the analog stage, subtracting the analog output signal from an input signal to generate an analog input signal which is executed on the analog stage, and integrating the analog input signal to generate an analog quantizing input signal which is executed on the analog stage. In another embodiment, the modulation method further includes converting the analog quantizing input signal into a digital conversion signal which is executed on the analog stage, adding a quantization noise to the digital conversion signal to generate a digital input signal which is executed on the analog stage, and receiving and integrating the digital input signal to generate the digital integration output signal which are executed on the digital stage.
The modulation circuit provided by the present invention is featured by an analog first stage and a digital second stage including a digital ELD compensation. The analog stage rejects the noise aliased by the sampling analog quantizer, and the following digital stage has the advantage of small size. In addition, the ELD is compensated for on the digital stage before the signal truncation to provide a better compensation with unrestricted gains. Accordingly, the feedback latency is allowed in the proposed modulation circuit. Moreover, the analog quantizer could be shared for dual-channel operations. This proposed hybrid modulation circuit enables the circuit area to be scaled down with advanced CMOS process technology.
Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
This application claims the benefit of U.S. Provisional Application No. 62/009,979, filed on Jun. 10, 2014, the entirety of which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 62009979 | Jun 2014 | US |
