Patent Application
20080316071
This invention relates to a method of converting a user bitstream into a coded bitstream by means of a channel code where the channel code has a constraint of d=1, to a coder for converting a user bitstream into a coded bitstream by means of a channel code where the coder comprises processing device for applying a channel code with the constraint of d=1, to a recording device comprising such a coder, to a record carrier comprising a track comprising a signal comprising a user bitstream coded in a coded bitstream by means of a channel code where the channel code has the constraint of d=1, to a bit detector for performing bit detection on a code bitstream comprising a user bitstream coded in a coded bitstream by means of a channel code where the channel code has the constraint of d=1, and to a playback device comprising such a bit detector.
At very high densities for a d=1 constrained storage system (e.g. capacities on a 12 cm disc of 33-37 GB, well beyond the 25 GB of Blu-ray Disc), consecutive 2T runs are the Achilles' heel for the bit-detection. Such sequences of 2T runs bounded by larger runlengths at both sides, are called 2T-trains. Therefore, it turns out to be advantageous to limit the length of such 2T-trains. This is a general observation, and is not new as such. Currently, the 17PP code of BD as disclosed by T. Narahara, S. Kobayashi, M. Hattori, Y. Shimpuku, G. van den Enden, J. A. H. M. Kahlman, M. van Dijk and R. van Woudenberg, in “Optical Disc System for Digital Video Recording”, Jpn. J. Appl. Phys., Vol. 39 (2000) Part 1, No. 2B, pp. 912-919. has a so-called RMTR constraint (Repeated Minimum Transition Runlength) of r=6, which means that the number of consecutive minimum runlengths is limited to 6 or, stated differently, the maximum length of the 2T-train is 12 channel bits. The 17PP code is based on the parity-preserve principle as disclosed in U.S. Pat. No. 5,477,222.
In the literature, the RMTR constraint is often referred to as the MTR constraint. Originally, the maximum transition-run (MTR) constraint as introduced by J. Moon and B. Brickner, in “Maximum transition run codes for data storage systems”, IEEE Transactions on Magnetics, Vol. 32, No. 5, pp. 3992-3994, 1996, for a d=0 case, specifies the maximum number of consecutive “1”-bits in the NRZ bitstream where a “1” indicates a transition in the bi-polar channel bitstream. Equivalently, in the NRZI bitstream, the MTR constraint limits the number of successive 1T runs. As argued above, the MTR constraint can also be combined with a d-constraint, in which case the MTR constraint limits the number of consecutive minimum runlengths as is the case for the 17PP code. The basic idea behind the use of MTR codes is to eliminate the so-called dominant error patterns, that is, those patterns that would cause most of the errors in the partial response maximum likelihood (PRML) sequence detectors used for high density recording. A highly efficient rate 16→17 MTR code limiting the number of consecutive transitions to at most two for d=0 has been described in T. Nishiya, K. Tsukano, T. Hirai, T. Nara, S. Mita, “Turbo-EEPRML: An EEPRML channel with an error correcting post-processor designed for 16/17 rate quasi MTR code”, Proceedings Globecom '98, Sydney, pp. 2706-2711, 1998.
It is an objective of the present invention to provide a method of converting a user bitstream into a coded bitstream by means of a channel code that improves the performance of the bit-detector.
To achieve this object the method of converting a user bitstream into a coded bitstream by means of a channel code is characterized in that the channel code has an additional constraint of r=2.
Within the scope of a code-rate of R=⅔ for d=1 the minimum RMTR constraint that is still possible is r=2. It turned out that r=2 results in a improved bit-detection performance. Thus, for exactly the same rate as the 17PP code, a maximally improved RMTR constraint and correspondingly improved bit-detection performance is obtained.
In addition another advantage is achieved by applying the RMTR constraint, which is a limitation of the back-tracking depth (or trace-back depth) of a Viterbi (PRML) bit-detector when such a detector is used on the receiving/retrieving side.
Performance gain due to the RMTR constraint has been studied experimentally for high-density optical recording channels derived from the Blu-ray Disc (BD) system. Experiments have been performed using the increased-density BD rewritable system with the disc capacity increased from the standard 23.3-25-27 GB to 37 GB. This particular experimental platform has been chosen because of the plans for standardization of an increased-density system derived from the current Blu-ray Disc standard. PRML (Viterbi) bit detection has been employed. Moreover, next-generation high-numerical-aperture near-field optical recording systems will likewise profit from the improved bit-detection performance that is offered by channel codes that have the r=2 constraint.
Performance of the Viterbi bit detector has been measured based on the sequenced amplitude margin (SAM) analysis. SAM analysis allows computing the error probability (SAMEP) at the output of the Viterbi detector as well as calculation of the SAM-based pre-detection signal-to-noise ratio (SAMSNR) defined as
SAMSNR=20*log10(√{square root over (2)}*erfinv(1−2*SAMEP)) [dB].
SAMSNR proved to be a useful performance measure since it can be related to the potential capacity gain. Namely, in the relevant range of capacities around 35 GB, 1 dB gain in SAMSNR means almost 6% disc capacity increase.
Channel codes with different RMTR constraints (r=1, r=2, r=3 and r=6) have been compared to each other. (Note that the r=1 constraint is the only one that cannot be realized with a rate R=⅔ code; a rate R= 16/25 is assumed instead.) In order to separate read-channel performance gain due to the imposed RMTR constraint from the corresponding write-channel gain, two different Viterbi bit detectors have been used: one which is aware of the RMTR constraint, and the other which is not. In the second case the performance gain can be attributed solely to the improved spectral content of the data written on the disc (such that it is better matched to the characteristics of the write channel used).
When the 17PP channel code with the RMTR constraint r=6 (as used in the BD system) is employed, SAMSNR of 11.66 dB is achieved for both RMTR-aware and RMTR-unaware bit detectors, i.e. no RMTR-related performance gain is observed in the read channel. When the channel code with r=3 is used, SAMSNR of 11.87 dB and 11.72 dB are achieved for the RMTR-aware and RMTR-unaware bit detectors correspondingly. As one can see, in both write and read channels, RMTR-related SAMSNR increase of about 0.15 dB is gained with respect to the case of r=6, leading to a total SAMSNR gain of about 0.3 dB. The channel code with r=2 leads to an even greater SAMSNR improvement with respect to r=6: SAMSNR of 12.07 dB and 12.55 dB are achieved for the RMTR-aware and RMTR-unaware bit detectors correspondingly, which means a total SAMSNR gain of about 0.9 dB. Decreasing the RMTR further from r=2 to r=1 does not lead to any significant SAMSNR gain. To the contrary, the overall system performance is deteriorated because of the increased code rate loss for the case of r=1 as is discussed in the following discussion.
For d=1 and RMTR r=2, the theoretical capacity amounts to:
C(d=1,k=∞,r=2)=0.679289. (1)
So, a code with rate ⅔ is still feasible. For an even more aggressive RMTR constraint r=1, the theoretical capacity amounts to:
C(d=1,k=∞,r=1)=0.650902. (2)
Clearly, a practical code with rate ⅔ for r=1 is thus not possible. As shown by the experimental results, no performance gain is observed by going from r=2 to r=1, since 2T trains of length 1 and 2 are clearly distinguishable by the Viterbi bit-detector (intuitively by looking at the polarity at the longer runlengths at both sides of the short 2T-train). Therefore, the following derivation focuses on the case r=2, for which we can achieve the same code rate as the 17PP code of BD, with RMTR r=6.
It is thus shown that a code with constraints d=1 and r=2 provides improved performance which can be used to obtain an increase in disc capacity or an increase in the reliability of the bit detection by allowing a gain of almost 1 dB (in fact 0.9 dB), i.e. about 5% disc capacity increase.
Detailed description of a code with d=1 and an RMTR Constraint r=2.
A new d=1 parity-preserving RLL code with identical code-rate as 17PP (R=⅔) and with the minimum RMTR constraint possible (r=2) is proposed so that the bit-detection performance can be improved: the improvement can be quantified as 0.9 dB of (SAM) SNR, or, equivalently, about 5% of capacity in the capacity range of 35 GB for a BD system.
The following additional properties of the channel code can also to be realized, based on the ACH algorithm as disclosed by R. L. Adler, D. Coppersmith, and M. Hassner, in “Algorithms for Sliding Block Codes. An Application of Symbolic Dynamics to Information Theory”, IEEE Transaction on Information Theory, Vol. IT-29, 1983, pp. 5-22., a well-known technique for the construction of a sliding block code with look-ahead decoding:
First, the mathematical procedure for the ACH-based code-construction will be outlined for the specific case of codes with the parity-preserve property. Subsequently, two particular codes will be discussed, that have been designed according to this construction method: one code has runlength constraints d=1, k=12 and r=2, the other has runlength constraints d=1, k=10 and r=2. Both codes have an 8-to-12 mapping, meaning that bytes of user information are encoded onto 12-bit channel words. Because of the larger k-constraint of the first code, the required amount of so-called state-splitting in the ACH algorithm will be less than for the second code with the more tight k=10 constraint: this is reflected by the fact that the maximum component of the approximate eigenvector equals 5 and 8 for the first and the second code, respectively. It should be noted that, for the same 8-to-12 mapping, an even lower value for the k-constraint, k−9, is possible within the assumed boundary conditions (8-to-12 mapping, PP-property), but would require a 28-fold state-splitting in the ACH-algorithm, which leads to increased error propagation for such a code.
In order to explain the ACH-based code-construction of parity-preserving codes, the construction of a code using a combi-code construction is outlined.
In US-patent U.S. Pat. No. 6,469,645-B2, the concept of combi-codes has been disclosed. Additional information can be found in “Combi-Codes for DC-Free Runlength-Limited Coding”, Wim M. J. Coene, IEEE Transactions on Consumer Electronics, Vol. 46, No. 4, pp. 1082-1087, November 2000.
A combi-code for a given constraint consists of a set of at least two codes for that constraint, possibly with different rates, where the encoders of the various codes share a common set of encoder states. As a consequence, after each encoding step the encoder of the current code may be replaced by the encoder of any other code in the set, where the new encoder has to start in the ending state of the current encoder. Typically, one of the codes, called the standard code or main code, is an efficient code for standard use; the other codes serve to realise certain additional properties of the channel bitstream. Sets of sliding-block decodable codes for a combi-code can be constructed via the ACH-algorithm; here the codes are jointly constructed starting with suitable presentations derived from the basic presentation for the constraint and using the same approximate eigenvector. The construction of a Combi-Code satisfying the (dk) constraints is guided by an approximate eigenvector, see K. A. S. Immink, “Codes for Mass Data Storage Systems”, 1999, Shannon Foundation Publishers, The Netherlands and A. Lempel and M. Cohn, “Look-Ahead Coding for Input-Constrained Channels”, IEEE Trans. Inform. Theory, Vol. 28, 1982, pp. 933-937, and H. D. L. Hollmann, “On the Construction of Bounded-Delay Encodable Codes for Constrained Systems”, IEEE Trans. Inform. Theory, Vol. 41, 1995, pp. 1354-1378. The components of this vector indicate the amount of state-splitting needed in the ACH-algorithm as disclosed by R. L. Adler, D. Coppersmith, M. Hassner, in “Algorithms for Sliding Block Codes. An Application of Symbolic Dynamics to Information Theory”, IEEE Trans. Inform. Theory, Vol. 29, 1983, pp. 5-22. This algorithm has to be applied to the construction of the main code and the substitution code simultaneously.
The main code is denoted C1; it maps n-bit data words into m1-bit channel words, and can be constructed on the basis of an approximate eigenvector vi, i=1, . . . ,k+1 that satisfies the inequality:
Σj=1k+1Dijm
where the matrix D is a (k+1)×(k+1) matrix, known as the adjacency matrix or connection matrix for the state-transition diagram (STD) that describes (dk)-sequences.
For the substitution code, denoted C2, we derive a similar approximate eigenvector inequality, that takes the two properties of the substitution code into account: for each branch (or transition between coding states), there are two channel words with opposite parity and the same next-state. We enumerate separately the number of channel words of length m2 (leaving from state σi and arriving at state σj of the STD) that have even parity and the number of those words that have odd parity. We represent these numbers by DE[m2]ij and DO[m2]ij, respectively. For the substitution code, the enumeration does not involve single channel words, but word-pairs, where the two channel words of each word-pair have opposite parity and arrive at the same next-state σj of the STD. For this purpose, we define a new connection matrix for sequences of length m denoted by DEO[m] with the matrix elements:
D
EO
[m]
ij=Min[DE[m]ij, DO[m]ij]. (4)
A substitution code that maps n-bit data words into a set of two m2-bit channel words with the same next-state and with opposite parity, can be constructed on the basis of an approximate eigenvector vi, i=1, . . . , k+1 that satisfies the inequality:
Σj=1k+1DEO[m2]ijvj≧2nvi, i=1, . . . , k+1. (5)
For the construction of a Combi-Code, an approximate eigenvector must satisfy the inequalities (3) and (5) simultaneously. The requirement of a single approximate eigenvector for the main code and the substitution code enables a seamless transition from the main code to the substitution code and vice versa. Moreover, the same operation of merging-of-states (as needed in the ACH-algorithm) can be carried out for both codes.
Design Rules for a Parity-Preserving RLL Code by means of Relaxation of Design Rules for a Substitution Code for the case that the latter is only to be used as Parity-Preserve Code
The substitution code used alone, that is without standard code, is a parity-preserve code (which by definition maintains the parity between user words and channel words). This can be seen as follows. For each n-bit input word, the substitution code has two channel words with opposite parity, and the same next-state. The possible choice between the two channel words with opposite parity represents in fact one bit of information: hence, we could consider this as a n+1-to-m2 mapping (with m2 the length of the channel words). Precisely 2n input words and the corresponding channel words have even parity, and precisely 2n input words and the corresponding channel words have odd parity: thus the code as such is parity-preserving. Now, in the special case that we only use the substitution code (and thus no concatenation with a main code is required), the “same-next-state” property is not required at all, and can therefore be omitted. Therefore the joint design rule of Eq. (5) as required for a substitution code, can be relaxed for a parity-preserving code into the two independent design rules that have to be satisfied simultaneously by the aimed approximate eigenvector:
Σj=1k+1DE[m2]ijvj≧2nvi, i=1, . . . , k+1. (6)
and
Σj=1k+1DO[m2]ijvj≧2nvi, i=1, . . . , k+1. (7)
The above formulas Eq. (6) and Eq. (7) are crucial since they describe the recipe for the code-construction of parity-preserving codes on the basis of the ACH-algorithm. This is a quite unique code-construction method, since the latest review on d,k constrained channel codes by K. A. S. Immink (“Codes for Mass Data Storage Systems”, Second Edition, 2004, Shannon Foundation Publishers, Eindhoven) claims on page 290 that “ . . . it is not yet clear how we can efficiently design parity preserving codes with the ACH algorithm.” Obviously, the above code-construction has clarified the pending issue.
For the practical case considered here with the 8-to-12 parity-preserving RLL code, the parameters (with the definitions of above as used for the substitution code) are: d=1, r=2, k=12, n+1=8 and m2=12. Note that these parameters should not lead to any confusion here: the actual mapping of the code as a parity-preserve code is 8-to-12; the corresponding substitution code (if it would exist), would have a 7-to-12 mapping (with two channel words along the branches).
The invention will now be discussed based on FIGURES.
As a first example, an RLL code is disclosed with constraints: d=1, k=12 and r=2. The state-transition diagram (STD) for these RLL constraints is shown in
The approximate eigenvector for ACH-based construction of a sliding-block code with the parity-preserving property, and mapping 8-bit symbols onto 12-bit channel words, satisfying Eqs. (6-7) of the above code-construction, has been chosen as:
{3,5,5,5,5,5,5,4,4,4,3,3,0,2,4,2,3}. (8)
State-splitting according to the above approximate eigenvector, and subsequent state-merging leads to a final Finite-State Machine comprising 10 states. The code-tables are shown in the table III. The states are numbered from S0 to S 9. The code-words are listed by their decimal representation, with the MSB first (at left side of code-word). Channel words entering a given state are characterized by their specific word endings as indicated in Table I.
Note that the state-merging resulting into S0, S1 and S2 for all of the six first lines in the above table has made it possible to arrive at a 10-state FSM.
A sliding block code needs to decode the next-state of a given channel word in order to be able to uniquely decode said channel word. The next-state depends on the characteristics of the considered channel word (in particular the bits at the end of the word, as indicated in Table I), and a number of leading bits of the next channel word. The combination of a given channel word and its next state is sufficient to uniquely decode the corresponding source symbol. The “next-state” function for the latter discrimination has been realized in the coding tables according to a specific grouping (see Table II) with respect to the decimal representation.
Note that for a given channel word, at maximum 5 states (the maximum amount of state-splitting applied) can be possible “next-states” for that word. There are two sets, each of 5 states, that represent the maximum number of next-states (the 1 st set comprising S0, S1, . . . , S4, the 2nd set comprising S5, S6, . . . , S9). Note that the fan-out of all states in each of both sets is clearly separated into contiguous subsets of output words. Each subset is based on a range of decimal representations. Such a grouping of words in the fan-out of the states of the FSM limits error propagation. A similar ordering could of course be obtained based on a lexicographic ordering instead of the decimal ordering (which has some ‘gaps’ or missing words because of the RLL constraints).
DC control aspects.
Note that other measures for reducing the error-propagation that is caused by the insertion of DC-control bits into the source bitstream, prior to encoding, can also be combined with the currently proposed channel code. Such a measure is described by U.S. Pat. No. 6,265,994.
As a second example, an RLL code is disclosed with constraints d=1, k=10 and r=2. Compared relative to the state-transition diagram (STD) of
{5,8,8,8,8,8,7,7,6,5,3,4,7,3,5}. (9)
State-splitting according to the above approximate eigenvector, and subsequent state-merging leads to a final Finite-State Machine comprising 16 states. The code-tables are shown in the table IV. The states are numbered from S0 to S15. A sliding block code needs to decode the next-state of a given channel word in order to be able to uniquely decode said channel word. The next-state depends on the characteristics of the considered channel word, and a number of leading bits of the next channel word. The combination of a given channel word and its next state is sufficient to uniquely decode the corresponding user (or source) symbol.
| Number | Date | Country | Kind |
|---|---|---|---|
| 04104463.7 | Sep 2004 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/IB05/52956 | 9/9/2005 | WO | 00 | 3/12/2007 |
