FIELD
The present disclosure relates to power converters, and particularly to modulation of parallel-connected converters comprising converter bridges.
BACKGROUND INFORMATION
Power converters are being used in a large variation of applications. A power converter, such as a frequency converter, may comprise a converter bridge, and the output voltage of the converter may be controlled by controlling the operational states of power semiconductor switches in the converter bridge. FIG. 1 shows a simplified representation of an exemplary two-level, three-phase converter bridge of a frequency converter. The converter bridge in FIG. 1 is supplied through two DC terminals DC+ and DC− and generates three output phase voltages va, vb, and vc. The converter bridge comprises three converter legs 11a to 11c, each leg driving one of the phase voltages and comprising an upper power semiconductor switch 12, and a lower power semiconductor switch 13.
Converters comprising a converter bridge generate desired outputs by using pulse width modulation (PWM). For each converter leg of the converter bridge, the switches in the converter leg may be modulated between a conducting state and a non-conducting state in order to produce the desired phase voltage. For example, in FIG. 1, the two switches 12 and 13 of each leg may be controlled such that one of the switches is conducting and the other non-conducting. Thus, in principle (disregarding switching transitions), each converter leg can be in one of two operational states. Space vector modulation (SVM) is a carrierless PWM scheme. Space vector modulation can produce a high modulation index while maintaining a low total harmonic distortion (THD). The operational states of the switches of the converter bridge are controlled to form specified switching sets (i.e. a predefined combination of operational states of the switches). Each switching set represents a predefined output voltage vector, i.e. a space vector. The desired output voltage may be generated by controlling duty cycles of the space vectors.
In order to achieve a higher power rating, a plurality of power converters may be connected in parallel. The parallel-connected converters may be considered to operate as one large converter. Ideally, no additional components are required. However, in practice, additional inductances may have to be placed between the parallel phases in order to cope with possible timing or device characteristic mismatches.
BRIEF DISCLOSURE
An object of the present invention is to provide a method and an apparatus for implementing the method so as to alleviate the above disadvantages. The objects of the invention are achieved by a method and an arrangement which are characterized by what is stated in the independent claims. The preferred embodiments of the invention are disclosed in the dependent claims.
The present disclosure presents an efficient method for generating a multiplicity of duty cycle values for parallel-connected converters with converter bridges. The method involves using complementary switching sequences in the converters. Switching sequences of different converters may also be staggered so that the starting instants of the switching sequences have a set delay between each other. One set of base space vector duty cycles may be calculated for a reference vector. The reference vectors may be generated by any open loop or closed control method which generates a desired average output, typically a sinusoidally varying waveform.
A method according to the present disclosure the allows generation of turn-on and turn-off transition signals of the switches in the parallel-connected converter bridges from a single set of reference switching signals. The method may be implemented with minimum added complexity. Further, by using the complementary switching sequences, the effective output pulse frequency may be doubled without an increase in switching losses. With a higher effective output pulse frequency, the size of an output filter filtering the shared output of the parallel-connected converters may be reduced. The method is applicable for two-level converters and can be easily extended to multi-level converters.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following the invention will be described in greater detail by means of preferred embodiments with reference to the attached drawings, in which
FIG. 1 shows a simplified representation of an exemplary two-level, three-phase converter bridge;
FIG. 2 shows eight space vectors for the exemplary two-level, three-phase converter bridge of FIG. 1;
FIGS. 3a and 3b show exemplary switching sequences for sector 1 of FIG. 2;
FIG. 4 shows an example of the selection of the zero vectors on the αβ plane according to a discontinuous SVM scheme;
FIG. 5 shows an exemplary switching sequence according to a discontinuous SVM scheme;
FIG. 6 shows exemplary synchronized switching sequences of complementary sequence types for two converters;
FIG. 7 shows exemplary synchronized switching sequences of three converters where the sequences are initialized at set intervals;
FIG. 8 shows exemplary synchronized switching sequences of four converters;
FIG. 9 shows an exemplary arrangement controlling at least two parallel-connected, multi-phase power converters; and
FIG. 10 shows an exemplary, simplified implementation of the generation of first half sequences and second half sequences for a three-phase converter.
DETAILED DISCLOSURE
The present disclosure describes a modulation method for controlling at least two parallel-connected, multi-phase power converters, such as frequency converters. The power converters comprise a converter bridge. The method controls duty cycles of switching states of converter bridges in the power converters. The duty cycles may be determined on the basis of a space vector modulation scheme, for example. The present disclosure further describes an arrangement implementing the modulation method.
In space vector modulation, a multi-phase output voltage may be represented by a space vector, i.e. a single voltage vector rotating in a stationary alpha-beta (αβ) reference frame. A reference for a desired multi-phase output voltage or current may also be a vector. For example, in a three-phase converter system, three phase voltages vabc (=[va, vb, vc]T) in a stationary reference frame may be transformed to the αβ reference frame by using Clarke transformation T:
An αβ reference frame vector representation vref of the three-phase voltage references vabc is then:
v
ref
=Tv
abc. (2)
The operational states of the switches of the converter bridge are controlled to form predefined switching sets (i.e. predefined combinations of operational states of the switches). Each switching set represents a predefined output voltage vector, i.e. a space vector. The desired output voltage may be generated by controlling duty cycles of the space vectors. A duty cycle represents the percentage of time a space vector is active during a switching sequence. In this context, a switching sequence represents a sequence of duty cycles of output space vectors forming a full switching cycle.
FIG. 2 shows eight space vectors V0 to V7 for the exemplary two-level, three-phase converter bridge of FIG. 1. In FIG. 2, all eight space vectors are shown on the left. An enlarged view of sector 1 of the space vectors is shown on the right in FIG. 2. The space vectors, as well as a voltage reference vector Vref at angle θ, are shown in the stationary αβ reference frame in FIG. 2. In the two-level converter topology of FIG. 1, each converter leg can be in one of two operational states, and with all three converter legs, the converter can produce eight different switching sets and, thus, eight space vectors. The operational state of a converter leg where the upper switch is conducting (and the lower switch is non-conducting) is denoted a “high” or “1” state and the other state (where the upper switch is not conducting and the lower switch is conducting) is a “low” or “0” state. A converter leg may be controlled to either state on the basis of a converter leg control signal. The eight switching sets V0 to V7 are denoted with “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “11”, respectively, by using the same logic. The switching sets producing the space vectors V0 to V7 are shown in parenthesis next to the space vector references.
In FIG. 2, two of the space vectors (i.e. V0 and V7) are zero vectors that drive all phases to the same voltage potential (i.e. either to DC− or DC+). In other words, the zero vectors represent switching sets that do not generate voltage differences between any of the phases. The other six space vectors V1 to V6 are active vectors that drive the phases to different voltage potentials. In other words, at least one phase is driven to a different voltage potential from the other phases. The endpoints of the space vectors define triangular modulation sectors. Any output voltage within a modulation sector may be generated using the space vectors defining the sector. The sectors together define an area within which the space vectors are able to produce output voltages. Six such sectors are indicated by circled numbers 1-6 in FIG. 2.
The relation between a reference output voltage vector and the duty cycles of the space vectors may be represented by the following equations:
v
ref
=D
0
v
Z
+D
1
v
A,1
+D
2
v
A,2, (3)
D
0
+D
1
+D
2=1, (4)
where vz is one or both of the zero vectors V0 and V7, vA,1 and VA,2 represent two of the active vectors V1 to V6. D1 and D2 represent the duty cycle of the active vectors vA,4 and vA,2. D0 is the duty cycle of the zero vector vz.
The two active vectors may be considered to form a non-orthogonal coordinate system. A duty cycle for an active vector may then be represented by a projection of the output voltage on one active vector along the other active vector. The right-hand side of FIG. 2 shows an example of a voltage reference voltage being generated as a sum of a first active vector V1 and a second active vector V2. On the right-hand side of FIG. 2, the vector D1V1 represents the projection of the output voltage along the first axis D1. Thus, the duty cycle D1 for the active vector V1 can be calculated as a ratio between the projection and the first active vector V1. The duty cycle for the second active vector may be calculated in a similar manner. In FIG. 2, for example, the angle between two neighbouring active vectors is 60°. The duty cycles D1 to D2 for active vectors V1 and V2, respectively, may be calculated as follows:
When the duty cycles for the active vectors are known, the duty cycle from the zero vector(s) may be calculated from Equation (4). The actual turn-on and turn-off instants may then be calculated on the basis of the duty cycle and the length of the switching sequence.
A method according to the present disclosure is not limited only to space vector modulation. Other methods may be used for determining the duty cycles. For example, the duty cycles may be generated by using hysteresis control. Further, although the above embodiments discuss two-level converter bridges, a method according to the present disclosure may also be used with multi-level converters.
In a method according to the present disclosure, each parallel-connected power converter generates an output voltage vector by executing synchronized switching sequences that produce the above-described duty cycles. Each synchronized switching sequence comprises a first half sequence followed by a second half sequence. For example, a switching sequence producing an output voltage vector may be generated by using a first sequence type in which a turn-high half sequence (i.e. a rising-edge half sequence) comes before a turn-low half sequence (i.e. a falling-edge half sequence).
During the turn-high half sequence, the phase outputs may be switched high (i.e. set to a “high” state) in sequence. Switching a phase output high may be interpreted as connecting the phase output to a higher voltage potential. For example, in a two-level converter topology, switching a phase output high may mean disconnecting the phase output from the negative DC link potential and connecting it to the positive DC link potential.
During the turn-low half sequence, the phase outputs may be switched low in reverse sequence. Switching a phase output low may be interpreted as setting the phase to a “low” state, i.e. connecting the phase output to a lower voltage potential. For example, in a two-level converter topology, switching a phase output low may mean disconnecting the phase output from the positive DC link potential and connecting it to the negative DC link potential.
Alternatively, a switching sequence producing the same output voltage vector may be generated by using a second, complementary sequence type in which a rising-edge half sequence is performed after a falling-edge half sequence.
FIGS. 3a and 3b show exemplary switching sequences for sector 1 of FIG. 2. FIG. 3a shows a switching sequence using the first sequence type. The switching sequence comprises two half sequences: first a turn-high half sequence Shigh (shown as a white block) and then a turn-low half sequence Slow (shown as a hatched block). The switching sequence has length Tsw. FIG. 3a shows phase voltages va, vb, and vc being turned high during the turn-high half sequence Shigh. Duty cycles D1 and D2 of the active vectors correspond to the given reference. The zero duty cycle D0 may be divided equally between the two zero vectors V0 and V7 at both ends of a half sequence, as shown in FIG. 3a. In FIG. 3a, at switching instant Ta,high(=D0/2·Tsw/2), phase Va is turned high, i.e. set to a “high” state. At switching instant Tb,high(=Ta,high+D1·Tsw/2), phase Vb is turned high. At switching instant Tc,high(=Ta,high+Tb,high+D2·Tsw/2), phase Vc is turned high. FIG. 3a also shows phase voltages va, vh, and vc being turned low during the turn-low half sequence Slow.
FIG. 3b shows a switching sequence using the second, complementary sequence type for producing the same output voltage vector as in FIG. 3a. The switching sequence comprises two half sequences: first a turn-low half sequence Slow (shown as a hatched block) and then a turn-high half sequence Shigh (shown as a white block). The switching sequences shown in FIGS. 3a and 3b produce the same output voltage vectors.
In a method according to the present disclosure, switching sequences of at least two parallel-connected power converters may be generated such that both switching sequence types, i.e. the first type and the second type, are concurrently being used for producing output voltages. The synchronized switching sequences of at least one of the power converters may be such that the first half sequence is a rising-edge half sequence and the second half sequence is a falling-edge half sequence, and the synchronized switching sequences of at least one of the power converters may be such that the first half sequence is a falling-edge half sequence and the second half sequence is a rising-edge half sequence. In other words, for at least one of the converters, the switching sequences are generated by using a first sequence type in which a rising-edge half sequence is performed before a falling-edge half sequence and, for at least one of the converters, the switching sequences are generated by using a second, complementary sequence type in which a rising-edge half sequence is performed after a falling-edge half sequence.
As the first switching sequence type and the second switching sequence type produce the output voltage vector by activating the space vectors in a different order, the converters drive the switches in their converter bridges into differing switching sets, and the effective pulse frequency of the arrangement of parallel-connected converters is increased.
Since both the turn-high half sequence and the turn-low half sequence are capable of producing any desired modulation reference within the area defined by the modulation sectors, sampling of the reference may be asymmetrical. During a switching sequence, the turn-low sequence may use a different reference value than the turn-high sequence. Thus, the length of a control cycle of the modulation may equal the length of half of a switching sequence. The duty cycles may represent switching sets being used for a percentage of a half sequence. In order to calculate the duration that a space vector must be active, the duty cycle in question may simply be multiplied by the length of the half sequence.
In FIGS. 3a and 3b, the modulation references are represented by a reference voltage vector that has a first value vref,n at the beginning of the first half sequence (Shigh in FIG. 3a and Slow in FIG. 3b) in the switching sequence. However, when the first half sequence is finished, the reference is updated to a new value vref,n+1, and the duty cycles of the subsequent half sequence (Slow in FIG. 3a and Shigh in FIG. 3b) are based on the updated value vref,n+1.
In FIGS. 3a and 3b, the zero duty cycle is divided equally between the two zero vectors at both ends of a half sequence. This approach may be called continuous SVM. Alternatively, discontinuous SVM may be used. In one type of discontinuous SVM, only one of the zero vectors is used during a half sequence. As a result, the half sequences may be performed with only two switching events. However, the area defined by the modulation sectors is divided into discontinuous regions centred on the peak voltages. Within each such region, only one of the zero vectors is used.
FIG. 4 shows an example of the selection of the zero vectors V0 and V7 in the αβ plane, when using a discontinuous modulation strategy (i.e. only one zero vector during the switching sequence). The discontinuous region can be shifted by an arbitrary angle to track the peak current and achieve the maximum benefit. In FIG. 4, the reference voltage Vref is in a region where the zero vector V7 is used.
FIG. 5 shows an exemplary switching sequence in sector 1 of FIG. 4. In FIG. 5, phase voltages va, vh, and vc are turned high during a turn-high half sequence Shigh. The duty cycles D1 and D2 of the active vectors correspond to the given reference. FIG. 5 also shows phase voltages va, vb, and vc being turned low during the turn-low half sequence Slow. The reference voltage has a first value vref,n at the beginning of the turn-high half sequence Shigh. However, the duty cycles of the subsequent turn-low half sequence Slow are based on an updated value vref,n+1.
In a method according to the present disclosure, the switching sequences of the parallel-connected converters may be generated on the basis of a common modulation reference. The value of the reference may be periodically updated, and at the same time the synchronized switching sequences of complementary sequence types may be based on the same update of the value of the common modulation reference. The value of the modulation reference may be updated for each half sequence in a switching sequence. When the converters use the latest value of the common modulation reference for each half sequence of their switching sequences, good control response may also be achieved.
FIG. 6 shows exemplary synchronized switching sequences of complementary sequence types being generated on the basis of a common reference. In FIG. 6 at time instant t0, a first converter Conv 1 initiates a switching sequence according to the first sequence type and starts to produce a turn-high half sequence Shigh(vref,n) on the basis of an updated value vref,n of the common reference. At the same instant, a second converter Conv 2 initiates a complementary switching sequence according to the second sequence type and starts a turn-low half sequence Slow(vref,n) on the basis of the same updated value vref,n of the common reference. As the turn-high half sequence and the turn-low half sequence produce the output by activating the space vectors in a different order, the converters use differing switching sets, and the effective pulse frequency of the arrangement of parallel-connected converters is increased. At instant t1, the first half sequences Shigh(vref,n) and Slow(vref,n) finish, new value vref,n+1 is updated for the reference. Converter Conv 1 begins the second half sequence Slow(vref,n+1) and converter Conv 2 begins the second half sequence Shigh(vref,n+1). The second half sequences are based on the updated value vref,n+1 of the common reference.
The effective pulse frequency may be increased by initiating the synchronized switching sequences of the parallel-connected converters in a staggered manner. The initializations of the synchronized switching sequences of at least two of the power converters may have a first time interval between them, and the value of the modulation reference may be updated at the start of each synchronized switching sequence of each converter. Starting instants of the switching sequences may be evenly distributed, for example. In other words, the intervals separating the starting instants of the switching sequences may be equal. Further, having an interval between the starting times of the switching sequences may reduce common mode voltages which might emerge when converters using complementary half cycles simultaneously use different zero vectors that tie output phases of the converters to different potentials.
FIG. 7 shows exemplary synchronized switching sequences of three converters where the sequences are staggered, i.e. are initialized at set intervals. In FIG. 7, the time interval between the starting times of the sequences corresponds to a third of a half sequence. At instant t0, the reference is updated to value vref,n, and converter Conv 1 starts a switching sequence with a turn-high half sequence Shigh(vref,n). A third of a half sequence later, the reference is updated again, now to value vref,n+1, and converter Conv 3 starts a complementary switching sequence with a turn-low half sequence Slow(vref,n+n) type. A third of a half sequence later, the reference is updated yet again to value Vref,n+2, and converter Conv 2 starts a switching sequence with a turn-high half sequence Shigh(vref,n+2). In FIG. 7 at instant t1, converter Conv 1 finishes the first half of its switching sequence, the reference is updated to value vref,n+3, and converter Conv 1 starts the second half of the switching sequence with a turn-low half sequence. A third of a half sequence later, converter Conv 3 starts the second half of the switching sequence with a turn-high half sequence using value vref,n+4. A third of a half sequence later, converter Conv 2 starts the second half of the switching sequence with a turn-low half sequence using value value Vref,n+5.
FIG. 8 shows exemplary synchronized switching sequences of four converters. At time instant t0, a first converter Conv 1 initiates a switching sequence according to the first sequence type and starts to produce a turn-high half sequence Shigh(vref,n) on the basis of an updated value vref,n of the reference. At the same instant, a second converter Conv 3 initiates a complementary switching sequence according to the second sequence type and starts a turn-low half sequence Slow(vref,n) on the basis of the same updated value vref,n. A half of a half sequence later, the reference is updated to value vref,n+1, and converters Conv 2 and Conv 2 start their switching sequences based on the updated value vref,n+1.
In FIG. 8 at instant t1, converters Conv 1 and Conv 2 finish the first half of their switching sequences, the reference is updated to value Vref,n+2, and the converters start the second half of their switching sequences. A half of the length of a half sequence later, converters Conv 2 and Conv 4 start the second half of their switching sequences based on reference value vref,n+3.
The above embodiments relate to 2, 3, and 4 parallel-connected converters. However, a method according to the present disclosure is also applicable to any multitude of parallel-connected converters.
In some embodiments, the modulation reference and, thus, also the duty cycles from which the switching instants are calculated, may also be calculated more than once per half sequence. For example, the sequences may be updated any number of times during a half switching sequence. This may further increase the control responsiveness. On the other hand, additional logic may be necessary to ensure that none of the phase legs switch more than once per half switching sequence.
In a method according to the present disclosure, a single modulator system may be used for generating switching sequences for all power converters. The modulator system may generate the synchronized switching sequences for each parallel-connected power converter on the basis of a common modulation reference. The modulator system may be configured to generate the synchronized switching sequences so that for at least one of the converters, the first half sequence is a rising-edge half sequence and the second half sequence is a falling-edge half sequence, while for at least one of the other converters, the first half sequence is a falling-edge half sequence and the second half sequence is a rising-edge half sequence.
Staggering of the initialization of switching sequences of the parallel-connected converters may be accomplished by shifting the initialization by (a multiple of) the first time interval. Each converters individual switching instant values may be determined by adding the first time interval (or its multiple) to base switching instant values calculated directly from the duty cycles. Thus, the modulator system may comprise, for each power converter, adjustment means for determining individual switching instant values on the basis of the common modulation reference and the first time interval between power converters.
The modulator system may comprise a first periodic counter and a second periodic counter. The period of the first counter and the second counter may be the length of the synchronized switching sequence. The first and second counter may have a phase shift between each other. The phase shift may be half of the length of the switching sequence, for example.
The first half sequences in the synchronized switching sequences may be generated by using the first counter and the second half sequences in the synchronized switching sequences may be generated by using the second counter. The modulator system may comprise, for each power converter, modulator means configured to generate the first half sequences on the basis of a comparison between the first counter and the individual switching instant values and the second half sequences on the basis of a comparison between the second counter and the individual switching instant values.
For example, FIGS. 7 and 8 show two counters c1 and c2. Counters c1 and c2 in FIGS. 7 and 8 are increasing counters which are reset after counting to a value representing the length Tsw of a full switching sequence. The counters have a phase shift of half of the length Tsw of the switching sequence between each other. FIGS. 7 and 8 show counter c1 being reset at instant t0 and counter c2 being reset at instant t1. In FIGS. 7 and 8, the converters use counter c1 for generating the first halves of their switching sequences.
For example, at instant t0 in FIG. 7, a first converter Conv 1 starts a first half sequence Shigh(vref,n) at zero value of counter c1. The third converter Conv 3 initiates its first half sequence after a first time interval has passed. In this case, its first half sequence is a falling-edge half sequence. The switching instants may be determined by adding a value φ (representing the first time interval) to the switching instant values calculated from the duty cycles. In FIG. 7 these switching instant values are based on an updated value vref,n+1 of the modulation reference. Next, the second converter Conv 2 initiates its first half sequence, after the first time interval has passed again. The half sequence starts when the counter reaches value 2φ representing twice the first time interval. The switching instants are based on a new update vref,n+2 of the reference.
FIG. 9 shows an exemplary arrangement controlling at least two parallel-connected, multi-phase frequency converters. In FIG. 9, a modulator system 90 comprises a reference modulator 91 that generates the common modulation reference that defines reference switching instants T. The modulator system 90 further comprises an adjustment system 92 which generates, using a method according to the present disclosure, individual modulation references T1-TN for each parallel-connected converter 94.1-94.N, respectively.
In FIG. 9, the adjustment 92 system comprises the two counters having a phase shift between each other. The adjustment system 92 acts as the means for generating the first half sequences and the second half sequences. The adjustment system 92 calculates adjusted switching instants for each switch of each parallel-connected frequency converter by adding a value representing the time interval between the initialization instant of the switching sequence of the converter and the initialization of the common reference switching sequence with respect to the common modulation reference. The adjustment system 92 then generates the first and second half sequences by using the two counters and the adjusted switching instant values.
FIG. 10 shows an exemplary, simplified implementation for generating the first half sequences and the second half sequences of a three-phase converter. In FIG. 10, three modulator blocks 100a to 100c are shown.
Each modulator block 100a to 100c controls one phase output and comprises a first comparator (101a to 101c), a second comparator (102a to 102c), and a multiplexer (103a to 103c). Each modulator block receives a switching instant (Ta to Tc) and values of two counters c1 and c2 as inputs. The switching instants represent instants at which the phase is to be switched to a different potential, i.e. when a converter leg driving the phase will change its operational state, as shown in FIGS. 3a and 3b, for example.
The switching instants Ta to Tc may include a term representing (a multiple of) the first time interval between the switching cycles of the parallel-connected converters. The counters c1 and c2 are synchronized incrementing counters that have a period of the length TSW of a full switching sequence and a 180-degree phase shift between them. The counters may be similar to those shown in FIGS. 7 and 8, for example. The first comparators 101a-101c are used for comparing the value of a first counter c1 according to the present method with values of switching instants Ta to Tc, whereas the second comparators 102a to 102c are used for comparing the value of a second counter c2 according to the present method with values of switching instants Ta to Tc. The modulator blocks 100a to 100c generate converter leg control signals Sa to Sc on the basis of the comparator outputs.
In FIG. 10, the modulator blocks 100a to 100c generate the rising-edge half sequences on the basis of the first counter c1 and the falling-edge half sequences on the basis of the second counter c2. The switching instants Ta to Tc are connected to the negative inputs of the first comparators 101a to 101c, respectively. The switching instants Ta to Tc are also connected to the positive input of the second comparators 102a to 102c, respectively. As a result, when the first counter c1 exceeds the reference Ta, Tb or Tc, the output of the respective first comparator changes to a logic high (“1”) level. Correspondingly, when the second counter c2 exceeds the reference Ta, Tb or Tc, the output of the respective second comparator changes to a logic low (“0”) level.
In FIG. 10, the multiplexers 103a to 103c are used for selecting which comparator (i.e. the first comparator or the second comparator) in each modulator block drives the respective converter leg control signals Sa to Sc. A selection signal sel controls the multiplexers 103a-103c. The selection signal sel may be a clock signal having a period of the full switching sequence. The phase of the selection signal sel may be configured such that during the rising-edge half sequence, the selection signal sel may be set to logic “1”, and the outputs of the first comparators 101a to 101c drive the converter leg control signals Sa to Sc. During the falling-edge half sequence, the selection signal sel may be set to logic “0”, and the outputs of the second comparators 102a to 102c drive the converter leg control signals Sa to Sc.
In FIG. 10, the multiplexers are implemented by using two AND gates and an OR gate. The selection signal connects to a non-inverted input of one AND gate and to an inverted input of the other AND gate. The outputs of the first comparator and the second comparator connect to the second inputs of the AND gates. The outputs of the AND gates drive the inputs of the OR gate, and the output of the OR gate drives a converter leg control signal.
With the above-described two-counter approach, the switching frequency of the parallel-connected converters can easily be changed by changing the count-up limit of the counters and the period of the multiplexer control signal.
It will be obvious to a person skilled in the art that the inventive concept can be implemented in various ways. The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims.
The techniques described herein may be implemented by various means so that an apparatus implementing one or more functions described with an embodiment comprises not only prior art means, but also specific means for implementing the one or more functions described with an embodiment, and it may comprise separate means for each separate function, or specific means may be configured to perform two or more functions. The specific means may be software and/or software-hardware and/or hardware and/or firmware components (recorded indelibly on a medium such as read-only-memory or embodied in hard-wired computer circuitry) or combinations thereof. Software codes may be stored in any suitable processor/computer-readable data storage medium(s) or memory unit(s) or article(s) of manufacture and executed by one or more processors/computers, hardware (one or more apparatuses), firmware (one or more apparatuses), software (one or more modules), or combinations thereof. For a firmware or software, implementation can be through modules (e.g. procedures, functions, and so on) that perform the functions described herein.
Patent Application
20170063247
